| Message ID | 1447713335-29707-1-git-send-email-yang.shi@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Mon, Nov 16, 2015 at 2:35 PM, Yang Shi <yang.shi@linaro.org> wrote: > Save and restore FP/LR in BPF prog prologue and epilogue, save SP to FP > in prologue in order to get the correct stack backtrace. > > However, ARM64 JIT used FP (x29) as eBPF fp register, FP is subjected to > change during function call so it may cause the BPF prog stack base address > change too. > > Use x25 to replace FP as BPF stack base register (fp). Since x25 is callee > saved register, so it will keep intact during function call. > It is initialized in BPF prog prologue when BPF prog is started to run > everytime. Save and restore x25/x26 in BPF prologue and epilogue to keep > them intact for the outside of BPF. Actually, x26 is unnecessary, but SP > requires 16 bytes alignment. > > So, the BPF stack layout looks like: > > high > original A64_SP => 0:+-----+ BPF prologue > |FP/LR| > current A64_FP => -16:+-----+ > | ... | callee saved registers > +-----+ > | | x25/x26 > BPF fp register => -80:+-----+ > | | > | ... | BPF prog stack > | | > | | > current A64_SP => +-----+ > | | > | ... | Function call stack > | | > +-----+ > low > > CC: Zi Shen Lim <zlim.lnx@gmail.com> > CC: Xi Wang <xi.wang@gmail.com> > Signed-off-by: Yang Shi <yang.shi@linaro.org> Acked-by: Zi Shen Lim <zlim.lnx@gmail.com>
On Mon, Nov 16, 2015 at 08:37:11PM -0800, Z Lim wrote: > On Mon, Nov 16, 2015 at 2:35 PM, Yang Shi <yang.shi@linaro.org> wrote: > > Save and restore FP/LR in BPF prog prologue and epilogue, save SP to FP > > in prologue in order to get the correct stack backtrace. ... > > CC: Zi Shen Lim <zlim.lnx@gmail.com> > > CC: Xi Wang <xi.wang@gmail.com> > > Signed-off-by: Yang Shi <yang.shi@linaro.org> > > Acked-by: Zi Shen Lim <zlim.lnx@gmail.com> great that it's finalized. Yang, please resubmit both patches to netdev as fresh submission so it gets picked up by patchwork.
On 11/16/2015 8:41 PM, Alexei Starovoitov wrote: > On Mon, Nov 16, 2015 at 08:37:11PM -0800, Z Lim wrote: >> On Mon, Nov 16, 2015 at 2:35 PM, Yang Shi <yang.shi@linaro.org> wrote: >>> Save and restore FP/LR in BPF prog prologue and epilogue, save SP to FP >>> in prologue in order to get the correct stack backtrace. > ... >>> CC: Zi Shen Lim <zlim.lnx@gmail.com> >>> CC: Xi Wang <xi.wang@gmail.com> >>> Signed-off-by: Yang Shi <yang.shi@linaro.org> >> >> Acked-by: Zi Shen Lim <zlim.lnx@gmail.com> > > great that it's finalized. > Yang, please resubmit both patches to netdev as fresh submission so it > gets picked up by patchwork. OK, btw the first one has been applied by David. Yang >
From: Alexei Starovoitov <alexei.starovoitov@gmail.com> Date: Mon, 16 Nov 2015 20:41:46 -0800 > On Mon, Nov 16, 2015 at 08:37:11PM -0800, Z Lim wrote: >> On Mon, Nov 16, 2015 at 2:35 PM, Yang Shi <yang.shi@linaro.org> wrote: >> > Save and restore FP/LR in BPF prog prologue and epilogue, save SP to FP >> > in prologue in order to get the correct stack backtrace. > ... >> > CC: Zi Shen Lim <zlim.lnx@gmail.com> >> > CC: Xi Wang <xi.wang@gmail.com> >> > Signed-off-by: Yang Shi <yang.shi@linaro.org> >> >> Acked-by: Zi Shen Lim <zlim.lnx@gmail.com> > > great that it's finalized. > Yang, please resubmit both patches to netdev as fresh submission so it > gets picked up by patchwork. He doesn't need to, I applied patch #1 independently the other day while the details of #2 were being worked out.
From: Yang Shi <yang.shi@linaro.org> Date: Mon, 16 Nov 2015 14:35:35 -0800 > Save and restore FP/LR in BPF prog prologue and epilogue, save SP to FP > in prologue in order to get the correct stack backtrace. > > However, ARM64 JIT used FP (x29) as eBPF fp register, FP is subjected to > change during function call so it may cause the BPF prog stack base address > change too. > > Use x25 to replace FP as BPF stack base register (fp). Since x25 is callee > saved register, so it will keep intact during function call. > It is initialized in BPF prog prologue when BPF prog is started to run > everytime. Save and restore x25/x26 in BPF prologue and epilogue to keep > them intact for the outside of BPF. Actually, x26 is unnecessary, but SP > requires 16 bytes alignment. > > So, the BPF stack layout looks like: ... > Signed-off-by: Yang Shi <yang.shi@linaro.org> Applied, thank you.
diff --git a/arch/arm64/net/bpf_jit_comp.c b/arch/arm64/net/bpf_jit_comp.c index ac8b548..86a3253 100644 --- a/arch/arm64/net/bpf_jit_comp.c +++ b/arch/arm64/net/bpf_jit_comp.c @@ -50,7 +50,7 @@ static const int bpf2a64[] = { [BPF_REG_8] = A64_R(21), [BPF_REG_9] = A64_R(22), /* read-only frame pointer to access stack */ - [BPF_REG_FP] = A64_FP, + [BPF_REG_FP] = A64_R(25), /* temporary register for internal BPF JIT */ [TMP_REG_1] = A64_R(23), [TMP_REG_2] = A64_R(24), @@ -155,16 +155,47 @@ static void build_prologue(struct jit_ctx *ctx) stack_size += 4; /* extra for skb_copy_bits buffer */ stack_size = STACK_ALIGN(stack_size); + /* + * BPF prog stack layout + * + * high + * original A64_SP => 0:+-----+ BPF prologue + * |FP/LR| + * current A64_FP => -16:+-----+ + * | ... | callee saved registers + * +-----+ + * | | x25/x26 + * BPF fp register => -80:+-----+ + * | | + * | ... | BPF prog stack + * | | + * | | + * current A64_SP => +-----+ + * | | + * | ... | Function call stack + * | | + * +-----+ + * low + * + */ + + /* Save FP and LR registers to stay align with ARM64 AAPCS */ + emit(A64_PUSH(A64_FP, A64_LR, A64_SP), ctx); + emit(A64_MOV(1, A64_FP, A64_SP), ctx); + /* Save callee-saved register */ emit(A64_PUSH(r6, r7, A64_SP), ctx); emit(A64_PUSH(r8, r9, A64_SP), ctx); if (ctx->tmp_used) emit(A64_PUSH(tmp1, tmp2, A64_SP), ctx); - /* Set up frame pointer */ + /* Save fp (x25) and x26. SP requires 16 bytes alignment */ + emit(A64_PUSH(fp, A64_R(26), A64_SP), ctx); + + /* Set up BPF prog stack base register (x25) */ emit(A64_MOV(1, fp, A64_SP), ctx); - /* Set up BPF stack */ + /* Set up function call stack */ emit(A64_SUB_I(1, A64_SP, A64_SP, stack_size), ctx); /* Clear registers A and X */ @@ -190,14 +221,17 @@ static void build_epilogue(struct jit_ctx *ctx) /* We're done with BPF stack */ emit(A64_ADD_I(1, A64_SP, A64_SP, stack_size), ctx); + /* Restore fs (x25) and x26 */ + emit(A64_POP(fp, A64_R(26), A64_SP), ctx); + /* Restore callee-saved register */ if (ctx->tmp_used) emit(A64_POP(tmp1, tmp2, A64_SP), ctx); emit(A64_POP(r8, r9, A64_SP), ctx); emit(A64_POP(r6, r7, A64_SP), ctx); - /* Restore frame pointer */ - emit(A64_MOV(1, fp, A64_SP), ctx); + /* Restore FP/LR registers */ + emit(A64_POP(A64_FP, A64_LR, A64_SP), ctx); /* Set return value */ emit(A64_MOV(1, A64_R(0), r0), ctx);
Save and restore FP/LR in BPF prog prologue and epilogue, save SP to FP in prologue in order to get the correct stack backtrace. However, ARM64 JIT used FP (x29) as eBPF fp register, FP is subjected to change during function call so it may cause the BPF prog stack base address change too. Use x25 to replace FP as BPF stack base register (fp). Since x25 is callee saved register, so it will keep intact during function call. It is initialized in BPF prog prologue when BPF prog is started to run everytime. Save and restore x25/x26 in BPF prologue and epilogue to keep them intact for the outside of BPF. Actually, x26 is unnecessary, but SP requires 16 bytes alignment. So, the BPF stack layout looks like: high original A64_SP => 0:+-----+ BPF prologue |FP/LR| current A64_FP => -16:+-----+ | ... | callee saved registers +-----+ | | x25/x26 BPF fp register => -80:+-----+ | | | ... | BPF prog stack | | | | current A64_SP => +-----+ | | | ... | Function call stack | | +-----+ low CC: Zi Shen Lim <zlim.lnx@gmail.com> CC: Xi Wang <xi.wang@gmail.com> Signed-off-by: Yang Shi <yang.shi@linaro.org> --- V4 --> V3: * Save/restore x25 and x26 V3 --> V2: * Make FP point to FP' * Fix a compile warning arch/arm64/net/bpf_jit_comp.c | 44 ++++++++++++++++++++++++++++++++++++++----- 1 file changed, 39 insertions(+), 5 deletions(-)