| Message ID | 564C94FD.60607@sigmadesigns.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Marc Gonzalez <marc_gonzalez@sigmadesigns.com> writes: > + clkgen: clkgen@10000 { > + compatible = "sigma,tango4-clkgen"; > + reg = <0x10000 0x40>; > + clocks = <&xtal>; > + clock-output-names = "cpuclk", "sysclk"; > + #clock-cells = <1>; > + }; Would you please consider using my clock driver that matches the actual hardware, supports all the clock outputs required for USB, SATA, etc, and works on tango3 as well?
On 18/11/2015 17:05, Måns Rullgård wrote: > Marc Gonzalez wrote: > >> + clkgen: clkgen@10000 { >> + compatible = "sigma,tango4-clkgen"; >> + reg = <0x10000 0x40>; >> + clocks = <&xtal>; >> + clock-output-names = "cpuclk", "sysclk"; >> + #clock-cells = <1>; >> + }; > > Would you please consider using my clock driver that matches the actual > hardware, supports all the clock outputs required for USB, SATA, etc, > and works on tango3 as well? I was hoping to take baby steps to work up to a fully-functional port. The first step (in my mind) is this submission: a minimal port which only requires the two "main" clocks. The next step will add to the minimal port by supporting as many peripherals as possible, as well as their required clocks. Would you agree to discuss the clkgen driver in a few weeks, when I can concentrate full-time on the subject? Working on other drivers will give me a better understanding of the required clocks. I've also been talking internally with our firmware writers, and with the clk maintainers to get a better picture of the whole mess. (Note that the next chip will come with a brand new clkgen block, much more sane.) Regards.
Marc Gonzalez <marc_gonzalez@sigmadesigns.com> writes: > On 18/11/2015 17:05, Måns Rullgård wrote: > >> Marc Gonzalez wrote: >> >>> + clkgen: clkgen@10000 { >>> + compatible = "sigma,tango4-clkgen"; >>> + reg = <0x10000 0x40>; >>> + clocks = <&xtal>; >>> + clock-output-names = "cpuclk", "sysclk"; >>> + #clock-cells = <1>; >>> + }; >> >> Would you please consider using my clock driver that matches the actual >> hardware, supports all the clock outputs required for USB, SATA, etc, >> and works on tango3 as well? > > I was hoping to take baby steps to work up to a fully-functional port. > The first step (in my mind) is this submission: a minimal port which > only requires the two "main" clocks. > > The next step will add to the minimal port by supporting as many > peripherals as possible, as well as their required clocks. But the code already exists. Why start over? > Would you agree to discuss the clkgen driver in a few weeks, when I can > concentrate full-time on the subject? Working on other drivers will give > me a better understanding of the required clocks. Perhaps it's premature to be pushing this as anything more than an RFC at this stage.
On Wed, Nov 18, 2015 at 8:38 AM, Måns Rullgård <mans@mansr.com> wrote: > Marc Gonzalez <marc_gonzalez@sigmadesigns.com> writes: > >> On 18/11/2015 17:05, Måns Rullgård wrote: >> >>> Marc Gonzalez wrote: >>> >>>> + clkgen: clkgen@10000 { >>>> + compatible = "sigma,tango4-clkgen"; >>>> + reg = <0x10000 0x40>; >>>> + clocks = <&xtal>; >>>> + clock-output-names = "cpuclk", "sysclk"; >>>> + #clock-cells = <1>; >>>> + }; >>> >>> Would you please consider using my clock driver that matches the actual >>> hardware, supports all the clock outputs required for USB, SATA, etc, >>> and works on tango3 as well? >> >> I was hoping to take baby steps to work up to a fully-functional port. >> The first step (in my mind) is this submission: a minimal port which >> only requires the two "main" clocks. >> >> The next step will add to the minimal port by supporting as many >> peripherals as possible, as well as their required clocks. > > But the code already exists. Why start over? Måns, I don't understand your role in this. Can you clarify? If you've already done a port, why haven't you contributed it yourself? Why are you driving Marc's work from the back seat like this instead of submitting your own work? If Marc prefers to start with a minimal implementation, that's just fine with me. -Olof
Olof Johansson <olof@lixom.net> writes: > On Wed, Nov 18, 2015 at 8:38 AM, Måns Rullgård <mans@mansr.com> wrote: >> Marc Gonzalez <marc_gonzalez@sigmadesigns.com> writes: >> >>> On 18/11/2015 17:05, Måns Rullgård wrote: >>> >>>> Marc Gonzalez wrote: >>>> >>>>> + clkgen: clkgen@10000 { >>>>> + compatible = "sigma,tango4-clkgen"; >>>>> + reg = <0x10000 0x40>; >>>>> + clocks = <&xtal>; >>>>> + clock-output-names = "cpuclk", "sysclk"; >>>>> + #clock-cells = <1>; >>>>> + }; >>>> >>>> Would you please consider using my clock driver that matches the actual >>>> hardware, supports all the clock outputs required for USB, SATA, etc, >>>> and works on tango3 as well? >>> >>> I was hoping to take baby steps to work up to a fully-functional port. >>> The first step (in my mind) is this submission: a minimal port which >>> only requires the two "main" clocks. >>> >>> The next step will add to the minimal port by supporting as many >>> peripherals as possible, as well as their required clocks. >> >> But the code already exists. Why start over? > > Måns, I don't understand your role in this. Can you clarify? Oh, I'm just the guy who did all the work and then got screwed over by Sigma. > If you've already done a port, why haven't you contributed it > yourself? Because it's not yet in a shape to be contributed, just like Marc's isn't. > Why are you driving Marc's work from the back seat like this instead > of submitting your own work? I have submitted bits and pieces. It's a slow process.
Måns Rullgård wrote: > Olof Johansson wrote: > >> Måns Rullgård wrote: >> >>> Marc Gonzalez wrote: >>> >>>> Måns Rullgård wrote: >>>> >>>>> Marc Gonzalez wrote: >>>>> >>>>>> + clkgen: clkgen@10000 { >>>>>> + compatible = "sigma,tango4-clkgen"; >>>>>> + reg = <0x10000 0x40>; >>>>>> + clocks = <&xtal>; >>>>>> + clock-output-names = "cpuclk", "sysclk"; >>>>>> + #clock-cells = <1>; >>>>>> + }; >>>>> >>>>> Would you please consider using my clock driver that matches the actual >>>>> hardware, supports all the clock outputs required for USB, SATA, etc, >>>>> and works on tango3 as well? >>>> >>>> I was hoping to take baby steps to work up to a fully-functional port. >>>> The first step (in my mind) is this submission: a minimal port which >>>> only requires the two "main" clocks. >>>> >>>> The next step will add to the minimal port by supporting as many >>>> peripherals as possible, as well as their required clocks. >>> >>> But the code already exists. Why start over? "La perfection est atteinte, non pas lorsqu'il n'y a plus rien à ajouter, mais lorsqu'il n'y a plus rien à retirer." For example, what is the point of not ignoring sysclk_premux, when the boot loader has always hard-coded "PLL1 drives sys_clk, PLL2 drives cd_clk". Having one clk driver for tango3, and another for tango4 allows you to submit your own tango3 clk driver, and I can then ignore all the insane tango3 clk legacy, and focus on the tango4 clean-ups. Would that work for you? (BTW, are you aware that the clk maintainers will NAK your clk driver in its current form, based on the fact that they insist on a single node for the entire clkgen block?) >> Måns, I don't understand your role in this. Can you clarify? > > Oh, I'm just the guy who did all the work and then got screwed over by > Sigma. Here's the sequence of events, to the best of my recollection. In 2010, you hacked the Popcorn Hour C-200 (Tango3 SoC) In 2014-11, I mentioned on LAKML that I planned to upstream Sigma's kernel In 2014-12, you pushed your tango3 port to github (3.18 at the time IIRC) https://github.com/mansr/linux-tangox In late 2015-02, you blogged about your work http://hardwarebug.org/2015/02/26/popcorn-hour-revisited/ I contacted you the next day, and you offered your services. You met management in late March. Then radio silence for several months. Sometime in July, I was told the deal had fallen apart :-( >> If you've already done a port, why haven't you contributed it >> yourself? > > Because it's not yet in a shape to be contributed, just like Marc's > isn't. Are you saying the DT needs to be perfect on the first submission? Has this been true for other mach? >> Why are you driving Marc's work from the back seat like this instead >> of submitting your own work? > > I have submitted bits and pieces. It's a slow process. Indeed. Especially when a maintainer NAKs a patch because one used 'unsigned' instead of 'unsigned int'. Regards.
Marc Gonzalez <marc_gonzalez@sigmadesigns.com> writes: > Måns Rullgård wrote: > >> Olof Johansson wrote: >> >>> Måns Rullgård wrote: >>> >>>> Marc Gonzalez wrote: >>>> >>>>> Måns Rullgård wrote: >>>>> >>>>>> Marc Gonzalez wrote: >>>>>> >>>>>>> + clkgen: clkgen@10000 { >>>>>>> + compatible = "sigma,tango4-clkgen"; >>>>>>> + reg = <0x10000 0x40>; >>>>>>> + clocks = <&xtal>; >>>>>>> + clock-output-names = "cpuclk", "sysclk"; >>>>>>> + #clock-cells = <1>; >>>>>>> + }; >>>>>> >>>>>> Would you please consider using my clock driver that matches the actual >>>>>> hardware, supports all the clock outputs required for USB, SATA, etc, >>>>>> and works on tango3 as well? >>>>> >>>>> I was hoping to take baby steps to work up to a fully-functional port. >>>>> The first step (in my mind) is this submission: a minimal port which >>>>> only requires the two "main" clocks. >>>>> >>>>> The next step will add to the minimal port by supporting as many >>>>> peripherals as possible, as well as their required clocks. >>>> >>>> But the code already exists. Why start over? > > "La perfection est atteinte, non pas lorsqu'il n'y a plus rien à ajouter, > mais lorsqu'il n'y a plus rien à retirer." > > For example, what is the point of not ignoring sysclk_premux, when the boot > loader has always hard-coded "PLL1 drives sys_clk, PLL2 drives cd_clk". What if the boot loader changes? Since we know the structure of the clock tree, it's safer to check how it is actually configured. > Having one clk driver for tango3, and another for tango4 allows you to > submit your own tango3 clk driver, and I can then ignore all the insane > tango3 clk legacy, and focus on the tango4 clean-ups. Would that work > for you? That would be a complete waste. > (BTW, are you aware that the clk maintainers will NAK your clk driver in > its current form, based on the fact that they insist on a single node > for the entire clkgen block?) Yes, I know that. It's the third or fourth time they've completely changed the preferred way of doing clocks. >>> Måns, I don't understand your role in this. Can you clarify? >> >> Oh, I'm just the guy who did all the work and then got screwed over by >> Sigma. > > Here's the sequence of events, to the best of my recollection. > > In 2010, you hacked the Popcorn Hour C-200 (Tango3 SoC) > In 2014-11, I mentioned on LAKML that I planned to upstream Sigma's kernel > In 2014-12, you pushed your tango3 port to github (3.18 at the time IIRC) > https://github.com/mansr/linux-tangox > In late 2015-02, you blogged about your work > http://hardwarebug.org/2015/02/26/popcorn-hour-revisited/ > I contacted you the next day, and you offered your services. > You met management in late March. > Then radio silence for several months. > Sometime in July, I was told the deal had fallen apart :-( Something like that, yes. I'd be less upset with them if there hadn't been promises made only to be followed by lame excuses and stonewalling. >>> If you've already done a port, why haven't you contributed it >>> yourself? >> >> Because it's not yet in a shape to be contributed, just like Marc's >> isn't. > > Are you saying the DT needs to be perfect on the first submission? > Has this been true for other mach? There's this notion of "DT is ABI" and must be stable. Changing existing bindings is strongly frowned upon. >>> Why are you driving Marc's work from the back seat like this instead >>> of submitting your own work? >> >> I have submitted bits and pieces. It's a slow process. > > Indeed. Especially when a maintainer NAKs a patch because one used > 'unsigned' instead of 'unsigned int'. That I can live with. It's more frustrating to have at least a day of turnaround time for each nitpick like that. Oh well. At least the serial port support is upstream. That's a start.
Marc Gonzalez <marc_gonzalez@sigmadesigns.com> writes: > Måns Rullgård wrote: > >> Marc Gonzalez wrote: >> >>> For example, what is the point of not ignoring sysclk_premux, when the boot >>> loader has always hard-coded "PLL1 drives sys_clk, PLL2 drives cd_clk". >> >> What if the boot loader changes? Since we know the structure of the >> clock tree, it's safer to check how it is actually configured. > > In my opinion, this might be the problem. > > You think you grok the clkgen block, based on > > 1) buggy driver code written by Sigma > 2) obsolete and/or incorrect documentation (it mentions tango1 for crying out loud) > 3) limited testing on 8642 and 8759 I also have documentation for SMP8654 that I found on some Chinese web site. I've played around with most of the controls, and things behave as expected. Where the Sigma code and documentation are ambiguous or disagree, I have tested what the hardware actually does for various values.
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 246473a244f6..2499295051d5 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -605,6 +605,8 @@ dtb-$(CONFIG_MACH_SUN8I) += \ dtb-$(CONFIG_MACH_SUN9I) += \ sun9i-a80-optimus.dtb \ sun9i-a80-cubieboard4.dtb +dtb-$(CONFIG_ARCH_TANGOX) += \ + tango4-vantage-1172.dtb dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \ tegra20-harmony.dtb \ tegra20-iris-512.dtb \ diff --git a/arch/arm/boot/dts/tango4-common.dtsi b/arch/arm/boot/dts/tango4-common.dtsi new file mode 100644 index 000000000000..2a49aeea137f --- /dev/null +++ b/arch/arm/boot/dts/tango4-common.dtsi @@ -0,0 +1,121 @@ +/* + * Based on Mans Rullgard's Tango3 DT + * https://github.com/mansr/linux-tangox + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + scu: scu@20000000 { + compatible = "arm,cortex-a9-scu"; + reg = <0x20000000 0x100>; + }; + + gic: interrupt-controller@20001000 { + compatible = "arm,cortex-a9-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x20001000 0x1000>, <0x20000100 0x0100>; + }; + + periphclk: periphclk { + compatible = "fixed-factor-clock"; + clocks = <&clkgen 0>; + clock-mult = <1>; + clock-div = <2>; + #clock-cells = <0>; + }; + + twd-timer@20000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x20000600 0x10>; + interrupts = <GIC_PPI 13 0xf04>; + clocks = <&periphclk>; + always-on; + }; + + l2cc: l2-cache-controller@20100000 { + compatible = "arm,pl310-cache"; + reg = <0x20100000 0x1000>; + cache-level = <2>; + cache-unified; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&irq0>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + xtal: xtal { + compatible = "fixed-clock"; + clock-frequency = <27000000>; + #clock-cells = <0>; + }; + + clkgen: clkgen@10000 { + compatible = "sigma,tango4-clkgen"; + reg = <0x10000 0x40>; + clocks = <&xtal>; + clock-output-names = "cpuclk", "sysclk"; + #clock-cells = <1>; + }; + + tick-counter@10048 { + compatible = "sigma,tick-counter"; + reg = <0x10048 0x4>; + clocks = <&xtal>; + }; + + uart: serial@10700 { + compatible = "ralink,rt2880-uart"; + reg = <0x10700 0x30>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <7372800>; + reg-shift = <2>; + }; + + eth0: ethernet@26000 { + compatible = "sigma,smp8734-ethernet"; + reg = <0x26000 0x800>; + interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkgen 1>; + }; + + intc: interrupt-controller@6e000 { + compatible = "sigma,smp8642-intc"; + reg = <0x6e000 0x400>; + ranges = <0 0x6e000 0x400>; + interrupt-parent = <&gic>; + interrupt-controller; + #address-cells = <1>; + #size-cells = <1>; + + irq0: irq0@000 { + reg = <0x000 0x100>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + }; + + irq1: irq1@100 { + reg = <0x100 0x100>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + }; + + irq2: irq2@300 { + reg = <0x300 0x100>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/tango4-smp8758.dtsi b/arch/arm/boot/dts/tango4-smp8758.dtsi new file mode 100644 index 000000000000..7ed88ee629fb --- /dev/null +++ b/arch/arm/boot/dts/tango4-smp8758.dtsi @@ -0,0 +1,31 @@ +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "sigma,tango4-smp"; + + cpu0: cpu@0 { + compatible = "arm,cortex-a9"; + next-level-cache = <&l2cc>; + device_type = "cpu"; + reg = <0>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a9"; + next-level-cache = <&l2cc>; + device_type = "cpu"; + reg = <1>; + }; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupt-affinity = <&cpu0>, <&cpu1>; + interrupts = + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + }; +}; diff --git a/arch/arm/boot/dts/tango4-vantage-1172.dts b/arch/arm/boot/dts/tango4-vantage-1172.dts new file mode 100644 index 000000000000..babe69a79c37 --- /dev/null +++ b/arch/arm/boot/dts/tango4-vantage-1172.dts @@ -0,0 +1,29 @@ +/dts-v1/; + +#include "tango4-smp8758.dtsi" +#include "tango4-common.dtsi" + +/ { + model = "Sigma Designs SMP8758 Vantage-1172 Rev E1"; + compatible = "sigma,vantage-1172", "sigma,smp8758", "sigma,tango4"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x80000000>; /* 2 GB */ + }; +}; + +ð0 { + phy-connection-type = "rgmii"; + phy-handle = <ð0_phy>; + #address-cells = <1>; + #size-cells = <0>; + + /* Atheros AR8035 */ + eth0_phy: ethernet-phy@4 { + compatible = "ethernet-phy-id004d.d072", + "ethernet-phy-ieee802.3-c22"; + interrupts = <37 IRQ_TYPE_EDGE_RISING>; + reg = <4>; + }; +};
This device tree was tested on a Sigma Designs SMP8758 Vantage-1172 development board. Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com> --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/tango4-common.dtsi | 121 ++++++++++++++++++++++++++++++ arch/arm/boot/dts/tango4-smp8758.dtsi | 31 ++++++++ arch/arm/boot/dts/tango4-vantage-1172.dts | 29 +++++++ 4 files changed, 183 insertions(+) create mode 100644 arch/arm/boot/dts/tango4-common.dtsi create mode 100644 arch/arm/boot/dts/tango4-smp8758.dtsi create mode 100644 arch/arm/boot/dts/tango4-vantage-1172.dts