| Message ID | 1447970832-774-1-git-send-email-moritz.fischer@ettus.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
?On 19-11-15 23:07, Moritz Fischer wrote: > Replaced constant clock_{enable,disable} calls with pm_runtime > hooks for suspend and resume to avoid constant clk_enable / > clk_disable. > > Acked-by: Alan Tull <atull@opensource.altera.com> > Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> > --- > Changes: > > v1: > - Removed superfluous #ifdef CONFIG_PM as suggested by Michal > - Changed commit message to include suspend / resume > - Added Alan's Acked-by > > drivers/fpga/zynq-fpga.c | 76 +++++++++++++++++++++++++++++++++++++----------- > 1 file changed, 59 insertions(+), 17 deletions(-) > > diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c > index c2fb412..3f5469d 100644 > --- a/drivers/fpga/zynq-fpga.c > +++ b/drivers/fpga/zynq-fpga.c > @@ -28,6 +28,7 @@ > #include <linux/of_address.h> > #include <linux/of_irq.h> > #include <linux/pm.h> > +#include <linux/pm_runtime.h> > #include <linux/regmap.h> > #include <linux/string.h> > > @@ -184,8 +185,8 @@ static int zynq_fpga_ops_write_init(struct fpga_manager *mgr, u32 flags, > > priv = mgr->priv; > > - err = clk_enable(priv->clk); > - if (err) > + err = pm_runtime_get_sync(priv->dev); > + if (err < 0) > return err; > > /* don't globally reset PL if we're doing partial reconfig */ > @@ -271,12 +272,12 @@ static int zynq_fpga_ops_write_init(struct fpga_manager *mgr, u32 flags, > ctrl = zynq_fpga_read(priv, MCTRL_OFFSET); > zynq_fpga_write(priv, MCTRL_OFFSET, (~MCTRL_PCAP_LPBK_MASK & ctrl)); > > - clk_disable(priv->clk); > + pm_runtime_put(priv->dev); > > return 0; > > out_err: > - clk_disable(priv->clk); > + pm_runtime_put(priv->dev); > > return err; > } > @@ -301,9 +302,8 @@ static int zynq_fpga_ops_write(struct fpga_manager *mgr, > > memcpy(kbuf, buf, count); > > - /* enable clock */ > - err = clk_enable(priv->clk); > - if (err) > + err = pm_runtime_get_sync(priv->dev); > + if (err < 0) > goto out_free; > > zynq_fpga_write(priv, INT_STS_OFFSET, IXR_ALL_MASK); > @@ -335,7 +335,7 @@ static int zynq_fpga_ops_write(struct fpga_manager *mgr, > err = -EFAULT; > } > > - clk_disable(priv->clk); > + pm_runtime_put(priv->dev); > > out_free: > dma_free_coherent(priv->dev, in_count, kbuf, dma_addr); > @@ -349,8 +349,8 @@ static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr, u32 flags) > int err; > u32 intr_status; > > - err = clk_enable(priv->clk); > - if (err) > + err = pm_runtime_get_sync(priv->dev); > + if (err < 0) > return err; > > err = zynq_fpga_poll_timeout(priv, INT_STS_OFFSET, intr_status, > @@ -358,7 +358,7 @@ static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr, u32 flags) > INIT_POLL_DELAY, > INIT_POLL_TIMEOUT); > > - clk_disable(priv->clk); > + pm_runtime_put(priv->dev); > > if (err) > return err; > @@ -385,12 +385,12 @@ static enum fpga_mgr_states zynq_fpga_ops_state(struct fpga_manager *mgr) > > priv = mgr->priv; > > - err = clk_enable(priv->clk); > - if (err) > + err = pm_runtime_get_sync(priv->dev); > + if (err < 0) > return FPGA_MGR_STATE_UNKNOWN; > > intr_status = zynq_fpga_read(priv, INT_STS_OFFSET); > - clk_disable(priv->clk); > + pm_runtime_put(priv->dev); > > if (intr_status & IXR_PCFG_DONE_MASK) > return FPGA_MGR_STATE_OPERATING; > @@ -457,19 +457,26 @@ static int zynq_fpga_probe(struct platform_device *pdev) > return err; > } > > + pm_runtime_get_noresume(&pdev->dev); > + pm_runtime_set_active(&pdev->dev); > + pm_runtime_enable(&pdev->dev); > + > /* unlock the device */ > zynq_fpga_write(priv, UNLOCK_OFFSET, UNLOCK_MASK); > > - clk_disable(priv->clk); > > err = fpga_mgr_register(dev, "Xilinx Zynq FPGA Manager", > &zynq_fpga_ops, priv); > if (err) { > dev_err(dev, "unable to register FPGA manager"); > - clk_unprepare(priv->clk); > + clk_disable_unprepare(priv->clk); > + pm_runtime_put_noidle(&pdev->dev); > + pm_runtime_disable(&pdev->dev); > return err; > } > > + pm_runtime_put(&pdev->dev); > + > return 0; > } > > @@ -483,11 +490,45 @@ static int zynq_fpga_remove(struct platform_device *pdev) > > fpga_mgr_unregister(&pdev->dev); > > - clk_unprepare(priv->clk); > + pm_runtime_get_sync(&pdev->dev); > + clk_disable_unprepare(priv->clk); > + pm_runtime_put_noidle(&pdev->dev); > + pm_runtime_disable(&pdev->dev); > > return 0; > } > > +static int __maybe_unused zynq_fpga_runtime_suspend(struct device *dev) > +{ > + struct zynq_fpga_priv *priv; > + struct fpga_manager *mgr; > + > + mgr = dev_get_drvdata(dev); > + priv = mgr->priv; > + > + clk_disable(priv->clk); From what I understand, this call is done in a sleepable context, so you can use clk_disable_unprepare here (and its counterpart in resume). And remove the prepare at probe time and unprepare at removal. Not all clocks can implement atomic enable/disable, for example I2C and SPI controlled clocks only implement the prepare/unprepare routines. I guess the "clk" here will always be a SOC provided one, so it won't make any difference for the Zynq, but someone is likely to some day copy/paste this driver and use it for some externally connected FPGA instead. > + > + return 0; > +} > + > +static int __maybe_unused zynq_fpga_runtime_resume(struct device *dev) > +{ > + struct zynq_fpga_priv *priv; > + struct fpga_manager *mgr; > + > + mgr = dev_get_drvdata(dev); > + priv = mgr->priv; > + > + clk_enable(priv->clk); > + > + return 0; > +} > + > +static const struct dev_pm_ops zynq_fpga_pm_ops = { > + SET_RUNTIME_PM_OPS(zynq_fpga_runtime_suspend, > + zynq_fpga_runtime_resume, NULL) > +}; > + > #ifdef CONFIG_OF > static const struct of_device_id zynq_fpga_of_match[] = { > { .compatible = "xlnx,zynq-devcfg-1.0", }, > @@ -503,6 +544,7 @@ static struct platform_driver zynq_fpga_driver = { > .driver = { > .name = "zynq_fpga_manager", > .of_match_table = of_match_ptr(zynq_fpga_of_match), > + .pm = &zynq_fpga_pm_ops, > }, > }; > > Kind regards, Mike Looijmans System Expert TOPIC Embedded Products Eindhovenseweg 32-C, NL-5683 KH Best Postbus 440, NL-5680 AK Best Telefoon: +31 (0) 499 33 69 79 Telefax: +31 (0) 499 33 69 70 E-mail: mike.looijmans@topicproducts.com Website: www.topicproducts.com Please consider the environment before printing this e-mail Visit us at : Aerospace Electrical Systems Expo Europe which will be held from 17.11.2015 till 19.11.2015, Findorffstrasse 101 Bremen, Germany, Hall 5, stand number C65 http://www.aesexpo.eu
Hi Mike, thanks for your feedback. I put what I think you suggested inline below. On Thu, Nov 19, 2015 at 11:25 PM, Mike Looijmans <mike.looijmans@topic.nl> wrote: > On 19-11-15 23:07, Moritz Fischer wrote: >> @@ -457,19 +457,26 @@ static int zynq_fpga_probe(struct platform_device >> *pdev) >> return err; >> } >> >> + pm_runtime_get_noresume(&pdev->dev); >> + pm_runtime_set_active(&pdev->dev); >> + pm_runtime_enable(&pdev->dev); >> + >> /* unlock the device */ >> zynq_fpga_write(priv, UNLOCK_OFFSET, UNLOCK_MASK); >> >> - clk_disable(priv->clk); >> >> err = fpga_mgr_register(dev, "Xilinx Zynq FPGA Manager", >> &zynq_fpga_ops, priv); >> if (err) { >> dev_err(dev, "unable to register FPGA manager"); >> - clk_unprepare(priv->clk); >> + clk_disable_unprepare(priv->clk); - clk_disable_unprepare(priv->clk); >> + pm_runtime_put_noidle(&pdev->dev); >> + pm_runtime_disable(&pdev->dev); >> return err; >> } >> >> + pm_runtime_put(&pdev->dev); >> + >> return 0; >> } >> >> @@ -483,11 +490,45 @@ static int zynq_fpga_remove(struct platform_device >> *pdev) >> >> fpga_mgr_unregister(&pdev->dev); >> >> - clk_unprepare(priv->clk); >> + pm_runtime_get_sync(&pdev->dev); >> + clk_disable_unprepare(priv->clk); - clk_disable_unprepare(priv->clk); >> + pm_runtime_put_noidle(&pdev->dev); >> + pm_runtime_disable(&pdev->dev); >> >> return 0; >> } >> >> +static int __maybe_unused zynq_fpga_runtime_suspend(struct device *dev) >> +{ >> + struct zynq_fpga_priv *priv; >> + struct fpga_manager *mgr; >> + >> + mgr = dev_get_drvdata(dev); >> + priv = mgr->priv; >> + >> + clk_disable(priv->clk); - clk_disable(priv->clk) + clk_disable_unprepare(priv->clk) > > > From what I understand, this call is done in a sleepable context, so you can > use clk_disable_unprepare here (and its counterpart in resume). And remove > the prepare at probe time and unprepare at removal. > > Not all clocks can implement atomic enable/disable, for example I2C and SPI > controlled clocks only implement the prepare/unprepare routines. > > I guess the "clk" here will always be a SOC provided one, so it won't make > any difference for the Zynq, but someone is likely to some day copy/paste > this driver and use it for some externally connected FPGA instead. To clarify. Is the above / below what you suggested? >> +static int __maybe_unused zynq_fpga_runtime_resume(struct device *dev) >> +{ >> + struct zynq_fpga_priv *priv; >> + struct fpga_manager *mgr; >> + >> + mgr = dev_get_drvdata(dev); >> + priv = mgr->priv; >> + >> + clk_enable(priv->clk); - clk_enable(priv->clk) + clk_prepare_enable(priv->clk) >> + >> + return 0; >> +} >> + Cheers, Moritz
?On 23-11-15 23:02, Moritz Fischer wrote: > Hi Mike, > > thanks for your feedback. I put what I think you suggested inline below. > > On Thu, Nov 19, 2015 at 11:25 PM, Mike Looijmans > <mike.looijmans@topic.nl> wrote: >> On 19-11-15 23:07, Moritz Fischer wrote: > >>> @@ -457,19 +457,26 @@ static int zynq_fpga_probe(struct platform_device >>> *pdev) >>> return err; >>> } >>> >>> + pm_runtime_get_noresume(&pdev->dev); >>> + pm_runtime_set_active(&pdev->dev); >>> + pm_runtime_enable(&pdev->dev); >>> + >>> /* unlock the device */ >>> zynq_fpga_write(priv, UNLOCK_OFFSET, UNLOCK_MASK); >>> >>> - clk_disable(priv->clk); >>> >>> err = fpga_mgr_register(dev, "Xilinx Zynq FPGA Manager", >>> &zynq_fpga_ops, priv); >>> if (err) { >>> dev_err(dev, "unable to register FPGA manager"); >>> - clk_unprepare(priv->clk); >>> + clk_disable_unprepare(priv->clk); > - clk_disable_unprepare(priv->clk); >>> + pm_runtime_put_noidle(&pdev->dev); >>> + pm_runtime_disable(&pdev->dev); >>> return err; >>> } >>> >>> + pm_runtime_put(&pdev->dev); >>> + >>> return 0; >>> } >>> >>> @@ -483,11 +490,45 @@ static int zynq_fpga_remove(struct platform_device >>> *pdev) >>> >>> fpga_mgr_unregister(&pdev->dev); >>> >>> - clk_unprepare(priv->clk); >>> + pm_runtime_get_sync(&pdev->dev); >>> + clk_disable_unprepare(priv->clk); > - clk_disable_unprepare(priv->clk); > >>> + pm_runtime_put_noidle(&pdev->dev); >>> + pm_runtime_disable(&pdev->dev); >>> >>> return 0; >>> } >>> >>> +static int __maybe_unused zynq_fpga_runtime_suspend(struct device *dev) >>> +{ >>> + struct zynq_fpga_priv *priv; >>> + struct fpga_manager *mgr; >>> + >>> + mgr = dev_get_drvdata(dev); >>> + priv = mgr->priv; >>> + >>> + clk_disable(priv->clk); > > - clk_disable(priv->clk) > + clk_disable_unprepare(priv->clk) >> >> >> From what I understand, this call is done in a sleepable context, so you can >> use clk_disable_unprepare here (and its counterpart in resume). And remove >> the prepare at probe time and unprepare at removal. >> >> Not all clocks can implement atomic enable/disable, for example I2C and SPI >> controlled clocks only implement the prepare/unprepare routines. >> >> I guess the "clk" here will always be a SOC provided one, so it won't make >> any difference for the Zynq, but someone is likely to some day copy/paste >> this driver and use it for some externally connected FPGA instead. > > To clarify. Is the above / below what you suggested? Indeed, that's exactly what I meant. >>> +static int __maybe_unused zynq_fpga_runtime_resume(struct device *dev) >>> +{ >>> + struct zynq_fpga_priv *priv; >>> + struct fpga_manager *mgr; >>> + >>> + mgr = dev_get_drvdata(dev); >>> + priv = mgr->priv; >>> + >>> + clk_enable(priv->clk); > > - clk_enable(priv->clk) > + clk_prepare_enable(priv->clk) >>> + >>> + return 0; >>> +} >>> + > > Cheers, > > Moritz > Kind regards, Mike Looijmans System Expert TOPIC Embedded Products Eindhovenseweg 32-C, NL-5683 KH Best Postbus 440, NL-5680 AK Best Telefoon: +31 (0) 499 33 69 79 Telefax: +31 (0) 499 33 69 70 E-mail: mike.looijmans@topicproducts.com Website: www.topicproducts.com Please consider the environment before printing this e-mail
diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c index c2fb412..3f5469d 100644 --- a/drivers/fpga/zynq-fpga.c +++ b/drivers/fpga/zynq-fpga.c @@ -28,6 +28,7 @@ #include <linux/of_address.h> #include <linux/of_irq.h> #include <linux/pm.h> +#include <linux/pm_runtime.h> #include <linux/regmap.h> #include <linux/string.h> @@ -184,8 +185,8 @@ static int zynq_fpga_ops_write_init(struct fpga_manager *mgr, u32 flags, priv = mgr->priv; - err = clk_enable(priv->clk); - if (err) + err = pm_runtime_get_sync(priv->dev); + if (err < 0) return err; /* don't globally reset PL if we're doing partial reconfig */ @@ -271,12 +272,12 @@ static int zynq_fpga_ops_write_init(struct fpga_manager *mgr, u32 flags, ctrl = zynq_fpga_read(priv, MCTRL_OFFSET); zynq_fpga_write(priv, MCTRL_OFFSET, (~MCTRL_PCAP_LPBK_MASK & ctrl)); - clk_disable(priv->clk); + pm_runtime_put(priv->dev); return 0; out_err: - clk_disable(priv->clk); + pm_runtime_put(priv->dev); return err; } @@ -301,9 +302,8 @@ static int zynq_fpga_ops_write(struct fpga_manager *mgr, memcpy(kbuf, buf, count); - /* enable clock */ - err = clk_enable(priv->clk); - if (err) + err = pm_runtime_get_sync(priv->dev); + if (err < 0) goto out_free; zynq_fpga_write(priv, INT_STS_OFFSET, IXR_ALL_MASK); @@ -335,7 +335,7 @@ static int zynq_fpga_ops_write(struct fpga_manager *mgr, err = -EFAULT; } - clk_disable(priv->clk); + pm_runtime_put(priv->dev); out_free: dma_free_coherent(priv->dev, in_count, kbuf, dma_addr); @@ -349,8 +349,8 @@ static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr, u32 flags) int err; u32 intr_status; - err = clk_enable(priv->clk); - if (err) + err = pm_runtime_get_sync(priv->dev); + if (err < 0) return err; err = zynq_fpga_poll_timeout(priv, INT_STS_OFFSET, intr_status, @@ -358,7 +358,7 @@ static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr, u32 flags) INIT_POLL_DELAY, INIT_POLL_TIMEOUT); - clk_disable(priv->clk); + pm_runtime_put(priv->dev); if (err) return err; @@ -385,12 +385,12 @@ static enum fpga_mgr_states zynq_fpga_ops_state(struct fpga_manager *mgr) priv = mgr->priv; - err = clk_enable(priv->clk); - if (err) + err = pm_runtime_get_sync(priv->dev); + if (err < 0) return FPGA_MGR_STATE_UNKNOWN; intr_status = zynq_fpga_read(priv, INT_STS_OFFSET); - clk_disable(priv->clk); + pm_runtime_put(priv->dev); if (intr_status & IXR_PCFG_DONE_MASK) return FPGA_MGR_STATE_OPERATING; @@ -457,19 +457,26 @@ static int zynq_fpga_probe(struct platform_device *pdev) return err; } + pm_runtime_get_noresume(&pdev->dev); + pm_runtime_set_active(&pdev->dev); + pm_runtime_enable(&pdev->dev); + /* unlock the device */ zynq_fpga_write(priv, UNLOCK_OFFSET, UNLOCK_MASK); - clk_disable(priv->clk); err = fpga_mgr_register(dev, "Xilinx Zynq FPGA Manager", &zynq_fpga_ops, priv); if (err) { dev_err(dev, "unable to register FPGA manager"); - clk_unprepare(priv->clk); + clk_disable_unprepare(priv->clk); + pm_runtime_put_noidle(&pdev->dev); + pm_runtime_disable(&pdev->dev); return err; } + pm_runtime_put(&pdev->dev); + return 0; } @@ -483,11 +490,45 @@ static int zynq_fpga_remove(struct platform_device *pdev) fpga_mgr_unregister(&pdev->dev); - clk_unprepare(priv->clk); + pm_runtime_get_sync(&pdev->dev); + clk_disable_unprepare(priv->clk); + pm_runtime_put_noidle(&pdev->dev); + pm_runtime_disable(&pdev->dev); return 0; } +static int __maybe_unused zynq_fpga_runtime_suspend(struct device *dev) +{ + struct zynq_fpga_priv *priv; + struct fpga_manager *mgr; + + mgr = dev_get_drvdata(dev); + priv = mgr->priv; + + clk_disable(priv->clk); + + return 0; +} + +static int __maybe_unused zynq_fpga_runtime_resume(struct device *dev) +{ + struct zynq_fpga_priv *priv; + struct fpga_manager *mgr; + + mgr = dev_get_drvdata(dev); + priv = mgr->priv; + + clk_enable(priv->clk); + + return 0; +} + +static const struct dev_pm_ops zynq_fpga_pm_ops = { + SET_RUNTIME_PM_OPS(zynq_fpga_runtime_suspend, + zynq_fpga_runtime_resume, NULL) +}; + #ifdef CONFIG_OF static const struct of_device_id zynq_fpga_of_match[] = { { .compatible = "xlnx,zynq-devcfg-1.0", }, @@ -503,6 +544,7 @@ static struct platform_driver zynq_fpga_driver = { .driver = { .name = "zynq_fpga_manager", .of_match_table = of_match_ptr(zynq_fpga_of_match), + .pm = &zynq_fpga_pm_ops, }, };
Replaced constant clock_{enable,disable} calls with pm_runtime hooks for suspend and resume to avoid constant clk_enable / clk_disable. Acked-by: Alan Tull <atull@opensource.altera.com> Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> --- Changes: v1: - Removed superfluous #ifdef CONFIG_PM as suggested by Michal - Changed commit message to include suspend / resume - Added Alan's Acked-by drivers/fpga/zynq-fpga.c | 76 +++++++++++++++++++++++++++++++++++++----------- 1 file changed, 59 insertions(+), 17 deletions(-)