| Message ID | 1304028785-10583-11-git-send-email-jbarnes@virtuousgeek.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Thu, 28 Apr 2011 15:12:56 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote: > - if (IS_GEN6(dev)) { > + if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) { IS_GEN6 for SNB and IS_IVYBRIDGE for IVB? More consistency, please.
On Thu, 28 Apr 2011 15:46:06 -0700 Keith Packard <keithp@keithp.com> wrote: > On Thu, 28 Apr 2011 15:12:56 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote: > > > - if (IS_GEN6(dev)) { > > + if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) { > > IS_GEN6 for SNB and IS_IVYBRIDGE for IVB? More consistency, please. > See earlier mail; GEN6 is the wrong one to use here imo.
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 3396043..fbb7a6b 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -7229,7 +7229,7 @@ void intel_enable_clock_gating(struct drm_device *dev) _3D_CHICKEN2_WM_READ_PIPELINED); } - if (IS_GEN6(dev)) { + if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) { I915_WRITE(WM3_LP_ILK, 0); I915_WRITE(WM2_LP_ILK, 0); I915_WRITE(WM1_LP_ILK, 0); @@ -7491,6 +7491,13 @@ static void intel_init_display(struct drm_device *dev) dev_priv->display.fdi_link_train = ivb_fdi_link_train; else dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; + if (SNB_READ_WM0_LATENCY()) { + dev_priv->display.update_wm = sandybridge_update_wm; + } else { + DRM_DEBUG_KMS("Failed to read display plane latency. " + "Disable CxSR\n"); + dev_priv->display.update_wm = NULL; + } } else dev_priv->display.update_wm = NULL; } else if (IS_PINEVIEW(dev)) {
Not fully tested. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> --- drivers/gpu/drm/i915/intel_display.c | 9 ++++++++- 1 files changed, 8 insertions(+), 1 deletions(-)