| Message ID | 1449228824-27152-1-git-send-email-michal.winiarski@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Dec 04, 2015 at 12:33:44PM +0100, Micha? Winiarski wrote: > According to bspec, some parts of HW expect the addresses to be in > a canonical form, where bits [63:48] == [47]. Let's convert addresses to > canonical form prior to relocating and return converted offsets to > userspace. > > Cc: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Michel Thierry <michel.thierry@intel.com> > Signed-off-by: Micha? Winiarski <michal.winiarski@intel.com> > --- > drivers/gpu/drm/i915/i915_gem_execbuffer.c | 9 ++++++--- > drivers/gpu/drm/i915/i915_gem_gtt.h | 5 +++++ > 2 files changed, 11 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c > index a4c243c..9f27be9 100644 > --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c > +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c > @@ -395,7 +395,7 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, > target_i915_obj = target_vma->obj; > target_obj = &target_vma->obj->base; > > - target_offset = target_vma->node.start; > + target_offset = gen8_canonical_addr(target_vma->node.start); > > /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and > * pipe_control writes because the gpu doesn't properly redirect them > @@ -583,6 +583,7 @@ i915_gem_execbuffer_reserve_vma(struct i915_vma *vma, > struct drm_i915_gem_object *obj = vma->obj; > struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; > uint64_t flags; > + uint64_t offset; > int ret; > > flags = PIN_USER; > @@ -623,8 +624,10 @@ i915_gem_execbuffer_reserve_vma(struct i915_vma *vma, > entry->flags |= __EXEC_OBJECT_HAS_FENCE; > } > > - if (entry->offset != vma->node.start) { > - entry->offset = vma->node.start; > + offset = gen8_canonical_addr(vma->node.start); > + > + if (entry->offset != offset) { > + entry->offset = offset; > *need_reloc = true; > } > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h > index 877c32c..65e8f88 100644 > --- a/drivers/gpu/drm/i915/i915_gem_gtt.h > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h > @@ -507,6 +507,11 @@ static inline size_t gen8_pte_count(uint64_t address, uint64_t length) > return i915_pte_count(address, length, GEN8_PDE_SHIFT); > } > > +static inline uint64_t gen8_canonical_addr(uint64_t address) > +{ > + return ((int64_t)address << 16) >> 16; > +} This could really use a comment explaining what it's doing and why. Just lifting the first sentence of your commit message into a comment would seem to be enough. > + > static inline dma_addr_t > i915_page_dir_dma_addr(const struct i915_hw_ppgtt *ppgtt, const unsigned n) > { > -- > 2.5.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Fri, Dec 04, 2015 at 12:33:44PM +0100, Micha? Winiarski wrote: > According to bspec, some parts of HW expect the addresses to be in > a canonical form, where bits [63:48] == [47]. Let's convert addresses to > canonical form prior to relocating and return converted offsets to > userspace. > > Cc: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Michel Thierry <michel.thierry@intel.com> > Signed-off-by: Micha? Winiarski <michal.winiarski@intel.com> > --- > drivers/gpu/drm/i915/i915_gem_execbuffer.c | 9 ++++++--- > drivers/gpu/drm/i915/i915_gem_gtt.h | 5 +++++ > 2 files changed, 11 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c > index a4c243c..9f27be9 100644 > --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c > +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c > @@ -395,7 +395,7 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, > target_i915_obj = target_vma->obj; > target_obj = &target_vma->obj->base; > > - target_offset = target_vma->node.start; > + target_offset = gen8_canonical_addr(target_vma->node.start); Ok, this keeps userspace in sync as well as writing the cannonical addreses to hardware. > /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and > * pipe_control writes because the gpu doesn't properly redirect them > @@ -583,6 +583,7 @@ i915_gem_execbuffer_reserve_vma(struct i915_vma *vma, > struct drm_i915_gem_object *obj = vma->obj; > struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; > uint64_t flags; > + uint64_t offset; > int ret; > > flags = PIN_USER; > @@ -623,8 +624,10 @@ i915_gem_execbuffer_reserve_vma(struct i915_vma *vma, > entry->flags |= __EXEC_OBJECT_HAS_FENCE; > } > > - if (entry->offset != vma->node.start) { > - entry->offset = vma->node.start; > + offset = gen8_canonical_addr(vma->node.start); > + Kill the extra line. > + if (entry->offset != offset) { > + entry->offset = offset; > *need_reloc = true; And this copies back the cannonical address to userspace. Ok, the userspace side looks correct (the presumed_offset and execobject.offsets will be updated to store the cannonical address). > } > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h > index 877c32c..65e8f88 100644 > --- a/drivers/gpu/drm/i915/i915_gem_gtt.h > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h > @@ -507,6 +507,11 @@ static inline size_t gen8_pte_count(uint64_t address, uint64_t length) > return i915_pte_count(address, length, GEN8_PDE_SHIFT); > } > > +static inline uint64_t gen8_canonical_addr(uint64_t address) > +{ You need the bspec reference here as well. Looks good to me, with just a quick explanation here as to what we are doing and why. -Chris
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index a4c243c..9f27be9 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -395,7 +395,7 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, target_i915_obj = target_vma->obj; target_obj = &target_vma->obj->base; - target_offset = target_vma->node.start; + target_offset = gen8_canonical_addr(target_vma->node.start); /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and * pipe_control writes because the gpu doesn't properly redirect them @@ -583,6 +583,7 @@ i915_gem_execbuffer_reserve_vma(struct i915_vma *vma, struct drm_i915_gem_object *obj = vma->obj; struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; uint64_t flags; + uint64_t offset; int ret; flags = PIN_USER; @@ -623,8 +624,10 @@ i915_gem_execbuffer_reserve_vma(struct i915_vma *vma, entry->flags |= __EXEC_OBJECT_HAS_FENCE; } - if (entry->offset != vma->node.start) { - entry->offset = vma->node.start; + offset = gen8_canonical_addr(vma->node.start); + + if (entry->offset != offset) { + entry->offset = offset; *need_reloc = true; } diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h index 877c32c..65e8f88 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.h +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h @@ -507,6 +507,11 @@ static inline size_t gen8_pte_count(uint64_t address, uint64_t length) return i915_pte_count(address, length, GEN8_PDE_SHIFT); } +static inline uint64_t gen8_canonical_addr(uint64_t address) +{ + return ((int64_t)address << 16) >> 16; +} + static inline dma_addr_t i915_page_dir_dma_addr(const struct i915_hw_ppgtt *ppgtt, const unsigned n) {
According to bspec, some parts of HW expect the addresses to be in a canonical form, where bits [63:48] == [47]. Let's convert addresses to canonical form prior to relocating and return converted offsets to userspace. Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Michel Thierry <michel.thierry@intel.com> Signed-off-by: Micha? Winiarski <michal.winiarski@intel.com> --- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 9 ++++++--- drivers/gpu/drm/i915/i915_gem_gtt.h | 5 +++++ 2 files changed, 11 insertions(+), 3 deletions(-)