| Message ID | 1304028785-10583-14-git-send-email-jbarnes@virtuousgeek.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Thu, 28 Apr 2011 15:12:59 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> Treat it like Sandy Bridge in a few places.
gen >= 6?
On Thu, 28 Apr 2011 15:12:59 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote: > Treat it like Sandy Bridge in a few places. > > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> > --- > drivers/gpu/drm/i915/intel_dp.c | 6 +++--- > 1 files changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index 0daefca..1d0eccd 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -312,7 +312,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, > else > aux_clock_divider = intel_hrawclk(dev) / 2; > > - if (IS_GEN6(dev)) > + if (IS_GEN6(dev) || IS_GEN7(dev)) Shouldn't these be IS_SANDYBRIDGE(dev) || IS_IVYBRIDGE(dev) following the convention that info->gen is reserved for the render engine. Perhaps if you do the s/IS_GEN6/IS_SNADYBRIDGE/ fixes first it will become much clearer? :) -Chris
On Sun, 01 May 2011 17:26:11 +0100, Chris Wilson <chris@chris-wilson.co.uk> wrote: > Perhaps if you do the s/IS_GEN6/IS_SNADYBRIDGE/ fixes first it will become > much clearer? :) The only question is one of regressions; getting the cleanups tested in isolation from the IVB patches. That seems do-able for the 2.6.40 merge window.
On Sun, 01 May 2011 17:26:11 +0100 Chris Wilson <chris@chris-wilson.co.uk> wrote: > On Thu, 28 Apr 2011 15:12:59 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote: > > Treat it like Sandy Bridge in a few places. > > > > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> > > --- > > drivers/gpu/drm/i915/intel_dp.c | 6 +++--- > > 1 files changed, 3 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > > index 0daefca..1d0eccd 100644 > > --- a/drivers/gpu/drm/i915/intel_dp.c > > +++ b/drivers/gpu/drm/i915/intel_dp.c > > @@ -312,7 +312,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, > > else > > aux_clock_divider = intel_hrawclk(dev) / 2; > > > > - if (IS_GEN6(dev)) > > + if (IS_GEN6(dev) || IS_GEN7(dev)) > > Shouldn't these be IS_SANDYBRIDGE(dev) || IS_IVYBRIDGE(dev) following the > convention that info->gen is reserved for the render engine. > > Perhaps if you do the s/IS_GEN6/IS_SNADYBRIDGE/ fixes first it will become > much clearer? :) Yeah, sorry I violated my own rule, will fix (this one can be delayed until I can test it anyway).
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 0daefca..1d0eccd 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -312,7 +312,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, else aux_clock_divider = intel_hrawclk(dev) / 2; - if (IS_GEN6(dev)) + if (IS_GEN6(dev) || IS_GEN7(dev)) precharge = 3; else precharge = 5; @@ -1302,7 +1302,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp) for (;;) { /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ uint32_t signal_levels; - if (IS_GEN6(dev) && is_edp(intel_dp)) { + if ((IS_GEN6(dev) || IS_GEN7(dev)) && is_edp(intel_dp)) { signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; } else { @@ -1376,7 +1376,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp) break; } - if (IS_GEN6(dev) && is_edp(intel_dp)) { + if ((IS_GEN6(dev) || IS_GEN7(dev)) && is_edp(intel_dp)) { signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; } else {
Treat it like Sandy Bridge in a few places. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> --- drivers/gpu/drm/i915/intel_dp.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-)