| Message ID | 1449236333-4410-2-git-send-email-dirk.behme@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Dec 04, 2015 at 02:38:52PM +0100, Dirk Behme wrote: > From: Gaku Inami <gaku.inami.xw@bp.renesas.com> > > Add Cortex-A57 CPU cores to r8a7795 SoC for a total of 4 x Cortex-A57. > > Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com> > Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> > Sigend-off-by: Dirk Behme <dirk.behme@gmail.com> Thanks, I have queued this up for v4.5.
On Sat, Dec 12, 2015 at 08:07:51AM +0900, Simon Horman wrote: > On Fri, Dec 04, 2015 at 02:38:52PM +0100, Dirk Behme wrote: > > From: Gaku Inami <gaku.inami.xw@bp.renesas.com> > > > > Add Cortex-A57 CPU cores to r8a7795 SoC for a total of 4 x Cortex-A57. > > > > Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com> > > Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> > > Sigend-off-by: Dirk Behme <dirk.behme@gmail.com> > > Thanks, I have queued this up for v4.5. I meant to test this earlier but somehow it slopped my mind. With this patch applied I still only see one CPU brought up whereas I was expecting 4. Are more patches needed in order to get more CPUs operating? I am using renesas-devel-20151214-v4.4-rc5 + the cpg-mmsr driver (v6). I built the kernel using the defconfig.
On 15.12.2015 06:12, Simon Horman wrote: > On Sat, Dec 12, 2015 at 08:07:51AM +0900, Simon Horman wrote: >> On Fri, Dec 04, 2015 at 02:38:52PM +0100, Dirk Behme wrote: >>> From: Gaku Inami <gaku.inami.xw@bp.renesas.com> >>> >>> Add Cortex-A57 CPU cores to r8a7795 SoC for a total of 4 x Cortex-A57. >>> >>> Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com> >>> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> >>> Sigend-off-by: Dirk Behme <dirk.behme@gmail.com> >> >> Thanks, I have queued this up for v4.5. > > I meant to test this earlier but somehow it slopped my mind. > > With this patch applied I still only see one CPU brought up > whereas I was expecting 4. Are more patches needed in order to > get more CPUs operating? Hmm, I don't think so (?). I tested this with https://github.com/dirkbehme/linux-renesas-rcar-gen3/commits/dirk/gen3-latest-update and got (including the A53 patch) ... ASID allocator initialised with 65536 entries Detected PIPT I-cache on CPU1 CPU1: Booted secondary processor [411fd073] Detected PIPT I-cache on CPU2 CPU2: Booted secondary processor [411fd073] Detected PIPT I-cache on CPU3 CPU3: Booted secondary processor [411fd073] Detected VIPT I-cache on CPU4 CPU features: enabling workaround for ARM erratum 845719 CPU4: Booted secondary processor [410fd034] Detected VIPT I-cache on CPU5 CPU5: Booted secondary processor [410fd034] Detected VIPT I-cache on CPU6 CPU6: Booted secondary processor [410fd034] Detected VIPT I-cache on CPU7 CPU7: Booted secondary processor [410fd034] Brought up 8 CPUs SMP: Total of 8 processors activated. CPU: All CPU(s) started at EL1 ... This is based on last weeks renesas-drivers-2015-12-08-v4.4-rc4 and besides the patches for SDHI/eMMC I don't think it contains anything additional regarding the number of CPU cores. Best regards Dirk
Hi Simon, On Tue, Dec 15, 2015 at 6:12 AM, Simon Horman <horms@verge.net.au> wrote: > On Sat, Dec 12, 2015 at 08:07:51AM +0900, Simon Horman wrote: >> On Fri, Dec 04, 2015 at 02:38:52PM +0100, Dirk Behme wrote: >> > From: Gaku Inami <gaku.inami.xw@bp.renesas.com> >> > >> > Add Cortex-A57 CPU cores to r8a7795 SoC for a total of 4 x Cortex-A57. >> > >> > Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com> >> > Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> >> > Sigend-off-by: Dirk Behme <dirk.behme@gmail.com> >> >> Thanks, I have queued this up for v4.5. > > I meant to test this earlier but somehow it slopped my mind. > > With this patch applied I still only see one CPU brought up > whereas I was expecting 4. Are more patches needed in order to > get more CPUs operating? > > I am using renesas-devel-20151214-v4.4-rc5 + the cpg-mmsr driver (v6). > I built the kernel using the defconfig. I can confirm I saw 4 CPUs online as soon as I had merged renesas-devel containing the above change into my tree (which was based on renesas-drivers-2015-12-08-v4.4-rc4 at that time). I was surprised to see it was that simple to enable the 3 other cores ;-) Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Simon, On Sat, Dec 12, 2015 at 8:07 AM, Simon Horman <horms@verge.net.au> wrote: > On Fri, Dec 04, 2015 at 02:38:52PM +0100, Dirk Behme wrote: >> From: Gaku Inami <gaku.inami.xw@bp.renesas.com> >> >> Add Cortex-A57 CPU cores to r8a7795 SoC for a total of 4 x Cortex-A57. >> >> Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com> >> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> >> Sigend-off-by: Dirk Behme <dirk.behme@gmail.com> > > Thanks, I have queued this up for v4.5. Thanks. May I ask if CPU hotplug is known to work? Also, which version of the boot loader stack is required? Best, / magnus
On 15.12.2015 09:38, Magnus Damm wrote: > Hi Simon, > > On Sat, Dec 12, 2015 at 8:07 AM, Simon Horman <horms@verge.net.au> wrote: >> On Fri, Dec 04, 2015 at 02:38:52PM +0100, Dirk Behme wrote: >>> From: Gaku Inami <gaku.inami.xw@bp.renesas.com> >>> >>> Add Cortex-A57 CPU cores to r8a7795 SoC for a total of 4 x Cortex-A57. >>> >>> Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com> >>> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> >>> Sigend-off-by: Dirk Behme <dirk.behme@gmail.com> >> >> Thanks, I have queued this up for v4.5. > > Thanks. May I ask if CPU hotplug is known to work? I didn't test that. > Also, which version > of the boot loader stack is required? I've the U-Boot / boot loader stack from BSP v3.0.2 on the board. I haven't tested v3.0.3, yet. Best regards Dirk
Hi Dirk, On Tue, Dec 15, 2015 at 5:48 PM, Dirk Behme <dirk.behme@gmail.com> wrote: > On 15.12.2015 09:38, Magnus Damm wrote: >> >> Hi Simon, >> >> On Sat, Dec 12, 2015 at 8:07 AM, Simon Horman <horms@verge.net.au> wrote: >>> >>> On Fri, Dec 04, 2015 at 02:38:52PM +0100, Dirk Behme wrote: >>>> >>>> From: Gaku Inami <gaku.inami.xw@bp.renesas.com> >>>> >>>> Add Cortex-A57 CPU cores to r8a7795 SoC for a total of 4 x Cortex-A57. >>>> >>>> Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com> >>>> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> >>>> Sigend-off-by: Dirk Behme <dirk.behme@gmail.com> >>> >>> >>> Thanks, I have queued this up for v4.5. >> >> >> Thanks. May I ask if CPU hotplug is known to work? > > > > I didn't test that. Ok, no worries. I feel that there are various CPU related features that need a bit of testing to make sure support is stable enough to enable without causing issues for other on-going development. CPU Hotplug is one of those, another is kernel command line options like maxcpus, and kexec would be good to have working as well. To make things a bit more complicated, there is a rather complicated software stack with trusted code installed by the boot loader, so there is a dependency on that as well. On earlier SoCs from previous generations there were issues with shared reset vectors and a watchdog, so SMP support may affect watchdog too... >> Also, which version >> of the boot loader stack is required? > > I've the U-Boot / boot loader stack from BSP v3.0.2 on the board. I haven't > tested v3.0.3, yet. Thanks for sharing! Cheers, / magnus
Hi Dirk, On Tue, Dec 15, 2015 at 09:48:46AM +0100, Dirk Behme wrote: > On 15.12.2015 09:38, Magnus Damm wrote: > >Hi Simon, > > > >On Sat, Dec 12, 2015 at 8:07 AM, Simon Horman <horms@verge.net.au> wrote: > >>On Fri, Dec 04, 2015 at 02:38:52PM +0100, Dirk Behme wrote: > >>>From: Gaku Inami <gaku.inami.xw@bp.renesas.com> > >>> > >>>Add Cortex-A57 CPU cores to r8a7795 SoC for a total of 4 x Cortex-A57. > >>> > >>>Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com> > >>>Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> > >>>Sigend-off-by: Dirk Behme <dirk.behme@gmail.com> > >> > >>Thanks, I have queued this up for v4.5. > > > >Thanks. May I ask if CPU hotplug is known to work? > > > I didn't test that. As a follow-up I am wondering if you subsequently observed CPU hotplug working. My recent testing on v4.5 indicates that it isn't working in my environment. It would be quite valuable to know if it has ever been known to work. > >Also, which version > >of the boot loader stack is required? > > > I've the U-Boot / boot loader stack from BSP v3.0.2 on the board. I haven't > tested v3.0.3, yet. For reference my environment is as follows: NOTICE: BL2: R-Car H3 Loader Rev.1.0.1 NOTICE: BL2: DDR1600(rev.0.10) NOTICE: BL2: DRAM Split is 4ch NOTICE: BL2: QoS is Gfx Oriented(rev.0.24A) NOTICE: BL2: v1.1(release):41099f4 NOTICE: BL2: Built : 11:47:26, Nov 19 2015 NOTICE: BL2: Normal boot NOTICE: BL2: memdrv_block_read dst=0xe630e0b0 src=0x8180000 len=36(0x24) NOTICE: BL2: memdrv_block_read dst=0x43f00000 src=0x8180400 len=3072(0xc00) NOTICE: BL2: memdrv_block_read dst=0x44000000 src=0x81c0000 len=65536(0x10000) NOTICE: BL2: memdrv_block_read dst=0x44100000 src=0x8200000 len=524288(0x80000) NOTICE: BL2: memdrv_block_read dst=0x49000000 src=0x8640000 len=1048576(0x100000) U-Boot 2015.04 (Nov 19 2015 - 11:47:49) CPU: Renesas Electronics CPU rev 1.0 Board: Salvator-X DRAM: 896 MiB MMC: sh-sdhi: 0, sh-sdhi: 1, sh-sdhi: 2 In: serial Out: serial Err: serial Net: ravb
Hi Simon, Dirk, Magnus, On 3/16/2016 8:19 AM, Simon Horman wrote: > Hi Dirk, > > On Tue, Dec 15, 2015 at 09:48:46AM +0100, Dirk Behme wrote: >> On 15.12.2015 09:38, Magnus Damm wrote: >>> Hi Simon, >>> >>> On Sat, Dec 12, 2015 at 8:07 AM, Simon Horman <horms@verge.net.au> wrote: >>>> On Fri, Dec 04, 2015 at 02:38:52PM +0100, Dirk Behme wrote: >>>>> From: Gaku Inami <gaku.inami.xw@bp.renesas.com> >>>>> >>>>> Add Cortex-A57 CPU cores to r8a7795 SoC for a total of 4 x Cortex-A57. >>>>> >>>>> Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com> >>>>> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> >>>>> Sigend-off-by: Dirk Behme <dirk.behme@gmail.com> >>>> >>>> Thanks, I have queued this up for v4.5. >>> >>> Thanks. May I ask if CPU hotplug is known to work? >> >> >> I didn't test that. > > As a follow-up I am wondering if you subsequently observed CPU hotplug > working. My recent testing on v4.5 indicates that it isn't working in my > environment. It would be quite valuable to know if it has ever been known > to work. > >>> Also, which version >>> of the boot loader stack is required? Yes. CPUHotplug will be supported in boot loader stack released by Dec 2015 and later. >> >> I've the U-Boot / boot loader stack from BSP v3.0.2 on the board. I haven't >> tested v3.0.3, yet. > > For reference my environment is as follows: > > > NOTICE: BL2: R-Car H3 Loader Rev.1.0.1 > NOTICE: BL2: DDR1600(rev.0.10) > NOTICE: BL2: DRAM Split is 4ch > NOTICE: BL2: QoS is Gfx Oriented(rev.0.24A) > NOTICE: BL2: v1.1(release):41099f4 > NOTICE: BL2: Built : 11:47:26, Nov 19 2015 > NOTICE: BL2: Normal boot > NOTICE: BL2: memdrv_block_read dst=0xe630e0b0 src=0x8180000 len=36(0x24) > NOTICE: BL2: memdrv_block_read dst=0x43f00000 src=0x8180400 len=3072(0xc00) > NOTICE: BL2: memdrv_block_read dst=0x44000000 src=0x81c0000 len=65536(0x10000) > NOTICE: BL2: memdrv_block_read dst=0x44100000 src=0x8200000 len=524288(0x80000) > NOTICE: BL2: memdrv_block_read dst=0x49000000 src=0x8640000 len=1048576(0x100000) > > U-Boot 2015.04 (Nov 19 2015 - 11:47:49) > > CPU: Renesas Electronics CPU rev 1.0 > Board: Salvator-X > DRAM: 896 MiB > MMC: sh-sdhi: 0, sh-sdhi: 1, sh-sdhi: 2 > In: serial > Out: serial > Err: serial > Net: ravb > -- > To unsubscribe from this list: send the line "unsubscribe linux-sh" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html >
On Wed, Mar 16, 2016 at 10:45:10AM +0700, Khiem Nguyen wrote: > Hi Simon, Dirk, Magnus, > > On 3/16/2016 8:19 AM, Simon Horman wrote: > >Hi Dirk, > > > >On Tue, Dec 15, 2015 at 09:48:46AM +0100, Dirk Behme wrote: > >>On 15.12.2015 09:38, Magnus Damm wrote: > >>>Hi Simon, > >>> > >>>On Sat, Dec 12, 2015 at 8:07 AM, Simon Horman <horms@verge.net.au> wrote: > >>>>On Fri, Dec 04, 2015 at 02:38:52PM +0100, Dirk Behme wrote: > >>>>>From: Gaku Inami <gaku.inami.xw@bp.renesas.com> > >>>>> > >>>>>Add Cortex-A57 CPU cores to r8a7795 SoC for a total of 4 x Cortex-A57. > >>>>> > >>>>>Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com> > >>>>>Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> > >>>>>Sigend-off-by: Dirk Behme <dirk.behme@gmail.com> > >>>> > >>>>Thanks, I have queued this up for v4.5. > >>> > >>>Thanks. May I ask if CPU hotplug is known to work? > >> > >> > >>I didn't test that. > > > >As a follow-up I am wondering if you subsequently observed CPU hotplug > >working. My recent testing on v4.5 indicates that it isn't working in my > >environment. It would be quite valuable to know if it has ever been known > >to work. > > > >>>Also, which version > >>>of the boot loader stack is required? > > Yes. CPUHotplug will be supported in boot loader stack released by Dec 2015 > and later. Thanks, that sounds positive. As Dec 2015 has already passed I wonder if a boot loader stack that supports CPU Hotplug is currently available. Perhaps internally? If so I think it would be good to verify v4.5. > >>I've the U-Boot / boot loader stack from BSP v3.0.2 on the board. I haven't > >>tested v3.0.3, yet. > > > >For reference my environment is as follows: > > > > > > NOTICE: BL2: R-Car H3 Loader Rev.1.0.1 > > NOTICE: BL2: DDR1600(rev.0.10) > > NOTICE: BL2: DRAM Split is 4ch > > NOTICE: BL2: QoS is Gfx Oriented(rev.0.24A) > > NOTICE: BL2: v1.1(release):41099f4 > > NOTICE: BL2: Built : 11:47:26, Nov 19 2015 > > NOTICE: BL2: Normal boot > > NOTICE: BL2: memdrv_block_read dst=0xe630e0b0 src=0x8180000 len=36(0x24) > > NOTICE: BL2: memdrv_block_read dst=0x43f00000 src=0x8180400 len=3072(0xc00) > > NOTICE: BL2: memdrv_block_read dst=0x44000000 src=0x81c0000 len=65536(0x10000) > > NOTICE: BL2: memdrv_block_read dst=0x44100000 src=0x8200000 len=524288(0x80000) > > NOTICE: BL2: memdrv_block_read dst=0x49000000 src=0x8640000 len=1048576(0x100000) > > > > U-Boot 2015.04 (Nov 19 2015 - 11:47:49) > > > > CPU: Renesas Electronics CPU rev 1.0 > > Board: Salvator-X > > DRAM: 896 MiB > > MMC: sh-sdhi: 0, sh-sdhi: 1, sh-sdhi: 2 > > In: serial > > Out: serial > > Err: serial > > Net: ravb > >-- > >To unsubscribe from this list: send the line "unsubscribe linux-sh" in > >the body of a message to majordomo@vger.kernel.org > >More majordomo info at http://vger.kernel.org/majordomo-info.html > > > > > -- > Best regards, > KHIEM Nguyen >
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 5611597..946a5bb 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -35,13 +35,31 @@ #address-cells = <1>; #size-cells = <0>; - /* 1 core only at this point */ a57_0: cpu@0 { compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x0>; device_type = "cpu"; enable-method = "psci"; }; + + a57_1: cpu@1 { + compatible = "arm,cortex-a57","arm,armv8"; + reg = <0x1>; + device_type = "cpu"; + enable-method = "psci"; + }; + a57_2: cpu@2 { + compatible = "arm,cortex-a57","arm,armv8"; + reg = <0x2>; + device_type = "cpu"; + enable-method = "psci"; + }; + a57_3: cpu@3 { + compatible = "arm,cortex-a57","arm,armv8"; + reg = <0x3>; + device_type = "cpu"; + enable-method = "psci"; + }; }; extal_clk: extal { @@ -101,6 +119,7 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -113,7 +132,7 @@ reg = <0x0 0xf1010000 0 0x1000>, <0x0 0xf1020000 0 0x2000>; interrupts = <GIC_PPI 9 - (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; gpio0: gpio@e6050000 { @@ -231,13 +250,13 @@ timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 - (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 14 - (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 11 - (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 10 - (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; cpg: clock-controller@e6150000 {