| Message ID | 1450353397-47668-2-git-send-email-majun258@huawei.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Thu, Dec 17, 2015 at 07:56:34PM +0800, MaJun wrote: > From: Ma Jun <majun258@huawei.com> > > Add the mbigen msi interrupt controller bindings document. > > This patch based on Mark Rutland's patch > https://lkml.org/lkml/2015/7/23/558 > > Signed-off-by: Ma Jun <majun258@huawei.com> > --- > Documentation/devicetree/bindings/arm/mbigen.txt | 74 ++++++++++++++++++++++ > 1 files changed, 74 insertions(+), 0 deletions(-) > create mode 100644 Documentation/devicetree/bindings/arm/mbigen.txt > > diff --git a/Documentation/devicetree/bindings/arm/mbigen.txt b/Documentation/devicetree/bindings/arm/mbigen.txt > new file mode 100644 > index 0000000..3eaa678 > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/mbigen.txt > @@ -0,0 +1,74 @@ > +Hisilicon mbigen device tree bindings. > +======================================= > + > +Mbigen means: message based interrupt generator. > + > +MBI is kind of msi interrupt only used on Non-PCI devices. > + > +To reduce the wired interrupt number connected to GIC, > +Hisilicon designed mbigen to collect and generate interrupt. > + > + > +Non-pci devices can connect to mbigen and generate the > +interrupt by writing ITS register. > + > +The mbigen chip and devices connect to mbigen have the following properties: > + > +Mbigen main node required properties: > +------------------------------------------- > +- compatible: Should be "hisilicon,mbigen-v2" > + > +- reg: Specifies the base physical address and size of the Mbigen > + registers. > + > +- interrupt controller: Identifies the node as an interrupt controller > + > +- msi-parent: Specifies the MSI controller this mbigen use. > + For more detail information,please refer to the generic msi-parent binding in > + Documentation/devicetree/bindings/interrupt-controller/msi.txt. > + > +- num-msis:Specifies the total number of interrupt this device has. Is this the number of pins implemented? Or the number of pins that are in use? The latter feels like something we can derive. > +- #interrupt-cells : Specifies the number of cells needed to encode an > + interrupt source. The value must be 2. > + > + The 1st cell is hardware pin number of the interrupt.This number is local to > + each mbigen chip and in the range from 0 to the maximum interrupts number > + of the mbigen. Just to check: 0 - 63 represent the "reserved" pins, yes? Other than those questions, this looks good to me. Thanks, Mark. > + > + The 2nd cell is the interrupt trigger type. > + The value of this cell should be: > + 1: rising edge triggered > + or > + 4: high level triggered > + > +Examples: > + > + mbigen_device_gmac:intc { > + compatible = "hisilicon,mbigen-v2"; > + reg = <0x0 0xc0080000 0x0 0x10000>; > + interrupt-controller; > + msi-parent = <&its_dsa 0x40b1c>; > + num-msis = <9>; > + #interrupt-cells = <2>; > + }; > + > +Devices connect to mbigen required properties: > +---------------------------------------------------- > +-interrupt-parent: Specifies the mbigen device node which device connected. > + > +-interrupts:Specifies the interrupt source. > + For the specific information of each cell in this property,please refer to > + the "interrupt-cells" description mentioned above. > + > +Examples: > + gmac0: ethernet@c2080000 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0 0xc2080000 0 0x20000>, > + <0 0xc0000000 0 0x1000>; > + interrupt-parent = <&mbigen_device_gmac>; > + interrupts = <656 1>, > + <657 1>; > + }; > + > -- > 1.7.1 > >
Hi Mark: ? 2015/12/17 21:52, Mark Rutland ??: > On Thu, Dec 17, 2015 at 07:56:34PM +0800, MaJun wrote: >> From: Ma Jun <majun258@huawei.com> [...] >> +- compatible: Should be "hisilicon,mbigen-v2" >> + >> +- reg: Specifies the base physical address and size of the Mbigen >> + registers. >> + >> +- interrupt controller: Identifies the node as an interrupt controller >> + >> +- msi-parent: Specifies the MSI controller this mbigen use. >> + For more detail information,please refer to the generic msi-parent binding in >> + Documentation/devicetree/bindings/interrupt-controller/msi.txt. >> + >> +- num-msis:Specifies the total number of interrupt this device has. > > Is this the number of pins implemented? Or the number of pins that are > in use? > > The latter feels like something we can derive. num-msis means the total number of pins implemented. > >> +- #interrupt-cells : Specifies the number of cells needed to encode an >> + interrupt source. The value must be 2. >> + >> + The 1st cell is hardware pin number of the interrupt.This number is local to >> + each mbigen chip and in the range from 0 to the maximum interrupts number >> + of the mbigen. > > Just to check: 0 - 63 represent the "reserved" pins, yes? Yes, you are right. > > Other than those questions, this looks good to me. Do i need to post a new patch to update these two questions? Thanks! MaJun > > Thanks, > Mark. > >> + >> + The 2nd cell is the interrupt trigger type. >> + The value of this cell should be: >> + 1: rising edge triggered >> + or >> + 4: high level triggered >> + >> +Examples: >> + >> + mbigen_device_gmac:intc { >> + compatible = "hisilicon,mbigen-v2"; >> + reg = <0x0 0xc0080000 0x0 0x10000>; >> + interrupt-controller; >> + msi-parent = <&its_dsa 0x40b1c>; >> + num-msis = <9>; >> + #interrupt-cells = <2>; >> + }; >> + >> +Devices connect to mbigen required properties: >> +---------------------------------------------------- >> +-interrupt-parent: Specifies the mbigen device node which device connected. >> + >> +-interrupts:Specifies the interrupt source. >> + For the specific information of each cell in this property,please refer to >> + the "interrupt-cells" description mentioned above. >> + >> +Examples: >> + gmac0: ethernet@c2080000 { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + reg = <0 0xc2080000 0 0x20000>, >> + <0 0xc0000000 0 0x1000>; >> + interrupt-parent = <&mbigen_device_gmac>; >> + interrupts = <656 1>, >> + <657 1>; >> + }; >> + >> -- >> 1.7.1 >> >> > > . >
On Fri, Dec 18, 2015 at 09:58:20AM +0800, majun (F) wrote: > Hi Mark: > > ? 2015/12/17 21:52, Mark Rutland ??: > > On Thu, Dec 17, 2015 at 07:56:34PM +0800, MaJun wrote: > >> From: Ma Jun <majun258@huawei.com> > [...] > >> +- compatible: Should be "hisilicon,mbigen-v2" > >> + > >> +- reg: Specifies the base physical address and size of the Mbigen > >> + registers. > >> + > >> +- interrupt controller: Identifies the node as an interrupt controller > >> + > >> +- msi-parent: Specifies the MSI controller this mbigen use. > >> + For more detail information,please refer to the generic msi-parent binding in > >> + Documentation/devicetree/bindings/interrupt-controller/msi.txt. > >> + > >> +- num-msis:Specifies the total number of interrupt this device has. > > > > Is this the number of pins implemented? Or the number of pins that are > > in use? > > > > The latter feels like something we can derive. > > num-msis means the total number of pins implemented. Ok. In that case I think it should be: - num-pins: the total number of pins implemented in this Mbigen instance. (with the appropriate fixups in the driver). With that: Acked-by: Mark Rutland <mark.rutland@arm.com> > >> +- #interrupt-cells : Specifies the number of cells needed to encode an > >> + interrupt source. The value must be 2. > >> + > >> + The 1st cell is hardware pin number of the interrupt.This number is local to > >> + each mbigen chip and in the range from 0 to the maximum interrupts number > >> + of the mbigen. > > > > Just to check: 0 - 63 represent the "reserved" pins, yes? > > Yes, you are right. > > > > > Other than those questions, this looks good to me. > > Do i need to post a new patch to update these two questions? Hopefully not. Marc, are you happy to fold in the s/num-msis/num-pins/ change? Thanks, Mark.
On 18/12/15 10:58, Mark Rutland wrote: > On Fri, Dec 18, 2015 at 09:58:20AM +0800, majun (F) wrote: >> Hi Mark: >> >> ? 2015/12/17 21:52, Mark Rutland ??: >>> On Thu, Dec 17, 2015 at 07:56:34PM +0800, MaJun wrote: >>>> From: Ma Jun <majun258@huawei.com> >> [...] >>>> +- compatible: Should be "hisilicon,mbigen-v2" >>>> + >>>> +- reg: Specifies the base physical address and size of the Mbigen >>>> + registers. >>>> + >>>> +- interrupt controller: Identifies the node as an interrupt controller >>>> + >>>> +- msi-parent: Specifies the MSI controller this mbigen use. >>>> + For more detail information,please refer to the generic msi-parent binding in >>>> + Documentation/devicetree/bindings/interrupt-controller/msi.txt. >>>> + >>>> +- num-msis:Specifies the total number of interrupt this device has. >>> >>> Is this the number of pins implemented? Or the number of pins that are >>> in use? >>> >>> The latter feels like something we can derive. >> >> num-msis means the total number of pins implemented. > > Ok. In that case I think it should be: > > - num-pins: the total number of pins implemented in this Mbigen > instance. > > (with the appropriate fixups in the driver). > > With that: > > Acked-by: Mark Rutland <mark.rutland@arm.com> > >>>> +- #interrupt-cells : Specifies the number of cells needed to encode an >>>> + interrupt source. The value must be 2. >>>> + >>>> + The 1st cell is hardware pin number of the interrupt.This number is local to >>>> + each mbigen chip and in the range from 0 to the maximum interrupts number >>>> + of the mbigen. >>> >>> Just to check: 0 - 63 represent the "reserved" pins, yes? >> >> Yes, you are right. >> >>> >>> Other than those questions, this looks good to me. >> >> Do i need to post a new patch to update these two questions? > > Hopefully not. > > Marc, are you happy to fold in the s/num-msis/num-pins/ change? Sure, I'll update the whole thing while merging it. Thanks, M.
On 18/12/15 10:58, Mark Rutland wrote: > On Fri, Dec 18, 2015 at 09:58:20AM +0800, majun (F) wrote: >> Hi Mark: >> >> ? 2015/12/17 21:52, Mark Rutland ??: >>> On Thu, Dec 17, 2015 at 07:56:34PM +0800, MaJun wrote: >>>> From: Ma Jun <majun258@huawei.com> >> [...] >>>> +- compatible: Should be "hisilicon,mbigen-v2" >>>> + >>>> +- reg: Specifies the base physical address and size of the Mbigen >>>> + registers. >>>> + >>>> +- interrupt controller: Identifies the node as an interrupt controller >>>> + >>>> +- msi-parent: Specifies the MSI controller this mbigen use. >>>> + For more detail information,please refer to the generic msi-parent binding in >>>> + Documentation/devicetree/bindings/interrupt-controller/msi.txt. >>>> + >>>> +- num-msis:Specifies the total number of interrupt this device has. >>> >>> Is this the number of pins implemented? Or the number of pins that are >>> in use? >>> >>> The latter feels like something we can derive. >> >> num-msis means the total number of pins implemented. > > Ok. In that case I think it should be: > > - num-pins: the total number of pins implemented in this Mbigen > instance. > > (with the appropriate fixups in the driver). > > With that: > > Acked-by: Mark Rutland <mark.rutland@arm.com> > >>>> +- #interrupt-cells : Specifies the number of cells needed to encode an >>>> + interrupt source. The value must be 2. >>>> + >>>> + The 1st cell is hardware pin number of the interrupt.This number is local to >>>> + each mbigen chip and in the range from 0 to the maximum interrupts number >>>> + of the mbigen. >>> >>> Just to check: 0 - 63 represent the "reserved" pins, yes? >> >> Yes, you are right. >> >>> >>> Other than those questions, this looks good to me. >> >> Do i need to post a new patch to update these two questions? > > Hopefully not. > > Marc, are you happy to fold in the s/num-msis/num-pins/ change? FWIW, I'm also moving this to: Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.txt in order to match the new documentation conventions. Thanks, M.
On Fri, Dec 18, 2015 at 11:35:36AM +0000, Marc Zyngier wrote: > On 18/12/15 10:58, Mark Rutland wrote: > > Marc, are you happy to fold in the s/num-msis/num-pins/ change? > > FWIW, I'm also moving this to: > > Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.txt > > in order to match the new documentation conventions. Even better! My ack stil stands. Mark.
diff --git a/Documentation/devicetree/bindings/arm/mbigen.txt b/Documentation/devicetree/bindings/arm/mbigen.txt new file mode 100644 index 0000000..3eaa678 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mbigen.txt @@ -0,0 +1,74 @@ +Hisilicon mbigen device tree bindings. +======================================= + +Mbigen means: message based interrupt generator. + +MBI is kind of msi interrupt only used on Non-PCI devices. + +To reduce the wired interrupt number connected to GIC, +Hisilicon designed mbigen to collect and generate interrupt. + + +Non-pci devices can connect to mbigen and generate the +interrupt by writing ITS register. + +The mbigen chip and devices connect to mbigen have the following properties: + +Mbigen main node required properties: +------------------------------------------- +- compatible: Should be "hisilicon,mbigen-v2" + +- reg: Specifies the base physical address and size of the Mbigen + registers. + +- interrupt controller: Identifies the node as an interrupt controller + +- msi-parent: Specifies the MSI controller this mbigen use. + For more detail information,please refer to the generic msi-parent binding in + Documentation/devicetree/bindings/interrupt-controller/msi.txt. + +- num-msis:Specifies the total number of interrupt this device has. + +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value must be 2. + + The 1st cell is hardware pin number of the interrupt.This number is local to + each mbigen chip and in the range from 0 to the maximum interrupts number + of the mbigen. + + The 2nd cell is the interrupt trigger type. + The value of this cell should be: + 1: rising edge triggered + or + 4: high level triggered + +Examples: + + mbigen_device_gmac:intc { + compatible = "hisilicon,mbigen-v2"; + reg = <0x0 0xc0080000 0x0 0x10000>; + interrupt-controller; + msi-parent = <&its_dsa 0x40b1c>; + num-msis = <9>; + #interrupt-cells = <2>; + }; + +Devices connect to mbigen required properties: +---------------------------------------------------- +-interrupt-parent: Specifies the mbigen device node which device connected. + +-interrupts:Specifies the interrupt source. + For the specific information of each cell in this property,please refer to + the "interrupt-cells" description mentioned above. + +Examples: + gmac0: ethernet@c2080000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0xc2080000 0 0x20000>, + <0 0xc0000000 0 0x1000>; + interrupt-parent = <&mbigen_device_gmac>; + interrupts = <656 1>, + <657 1>; + }; +