diff mbox

[v5,1/6] clk: hisilicon: add CRG driver for hi3519 soc

Message ID 1452219400-32478-2-git-send-email-xuejiancheng@huawei.com (mailing list archive)
State New, archived
Headers show

Commit Message

Jiancheng Xue Jan. 8, 2016, 2:16 a.m. UTC 
The CRG(Clock and Reset Generator) block provides clock
and reset signals for other modules in hi3519 soc.

Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
---
 .../devicetree/bindings/clock/hi3519-crg.txt       |  46 ++++++++
 drivers/clk/hisilicon/Kconfig                      |   7 ++
 drivers/clk/hisilicon/Makefile                     |   2 +
 drivers/clk/hisilicon/clk-hi3519.c                 | 105 +++++++++++++++++
 drivers/clk/hisilicon/reset.c                      | 129 +++++++++++++++++++++
 drivers/clk/hisilicon/reset.h                      |  32 +++++
 include/dt-bindings/clock/hi3519-clock.h           |  43 +++++++
 7 files changed, 364 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/hi3519-crg.txt
 create mode 100644 drivers/clk/hisilicon/clk-hi3519.c
 create mode 100644 drivers/clk/hisilicon/reset.c
 create mode 100644 drivers/clk/hisilicon/reset.h
 create mode 100644 include/dt-bindings/clock/hi3519-clock.h

Comments

kernel test robot Jan. 9, 2016, 6:24 a.m. UTC | #1 
Hi Jiancheng,

[auto build test ERROR on robh/for-next]
[also build test ERROR on v4.4-rc8 next-20160108]
[if your patch is applied to the wrong git tree, please drop us a note to help improving the system]

url:    https://github.com/0day-ci/linux/commits/Jiancheng-Xue/ARM-hisi-Add-initial-support-including-clock-driver-for-Hi3519-soc/20160108-103510
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux for-next
config: arm-allmodconfig (attached as .config)
reproduce:
        wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=arm 

All errors (new ones prefixed by >>):

>> ERROR: "hisi_reset_init" [drivers/clk/hisilicon/clk-hi3519.ko] undefined!
>> ERROR: "hisi_clk_register_gate" [drivers/clk/hisilicon/clk-hi3519.ko] undefined!
>> ERROR: "hisi_clk_register_mux" [drivers/clk/hisilicon/clk-hi3519.ko] undefined!
>> ERROR: "hisi_clk_register_fixed_rate" [drivers/clk/hisilicon/clk-hi3519.ko] undefined!
>> ERROR: "hisi_clk_init" [drivers/clk/hisilicon/clk-hi3519.ko] undefined!

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation
Rob Herring Jan. 9, 2016, 3:33 p.m. UTC | #2 
On Fri, Jan 08, 2016 at 10:16:35AM +0800, Jiancheng Xue wrote:
> The CRG(Clock and Reset Generator) block provides clock
> and reset signals for other modules in hi3519 soc.
> 
> Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>

[...]

> diff --git a/drivers/clk/hisilicon/clk-hi3519.c b/drivers/clk/hisilicon/clk-hi3519.c
> new file mode 100644
> index 0000000..72d3a7b0
> --- /dev/null
> +++ b/drivers/clk/hisilicon/clk-hi3519.c
> @@ -0,0 +1,105 @@
> +/*
> + * Hi3519 Clock Driver
> + *
> + * Copyright (c) 2015-2016 HiSilicon Technologies Co., Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <dt-bindings/clock/hi3519-clock.h>
> +#include <linux/delay.h>
> +#include <linux/of_address.h>
> +#include <linux/slab.h>
> +#include "clk.h"
> +#include "reset.h"
> +
> +#define HI3519_FIXED_24M	(HI3519_EXT_CLKS + 1)

This is fragile because HI3519_EXT_CLKS will change every time you 
add a clock to DT and means you have to keep the kernel and DT in sync. 

I'd be less worried if your clock definitions were more complete, but 
I'm guess the SOC has more than 19 clocks coming out of the clock 
controller.

> +#define HI3519_FIXED_50M	(HI3519_EXT_CLKS + 2)
> +#define HI3519_FIXED_75M	(HI3519_EXT_CLKS + 3)
> +#define HI3519_FIXED_125M	(HI3519_EXT_CLKS + 4)
> +#define HI3519_FIXED_150M	(HI3519_EXT_CLKS + 5)
> +#define HI3519_FIXED_200M	(HI3519_EXT_CLKS + 6)
> +#define HI3519_FIXED_250M	(HI3519_EXT_CLKS + 7)
> +#define HI3519_FIXED_300M	(HI3519_EXT_CLKS + 8)
> +#define HI3519_FIXED_400M	(HI3519_EXT_CLKS + 9)
> +#define HI3519_FMC_MUX		(HI3519_EXT_CLKS + 10)
> +
> +#define HI3519_NR_CLKS	128

You only have 29 clocks defined.


> +#ifndef __DTS_HI3519_CLOCK_H
> +#define __DTS_HI3519_CLOCK_H
> +
> +#define HI3519_FIXED_3M			1
> +#define HI3519_FMC_CLK			2
> +#define HI3519_USB2_BUS_CLK		3
> +#define HI3519_USB2_PORT_CLK		4
> +#define HI3519_USB3_CLK			5
> +#define HI3519_ETH_PHY_CLK		6
> +#define HI3519_ETH_MAC_CLK		7
> +#define HI3519_ETH_MACIF_CLK		8
> +#define HI3519_PWM_CLK			9
> +#define HI3519_DMA_CLK			10
> +#define HI3519_SPI0_CLK			11
> +#define HI3519_SPI1_CLK			12
> +#define HI3519_SPI2_CLK			13
> +#define HI3519_IR_CLK			14
> +#define HI3519_UART0_CLK		15
> +#define HI3519_UART1_CLK		16
> +#define HI3519_UART2_CLK		17
> +#define HI3519_UART3_CLK		18
> +#define HI3519_UART4_CLK		19
> +
> +#define HI3519_EXT_CLKS			19
> +
> +#endif	/* __DTS_HI3519_CLOCK_H */
Jiancheng Xue Jan. 11, 2016, 3:47 a.m. UTC | #3 
Hi Rob,

On 2016/1/9 23:33, Rob Herring wrote:
> On Fri, Jan 08, 2016 at 10:16:35AM +0800, Jiancheng Xue wrote:
>> The CRG(Clock and Reset Generator) block provides clock
>> and reset signals for other modules in hi3519 soc.
>>
>> Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
> 
> [...]
> 
>> diff --git a/drivers/clk/hisilicon/clk-hi3519.c b/drivers/clk/hisilicon/clk-hi3519.c
>> new file mode 100644
>> index 0000000..72d3a7b0
>> --- /dev/null
>> +++ b/drivers/clk/hisilicon/clk-hi3519.c
>> @@ -0,0 +1,105 @@
>> +/*
>> + * Hi3519 Clock Driver
>> + *
>> + * Copyright (c) 2015-2016 HiSilicon Technologies Co., Ltd.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
>> + */
>> +
>> +#include <dt-bindings/clock/hi3519-clock.h>
>> +#include <linux/delay.h>
>> +#include <linux/of_address.h>
>> +#include <linux/slab.h>
>> +#include "clk.h"
>> +#include "reset.h"
>> +
>> +#define HI3519_FIXED_24M	(HI3519_EXT_CLKS + 1)
> 
> This is fragile because HI3519_EXT_CLKS will change every time you 
> add a clock to DT and means you have to keep the kernel and DT in sync. 
> 

The dependence is indeed unneeded. Thank you.

> I'd be less worried if your clock definitions were more complete, but 
> I'm guess the SOC has more than 19 clocks coming out of the clock 
> controller.
> 

You are right. Some clocks in the SOC are not defined in this patch. Because
there is no plan to upstream those blocks drivers using these clocks. The clocks
defined in this file will not referred by the DT. So it's also not proper to
put these definitions into the dt-bingdings header file.

I will change HI3519_EXT_CLKS to a large number to make sure that enough space
is reserved for external clocks?  Is it OK?

Your advise will be appreciated. Thank you.

>> +#define HI3519_FIXED_50M	(HI3519_EXT_CLKS + 2)
>> +#define HI3519_FIXED_75M	(HI3519_EXT_CLKS + 3)
>> +#define HI3519_FIXED_125M	(HI3519_EXT_CLKS + 4)
>> +#define HI3519_FIXED_150M	(HI3519_EXT_CLKS + 5)
>> +#define HI3519_FIXED_200M	(HI3519_EXT_CLKS + 6)
>> +#define HI3519_FIXED_250M	(HI3519_EXT_CLKS + 7)
>> +#define HI3519_FIXED_300M	(HI3519_EXT_CLKS + 8)
>> +#define HI3519_FIXED_400M	(HI3519_EXT_CLKS + 9)
>> +#define HI3519_FMC_MUX		(HI3519_EXT_CLKS + 10)
>> +
>> +#define HI3519_NR_CLKS	128
> 
> You only have 29 clocks defined.
> 
> 
>> +#ifndef __DTS_HI3519_CLOCK_H
>> +#define __DTS_HI3519_CLOCK_H
>> +
>> +#define HI3519_FIXED_3M			1
>> +#define HI3519_FMC_CLK			2
>> +#define HI3519_USB2_BUS_CLK		3
>> +#define HI3519_USB2_PORT_CLK		4
>> +#define HI3519_USB3_CLK			5
>> +#define HI3519_ETH_PHY_CLK		6
>> +#define HI3519_ETH_MAC_CLK		7
>> +#define HI3519_ETH_MACIF_CLK		8
>> +#define HI3519_PWM_CLK			9
>> +#define HI3519_DMA_CLK			10
>> +#define HI3519_SPI0_CLK			11
>> +#define HI3519_SPI1_CLK			12
>> +#define HI3519_SPI2_CLK			13
>> +#define HI3519_IR_CLK			14
>> +#define HI3519_UART0_CLK		15
>> +#define HI3519_UART1_CLK		16
>> +#define HI3519_UART2_CLK		17
>> +#define HI3519_UART3_CLK		18
>> +#define HI3519_UART4_CLK		19
>> +
>> +#define HI3519_EXT_CLKS			19
>> +
>> +#endif	/* __DTS_HI3519_CLOCK_H */
> 
> .
>
Stephen Boyd Jan. 12, 2016, 10:12 p.m. UTC | #4 
On 01/08, Jiancheng Xue wrote:
> diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
> index e434854..b6baebf 100644
> --- a/drivers/clk/hisilicon/Kconfig
> +++ b/drivers/clk/hisilicon/Kconfig
> @@ -1,3 +1,10 @@
> +config COMMON_CLK_HI3519
> +	tristate "Clock Driver for Hi3519"

It looks like this has to be bool. Otherwise it needs to be a
platform driver and the hisilicon APIs need to be exported and
lose their __init markings.

> +	depends on ARCH_HISI
> +	default y
> +	help
> +	  Build the clock driver for hi3519.
> +
>  config COMMON_CLK_HI6220
>  	bool "Hi6220 Clock Driver"
>  	depends on ARCH_HISI || COMPILE_TEST
> diff --git a/drivers/clk/hisilicon/clk-hi3519.c b/drivers/clk/hisilicon/clk-hi3519.c
> new file mode 100644
> index 0000000..72d3a7b0
> --- /dev/null
> +++ b/drivers/clk/hisilicon/clk-hi3519.c
> @@ -0,0 +1,105 @@
> +
> +#define HI3519_FIXED_24M	(HI3519_EXT_CLKS + 1)
> +#define HI3519_FIXED_50M	(HI3519_EXT_CLKS + 2)
> +#define HI3519_FIXED_75M	(HI3519_EXT_CLKS + 3)
> +#define HI3519_FIXED_125M	(HI3519_EXT_CLKS + 4)
> +#define HI3519_FIXED_150M	(HI3519_EXT_CLKS + 5)
> +#define HI3519_FIXED_200M	(HI3519_EXT_CLKS + 6)
> +#define HI3519_FIXED_250M	(HI3519_EXT_CLKS + 7)
> +#define HI3519_FIXED_300M	(HI3519_EXT_CLKS + 8)
> +#define HI3519_FIXED_400M	(HI3519_EXT_CLKS + 9)
> +#define HI3519_FMC_MUX		(HI3519_EXT_CLKS + 10)
> +
> +#define HI3519_NR_CLKS	128

Is this the same clock provider as the external clocks? I don't
understand why we're offsetting the clock numbering if we have
different providers. And if these are truly fixed clocks (except
for the mux) perhaps they're not even provided by this hardware
block, and are clocks that come from the board? If that's true
then I would expect them to be described in DT as fixed rate
clocks.

> +
> +static struct hisi_fixed_rate_clock hi3519_fixed_rate_clks[] __initdata = {
> +	{ HI3519_FIXED_3M, "3m", NULL, CLK_IS_ROOT, 3000000, },
> +	{ HI3519_FIXED_24M, "24m", NULL, CLK_IS_ROOT, 24000000, },
> +	{ HI3519_FIXED_50M, "50m", NULL, CLK_IS_ROOT, 50000000, },
> +	{ HI3519_FIXED_75M, "75m", NULL, CLK_IS_ROOT, 75000000, },
> +	{ HI3519_FIXED_125M, "125m", NULL, CLK_IS_ROOT, 125000000, },
> +	{ HI3519_FIXED_150M, "150m", NULL, CLK_IS_ROOT, 150000000, },
> +	{ HI3519_FIXED_200M, "200m", NULL, CLK_IS_ROOT, 200000000, },
> +	{ HI3519_FIXED_250M, "250m", NULL, CLK_IS_ROOT, 250000000, },
> +	{ HI3519_FIXED_300M, "300m", NULL, CLK_IS_ROOT, 300000000, },
> +	{ HI3519_FIXED_400M, "400m", NULL, CLK_IS_ROOT, 400000000, },
> +};
> +
> +static const char *fmc_mux_p[] __initconst = {

const char * const ?

> +		"24m", "75m", "125m", "150m", "200m", "250m", "300m", "400m", };
> +static u32 fmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6, 7};
> +
> +static struct hisi_mux_clock hi3519_mux_clks[] __initdata = {
> +	{ HI3519_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
> +		CLK_SET_RATE_PARENT, 0xc0, 2, 3, 0, fmc_mux_table, },
> +};
> +
> +static struct hisi_gate_clock hi3519_gate_clks[] __initdata = {

We should look into making these things const.

> +	/* fmc */
> +	{ HI3519_FMC_CLK, "clk_fmc", "fmc_mux",
> +		CLK_SET_RATE_PARENT, 0xc0, 1, 0, },
> +	/* uart */
> +	{ HI3519_UART0_CLK, "clk_uart0", "24m",
> +		CLK_SET_RATE_PARENT, 0xe4, 20, 0, },
> +	{ HI3519_UART1_CLK, "clk_uart1", "24m",
> +		CLK_SET_RATE_PARENT, 0xe4, 21, 0, },
> +	{ HI3519_UART2_CLK, "clk_uart2", "24m",
> +		CLK_SET_RATE_PARENT, 0xe4, 22, 0, },
> +	{ HI3519_UART3_CLK, "clk_uart3", "24m",
> +		CLK_SET_RATE_PARENT, 0xe4, 23, 0, },
> +	{ HI3519_UART4_CLK, "clk_uart4", "24m",
> +		CLK_SET_RATE_PARENT, 0xe4, 24, 0, },
> +	{ HI3519_SPI0_CLK, "clk_spi0", "50m",
> +		CLK_SET_RATE_PARENT, 0xe4, 16, 0, },
> +	{ HI3519_SPI1_CLK, "clk_spi1", "50m",
> +		CLK_SET_RATE_PARENT, 0xe4, 17, 0, },
> +	{ HI3519_SPI2_CLK, "clk_spi2", "50m",
> +		CLK_SET_RATE_PARENT, 0xe4, 18, 0, },
> +};
> +
> +static void __init hi3519_clk_init(struct device_node *np)
> +{
> +	struct hisi_clock_data *clk_data;
> +
> +
> +	clk_data = hisi_clk_init(np, HI3519_NR_CLKS);
> +	if (!clk_data)
> +		return;
> +
> +	hisi_clk_register_fixed_rate(hi3519_fixed_rate_clks,
> +				     ARRAY_SIZE(hi3519_fixed_rate_clks),
> +				     clk_data);
> +	hisi_clk_register_mux(hi3519_mux_clks, ARRAY_SIZE(hi3519_mux_clks),
> +					clk_data);
> +	hisi_clk_register_gate(hi3519_gate_clks,
> +			ARRAY_SIZE(hi3519_gate_clks), clk_data);
> +
> +	hisi_reset_init(np);
> +}
> +
> +CLK_OF_DECLARE(hi3519_clk, "hisilicon,hi3519-crg", hi3519_clk_init);
> diff --git a/drivers/clk/hisilicon/reset.h b/drivers/clk/hisilicon/reset.h
> new file mode 100644
> index 0000000..37856089
> --- /dev/null
> +++ b/drivers/clk/hisilicon/reset.h
> @@ -0,0 +1,32 @@
> +/*
> + * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef	__HISI_RESET_H
> +#define	__HISI_RESET_H
> +
> +#include <linux/of.h>

Drop this include and forward declare struct device_node instead.

> +
> +#ifdef CONFIG_RESET_CONTROLLER
> +int __init hisi_reset_init(struct device_node *np);

We don't need __init in header files.
Jiancheng Xue Jan. 13, 2016, 3:03 a.m. UTC | #5 
Hi Stephen,
   Thank you very much for your reply.

On 2016/1/13 6:12, Stephen Boyd wrote:
> On 01/08, Jiancheng Xue wrote:
>> diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
>> index e434854..b6baebf 100644
>> --- a/drivers/clk/hisilicon/Kconfig
>> +++ b/drivers/clk/hisilicon/Kconfig
>> @@ -1,3 +1,10 @@
>> +config COMMON_CLK_HI3519
>> +	tristate "Clock Driver for Hi3519"
> 
> It looks like this has to be bool. Otherwise it needs to be a
> platform driver and the hisilicon APIs need to be exported and
> lose their __init markings.
> 
Yes,it's a problem. I will fix it in next version. Thank you.

>> +	depends on ARCH_HISI
>> +	default y
>> +	help
>> +	  Build the clock driver for hi3519.
>> +
>>  config COMMON_CLK_HI6220
>>  	bool "Hi6220 Clock Driver"
>>  	depends on ARCH_HISI || COMPILE_TEST
>> diff --git a/drivers/clk/hisilicon/clk-hi3519.c b/drivers/clk/hisilicon/clk-hi3519.c
>> new file mode 100644
>> index 0000000..72d3a7b0
>> --- /dev/null
>> +++ b/drivers/clk/hisilicon/clk-hi3519.c
>> @@ -0,0 +1,105 @@
>> +
>> +#define HI3519_FIXED_24M	(HI3519_EXT_CLKS + 1)
>> +#define HI3519_FIXED_50M	(HI3519_EXT_CLKS + 2)
>> +#define HI3519_FIXED_75M	(HI3519_EXT_CLKS + 3)
>> +#define HI3519_FIXED_125M	(HI3519_EXT_CLKS + 4)
>> +#define HI3519_FIXED_150M	(HI3519_EXT_CLKS + 5)
>> +#define HI3519_FIXED_200M	(HI3519_EXT_CLKS + 6)
>> +#define HI3519_FIXED_250M	(HI3519_EXT_CLKS + 7)
>> +#define HI3519_FIXED_300M	(HI3519_EXT_CLKS + 8)
>> +#define HI3519_FIXED_400M	(HI3519_EXT_CLKS + 9)
>> +#define HI3519_FMC_MUX		(HI3519_EXT_CLKS + 10)
>> +
>> +#define HI3519_NR_CLKS	128
> 
> Is this the same clock provider as the external clocks? I don't
> understand why we're offsetting the clock numbering if we have
> different providers. And if these are truly fixed clocks (except
> for the mux) perhaps they're not even provided by this hardware
> block, and are clocks that come from the board? If that's true
> then I would expect them to be described in DT as fixed rate
> clocks.
> 
External clocks mentioned here are used directly as work clocks of other modules.
Clocks defined in this file (internal clocks) are used as parents of external
clocks. Internal clocks won't be referred by dts files and are just used in this driver.
So they are moved here from the header file.

External clocks and internal clocks are all generated by this CRG block. The input clock
of the CRG block is always connected to a crystal oscillator on the board. So only one
clock provider is defined here.

Some clocks generated by CRG won't change their rate during the system running. These clocks
are treated as fixed clocks here.

>> +
>> +static struct hisi_fixed_rate_clock hi3519_fixed_rate_clks[] __initdata = {
>> +	{ HI3519_FIXED_3M, "3m", NULL, CLK_IS_ROOT, 3000000, },
>> +	{ HI3519_FIXED_24M, "24m", NULL, CLK_IS_ROOT, 24000000, },
>> +	{ HI3519_FIXED_50M, "50m", NULL, CLK_IS_ROOT, 50000000, },
>> +	{ HI3519_FIXED_75M, "75m", NULL, CLK_IS_ROOT, 75000000, },
>> +	{ HI3519_FIXED_125M, "125m", NULL, CLK_IS_ROOT, 125000000, },
>> +	{ HI3519_FIXED_150M, "150m", NULL, CLK_IS_ROOT, 150000000, },
>> +	{ HI3519_FIXED_200M, "200m", NULL, CLK_IS_ROOT, 200000000, },
>> +	{ HI3519_FIXED_250M, "250m", NULL, CLK_IS_ROOT, 250000000, },
>> +	{ HI3519_FIXED_300M, "300m", NULL, CLK_IS_ROOT, 300000000, },
>> +	{ HI3519_FIXED_400M, "400m", NULL, CLK_IS_ROOT, 400000000, },
>> +};
>> +
>> +static const char *fmc_mux_p[] __initconst = {
> 
> const char * const ?
> 

OK.

>> +		"24m", "75m", "125m", "150m", "200m", "250m", "300m", "400m", };
>> +static u32 fmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6, 7};
>> +
>> +static struct hisi_mux_clock hi3519_mux_clks[] __initdata = {
>> +	{ HI3519_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
>> +		CLK_SET_RATE_PARENT, 0xc0, 2, 3, 0, fmc_mux_table, },
>> +};
>> +
>> +static struct hisi_gate_clock hi3519_gate_clks[] __initdata = {
> 
> We should look into making these things const.
> 
OK. I'll add this in next version.

>> +	/* fmc */
>> +	{ HI3519_FMC_CLK, "clk_fmc", "fmc_mux",
>> +		CLK_SET_RATE_PARENT, 0xc0, 1, 0, },
>> +	/* uart */
>> +	{ HI3519_UART0_CLK, "clk_uart0", "24m",
>> +		CLK_SET_RATE_PARENT, 0xe4, 20, 0, },
>> +	{ HI3519_UART1_CLK, "clk_uart1", "24m",
>> +		CLK_SET_RATE_PARENT, 0xe4, 21, 0, },
>> +	{ HI3519_UART2_CLK, "clk_uart2", "24m",
>> +		CLK_SET_RATE_PARENT, 0xe4, 22, 0, },
>> +	{ HI3519_UART3_CLK, "clk_uart3", "24m",
>> +		CLK_SET_RATE_PARENT, 0xe4, 23, 0, },
>> +	{ HI3519_UART4_CLK, "clk_uart4", "24m",
>> +		CLK_SET_RATE_PARENT, 0xe4, 24, 0, },
>> +	{ HI3519_SPI0_CLK, "clk_spi0", "50m",
>> +		CLK_SET_RATE_PARENT, 0xe4, 16, 0, },
>> +	{ HI3519_SPI1_CLK, "clk_spi1", "50m",
>> +		CLK_SET_RATE_PARENT, 0xe4, 17, 0, },
>> +	{ HI3519_SPI2_CLK, "clk_spi2", "50m",
>> +		CLK_SET_RATE_PARENT, 0xe4, 18, 0, },
>> +};
>> +
>> +static void __init hi3519_clk_init(struct device_node *np)
>> +{
>> +	struct hisi_clock_data *clk_data;
>> +
>> +
>> +	clk_data = hisi_clk_init(np, HI3519_NR_CLKS);
>> +	if (!clk_data)
>> +		return;
>> +
>> +	hisi_clk_register_fixed_rate(hi3519_fixed_rate_clks,
>> +				     ARRAY_SIZE(hi3519_fixed_rate_clks),
>> +				     clk_data);
>> +	hisi_clk_register_mux(hi3519_mux_clks, ARRAY_SIZE(hi3519_mux_clks),
>> +					clk_data);
>> +	hisi_clk_register_gate(hi3519_gate_clks,
>> +			ARRAY_SIZE(hi3519_gate_clks), clk_data);
>> +
>> +	hisi_reset_init(np);
>> +}
>> +
>> +CLK_OF_DECLARE(hi3519_clk, "hisilicon,hi3519-crg", hi3519_clk_init);
>> diff --git a/drivers/clk/hisilicon/reset.h b/drivers/clk/hisilicon/reset.h
>> new file mode 100644
>> index 0000000..37856089
>> --- /dev/null
>> +++ b/drivers/clk/hisilicon/reset.h
>> @@ -0,0 +1,32 @@
>> +/*
>> + * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
>> + */
>> +
>> +#ifndef	__HISI_RESET_H
>> +#define	__HISI_RESET_H
>> +
>> +#include <linux/of.h>
> 
> Drop this include and forward declare struct device_node instead.
> 

OK.

>> +
>> +#ifdef CONFIG_RESET_CONTROLLER
>> +int __init hisi_reset_init(struct device_node *np);
> 
> We don't need __init in header files.
> 
OK. I'll remove it. Thank you.

Jiancheng
.
Michael Turquette Jan. 13, 2016, 6:57 p.m. UTC | #6 
Quoting xuejiancheng (2016-01-12 19:03:01)
> Hi Stephen,
>    Thank you very much for your reply.
> 
> On 2016/1/13 6:12, Stephen Boyd wrote:
> > On 01/08, Jiancheng Xue wrote:
> >> diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
> >> index e434854..b6baebf 100644
> >> --- a/drivers/clk/hisilicon/Kconfig
> >> +++ b/drivers/clk/hisilicon/Kconfig
> >> @@ -1,3 +1,10 @@
> >> +config COMMON_CLK_HI3519
> >> +    tristate "Clock Driver for Hi3519"
> > 
> > It looks like this has to be bool. Otherwise it needs to be a
> > platform driver and the hisilicon APIs need to be exported and
> > lose their __init markings.
> > 
> Yes,it's a problem. I will fix it in next version. Thank you.

The best solution would be to make this clock driver a real platform
driver.

Regards,
Mike

> 
> >> +    depends on ARCH_HISI
> >> +    default y
> >> +    help
> >> +      Build the clock driver for hi3519.
> >> +
> >>  config COMMON_CLK_HI6220
> >>      bool "Hi6220 Clock Driver"
> >>      depends on ARCH_HISI || COMPILE_TEST
> >> diff --git a/drivers/clk/hisilicon/clk-hi3519.c b/drivers/clk/hisilicon/clk-hi3519.c
> >> new file mode 100644
> >> index 0000000..72d3a7b0
> >> --- /dev/null
> >> +++ b/drivers/clk/hisilicon/clk-hi3519.c
> >> @@ -0,0 +1,105 @@
> >> +
> >> +#define HI3519_FIXED_24M    (HI3519_EXT_CLKS + 1)
> >> +#define HI3519_FIXED_50M    (HI3519_EXT_CLKS + 2)
> >> +#define HI3519_FIXED_75M    (HI3519_EXT_CLKS + 3)
> >> +#define HI3519_FIXED_125M   (HI3519_EXT_CLKS + 4)
> >> +#define HI3519_FIXED_150M   (HI3519_EXT_CLKS + 5)
> >> +#define HI3519_FIXED_200M   (HI3519_EXT_CLKS + 6)
> >> +#define HI3519_FIXED_250M   (HI3519_EXT_CLKS + 7)
> >> +#define HI3519_FIXED_300M   (HI3519_EXT_CLKS + 8)
> >> +#define HI3519_FIXED_400M   (HI3519_EXT_CLKS + 9)
> >> +#define HI3519_FMC_MUX              (HI3519_EXT_CLKS + 10)
> >> +
> >> +#define HI3519_NR_CLKS      128
> > 
> > Is this the same clock provider as the external clocks? I don't
> > understand why we're offsetting the clock numbering if we have
> > different providers. And if these are truly fixed clocks (except
> > for the mux) perhaps they're not even provided by this hardware
> > block, and are clocks that come from the board? If that's true
> > then I would expect them to be described in DT as fixed rate
> > clocks.
> > 
> External clocks mentioned here are used directly as work clocks of other modules.
> Clocks defined in this file (internal clocks) are used as parents of external
> clocks. Internal clocks won't be referred by dts files and are just used in this driver.
> So they are moved here from the header file.
> 
> External clocks and internal clocks are all generated by this CRG block. The input clock
> of the CRG block is always connected to a crystal oscillator on the board. So only one
> clock provider is defined here.
> 
> Some clocks generated by CRG won't change their rate during the system running. These clocks
> are treated as fixed clocks here.
> 
> >> +
> >> +static struct hisi_fixed_rate_clock hi3519_fixed_rate_clks[] __initdata = {
> >> +    { HI3519_FIXED_3M, "3m", NULL, CLK_IS_ROOT, 3000000, },
> >> +    { HI3519_FIXED_24M, "24m", NULL, CLK_IS_ROOT, 24000000, },
> >> +    { HI3519_FIXED_50M, "50m", NULL, CLK_IS_ROOT, 50000000, },
> >> +    { HI3519_FIXED_75M, "75m", NULL, CLK_IS_ROOT, 75000000, },
> >> +    { HI3519_FIXED_125M, "125m", NULL, CLK_IS_ROOT, 125000000, },
> >> +    { HI3519_FIXED_150M, "150m", NULL, CLK_IS_ROOT, 150000000, },
> >> +    { HI3519_FIXED_200M, "200m", NULL, CLK_IS_ROOT, 200000000, },
> >> +    { HI3519_FIXED_250M, "250m", NULL, CLK_IS_ROOT, 250000000, },
> >> +    { HI3519_FIXED_300M, "300m", NULL, CLK_IS_ROOT, 300000000, },
> >> +    { HI3519_FIXED_400M, "400m", NULL, CLK_IS_ROOT, 400000000, },
> >> +};
> >> +
> >> +static const char *fmc_mux_p[] __initconst = {
> > 
> > const char * const ?
> > 
> 
> OK.
> 
> >> +            "24m", "75m", "125m", "150m", "200m", "250m", "300m", "400m", };
> >> +static u32 fmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6, 7};
> >> +
> >> +static struct hisi_mux_clock hi3519_mux_clks[] __initdata = {
> >> +    { HI3519_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
> >> +            CLK_SET_RATE_PARENT, 0xc0, 2, 3, 0, fmc_mux_table, },
> >> +};
> >> +
> >> +static struct hisi_gate_clock hi3519_gate_clks[] __initdata = {
> > 
> > We should look into making these things const.
> > 
> OK. I'll add this in next version.
> 
> >> +    /* fmc */
> >> +    { HI3519_FMC_CLK, "clk_fmc", "fmc_mux",
> >> +            CLK_SET_RATE_PARENT, 0xc0, 1, 0, },
> >> +    /* uart */
> >> +    { HI3519_UART0_CLK, "clk_uart0", "24m",
> >> +            CLK_SET_RATE_PARENT, 0xe4, 20, 0, },
> >> +    { HI3519_UART1_CLK, "clk_uart1", "24m",
> >> +            CLK_SET_RATE_PARENT, 0xe4, 21, 0, },
> >> +    { HI3519_UART2_CLK, "clk_uart2", "24m",
> >> +            CLK_SET_RATE_PARENT, 0xe4, 22, 0, },
> >> +    { HI3519_UART3_CLK, "clk_uart3", "24m",
> >> +            CLK_SET_RATE_PARENT, 0xe4, 23, 0, },
> >> +    { HI3519_UART4_CLK, "clk_uart4", "24m",
> >> +            CLK_SET_RATE_PARENT, 0xe4, 24, 0, },
> >> +    { HI3519_SPI0_CLK, "clk_spi0", "50m",
> >> +            CLK_SET_RATE_PARENT, 0xe4, 16, 0, },
> >> +    { HI3519_SPI1_CLK, "clk_spi1", "50m",
> >> +            CLK_SET_RATE_PARENT, 0xe4, 17, 0, },
> >> +    { HI3519_SPI2_CLK, "clk_spi2", "50m",
> >> +            CLK_SET_RATE_PARENT, 0xe4, 18, 0, },
> >> +};
> >> +
> >> +static void __init hi3519_clk_init(struct device_node *np)
> >> +{
> >> +    struct hisi_clock_data *clk_data;
> >> +
> >> +
> >> +    clk_data = hisi_clk_init(np, HI3519_NR_CLKS);
> >> +    if (!clk_data)
> >> +            return;
> >> +
> >> +    hisi_clk_register_fixed_rate(hi3519_fixed_rate_clks,
> >> +                                 ARRAY_SIZE(hi3519_fixed_rate_clks),
> >> +                                 clk_data);
> >> +    hisi_clk_register_mux(hi3519_mux_clks, ARRAY_SIZE(hi3519_mux_clks),
> >> +                                    clk_data);
> >> +    hisi_clk_register_gate(hi3519_gate_clks,
> >> +                    ARRAY_SIZE(hi3519_gate_clks), clk_data);
> >> +
> >> +    hisi_reset_init(np);
> >> +}
> >> +
> >> +CLK_OF_DECLARE(hi3519_clk, "hisilicon,hi3519-crg", hi3519_clk_init);
> >> diff --git a/drivers/clk/hisilicon/reset.h b/drivers/clk/hisilicon/reset.h
> >> new file mode 100644
> >> index 0000000..37856089
> >> --- /dev/null
> >> +++ b/drivers/clk/hisilicon/reset.h
> >> @@ -0,0 +1,32 @@
> >> +/*
> >> + * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
> >> + *
> >> + * This program is free software; you can redistribute it and/or modify
> >> + * it under the terms of the GNU General Public License as published by
> >> + * the Free Software Foundation; either version 2 of the License, or
> >> + * (at your option) any later version.
> >> + *
> >> + * This program is distributed in the hope that it will be useful,
> >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> >> + * GNU General Public License for more details.
> >> + *
> >> + * You should have received a copy of the GNU General Public License
> >> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> >> + */
> >> +
> >> +#ifndef     __HISI_RESET_H
> >> +#define     __HISI_RESET_H
> >> +
> >> +#include <linux/of.h>
> > 
> > Drop this include and forward declare struct device_node instead.
> > 
> 
> OK.
> 
> >> +
> >> +#ifdef CONFIG_RESET_CONTROLLER
> >> +int __init hisi_reset_init(struct device_node *np);
> > 
> > We don't need __init in header files.
> > 
> OK. I'll remove it. Thank you.
> 
> Jiancheng
> .
>
Jiancheng Xue Jan. 14, 2016, 1:16 p.m. UTC | #7 
Hi Mike,

On 2016/1/14 2:57, Michael Turquette wrote:
> Quoting xuejiancheng (2016-01-12 19:03:01)
>> Hi Stephen,
>>    Thank you very much for your reply.
>>
>> On 2016/1/13 6:12, Stephen Boyd wrote:
>>> On 01/08, Jiancheng Xue wrote:
>>>> diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
>>>> index e434854..b6baebf 100644
>>>> --- a/drivers/clk/hisilicon/Kconfig
>>>> +++ b/drivers/clk/hisilicon/Kconfig
>>>> @@ -1,3 +1,10 @@
>>>> +config COMMON_CLK_HI3519
>>>> +    tristate "Clock Driver for Hi3519"
>>>
>>> It looks like this has to be bool. Otherwise it needs to be a
>>> platform driver and the hisilicon APIs need to be exported and
>>> lose their __init markings.
>>>
>> Yes,it's a problem. I will fix it in next version. Thank you.
> 
> The best solution would be to make this clock driver a real platform
> driver.
> 
Now the work clock of the clocksource timer-sp804 is provided by this driver. So
it need to be registered early by CLK_OF_DECLARE. If the timer clock is treated
as a fixed-clock provider, this driver can be implemented as a platform driver.
Then the crg device must be registered before other clock consumer devices.Accordingly
the crg device node must be written above all other clock consumer devices node in dts files.
I think it is also a dependence.

Can you help me understand why it is better to make this driver a platform driver?
Thank you very much!

> Regards,
> Mike
> 
>>
>>>> +    depends on ARCH_HISI
>>>> +    default y
>>>> +    help
>>>> +      Build the clock driver for hi3519.
>>>> +
>>>>  config COMMON_CLK_HI6220
>>>>      bool "Hi6220 Clock Driver"
>>>>      depends on ARCH_HISI || COMPILE_TEST
>>>> diff --git a/drivers/clk/hisilicon/clk-hi3519.c b/drivers/clk/hisilicon/clk-hi3519.c
>>>> new file mode 100644
>>>> index 0000000..72d3a7b0
>>>> --- /dev/null
>>>> +++ b/drivers/clk/hisilicon/clk-hi3519.c
>>>> @@ -0,0 +1,105 @@
>>>> +
>>>> +#define HI3519_FIXED_24M    (HI3519_EXT_CLKS + 1)
>>>> +#define HI3519_FIXED_50M    (HI3519_EXT_CLKS + 2)
>>>> +#define HI3519_FIXED_75M    (HI3519_EXT_CLKS + 3)
>>>> +#define HI3519_FIXED_125M   (HI3519_EXT_CLKS + 4)
>>>> +#define HI3519_FIXED_150M   (HI3519_EXT_CLKS + 5)
>>>> +#define HI3519_FIXED_200M   (HI3519_EXT_CLKS + 6)
>>>> +#define HI3519_FIXED_250M   (HI3519_EXT_CLKS + 7)
>>>> +#define HI3519_FIXED_300M   (HI3519_EXT_CLKS + 8)
>>>> +#define HI3519_FIXED_400M   (HI3519_EXT_CLKS + 9)
>>>> +#define HI3519_FMC_MUX              (HI3519_EXT_CLKS + 10)
>>>> +
>>>> +#define HI3519_NR_CLKS      128
>>>
>>> Is this the same clock provider as the external clocks? I don't
>>> understand why we're offsetting the clock numbering if we have
>>> different providers. And if these are truly fixed clocks (except
>>> for the mux) perhaps they're not even provided by this hardware
>>> block, and are clocks that come from the board? If that's true
>>> then I would expect them to be described in DT as fixed rate
>>> clocks.
>>>
>> External clocks mentioned here are used directly as work clocks of other modules.
>> Clocks defined in this file (internal clocks) are used as parents of external
>> clocks. Internal clocks won't be referred by dts files and are just used in this driver.
>> So they are moved here from the header file.
>>
>> External clocks and internal clocks are all generated by this CRG block. The input clock
>> of the CRG block is always connected to a crystal oscillator on the board. So only one
>> clock provider is defined here.
>>
>> Some clocks generated by CRG won't change their rate during the system running. These clocks
>> are treated as fixed clocks here.
>>
>>>> +
>>>> +static struct hisi_fixed_rate_clock hi3519_fixed_rate_clks[] __initdata = {
>>>> +    { HI3519_FIXED_3M, "3m", NULL, CLK_IS_ROOT, 3000000, },
>>>> +    { HI3519_FIXED_24M, "24m", NULL, CLK_IS_ROOT, 24000000, },
>>>> +    { HI3519_FIXED_50M, "50m", NULL, CLK_IS_ROOT, 50000000, },
>>>> +    { HI3519_FIXED_75M, "75m", NULL, CLK_IS_ROOT, 75000000, },
>>>> +    { HI3519_FIXED_125M, "125m", NULL, CLK_IS_ROOT, 125000000, },
>>>> +    { HI3519_FIXED_150M, "150m", NULL, CLK_IS_ROOT, 150000000, },
>>>> +    { HI3519_FIXED_200M, "200m", NULL, CLK_IS_ROOT, 200000000, },
>>>> +    { HI3519_FIXED_250M, "250m", NULL, CLK_IS_ROOT, 250000000, },
>>>> +    { HI3519_FIXED_300M, "300m", NULL, CLK_IS_ROOT, 300000000, },
>>>> +    { HI3519_FIXED_400M, "400m", NULL, CLK_IS_ROOT, 400000000, },
>>>> +};
>>>> +
>>>> +static const char *fmc_mux_p[] __initconst = {
>>>
>>> const char * const ?
>>>
>>
>> OK.
>>
>>>> +            "24m", "75m", "125m", "150m", "200m", "250m", "300m", "400m", };
>>>> +static u32 fmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6, 7};
>>>> +
>>>> +static struct hisi_mux_clock hi3519_mux_clks[] __initdata = {
>>>> +    { HI3519_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
>>>> +            CLK_SET_RATE_PARENT, 0xc0, 2, 3, 0, fmc_mux_table, },
>>>> +};
>>>> +
>>>> +static struct hisi_gate_clock hi3519_gate_clks[] __initdata = {
>>>
>>> We should look into making these things const.
>>>
>> OK. I'll add this in next version.
>>
>>>> +    /* fmc */
>>>> +    { HI3519_FMC_CLK, "clk_fmc", "fmc_mux",
>>>> +            CLK_SET_RATE_PARENT, 0xc0, 1, 0, },
>>>> +    /* uart */
>>>> +    { HI3519_UART0_CLK, "clk_uart0", "24m",
>>>> +            CLK_SET_RATE_PARENT, 0xe4, 20, 0, },
>>>> +    { HI3519_UART1_CLK, "clk_uart1", "24m",
>>>> +            CLK_SET_RATE_PARENT, 0xe4, 21, 0, },
>>>> +    { HI3519_UART2_CLK, "clk_uart2", "24m",
>>>> +            CLK_SET_RATE_PARENT, 0xe4, 22, 0, },
>>>> +    { HI3519_UART3_CLK, "clk_uart3", "24m",
>>>> +            CLK_SET_RATE_PARENT, 0xe4, 23, 0, },
>>>> +    { HI3519_UART4_CLK, "clk_uart4", "24m",
>>>> +            CLK_SET_RATE_PARENT, 0xe4, 24, 0, },
>>>> +    { HI3519_SPI0_CLK, "clk_spi0", "50m",
>>>> +            CLK_SET_RATE_PARENT, 0xe4, 16, 0, },
>>>> +    { HI3519_SPI1_CLK, "clk_spi1", "50m",
>>>> +            CLK_SET_RATE_PARENT, 0xe4, 17, 0, },
>>>> +    { HI3519_SPI2_CLK, "clk_spi2", "50m",
>>>> +            CLK_SET_RATE_PARENT, 0xe4, 18, 0, },
>>>> +};
>>>> +
>>>> +static void __init hi3519_clk_init(struct device_node *np)
>>>> +{
>>>> +    struct hisi_clock_data *clk_data;
>>>> +
>>>> +
>>>> +    clk_data = hisi_clk_init(np, HI3519_NR_CLKS);
>>>> +    if (!clk_data)
>>>> +            return;
>>>> +
>>>> +    hisi_clk_register_fixed_rate(hi3519_fixed_rate_clks,
>>>> +                                 ARRAY_SIZE(hi3519_fixed_rate_clks),
>>>> +                                 clk_data);
>>>> +    hisi_clk_register_mux(hi3519_mux_clks, ARRAY_SIZE(hi3519_mux_clks),
>>>> +                                    clk_data);
>>>> +    hisi_clk_register_gate(hi3519_gate_clks,
>>>> +                    ARRAY_SIZE(hi3519_gate_clks), clk_data);
>>>> +
>>>> +    hisi_reset_init(np);
>>>> +}
>>>> +
>>>> +CLK_OF_DECLARE(hi3519_clk, "hisilicon,hi3519-crg", hi3519_clk_init);
>>>> diff --git a/drivers/clk/hisilicon/reset.h b/drivers/clk/hisilicon/reset.h
>>>> new file mode 100644
>>>> index 0000000..37856089
>>>> --- /dev/null
>>>> +++ b/drivers/clk/hisilicon/reset.h
>>>> @@ -0,0 +1,32 @@
>>>> +/*
>>>> + * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
>>>> + *
>>>> + * This program is free software; you can redistribute it and/or modify
>>>> + * it under the terms of the GNU General Public License as published by
>>>> + * the Free Software Foundation; either version 2 of the License, or
>>>> + * (at your option) any later version.
>>>> + *
>>>> + * This program is distributed in the hope that it will be useful,
>>>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>>>> + * GNU General Public License for more details.
>>>> + *
>>>> + * You should have received a copy of the GNU General Public License
>>>> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
>>>> + */
>>>> +
>>>> +#ifndef     __HISI_RESET_H
>>>> +#define     __HISI_RESET_H
>>>> +
>>>> +#include <linux/of.h>
>>>
>>> Drop this include and forward declare struct device_node instead.
>>>
>>
>> OK.
>>
>>>> +
>>>> +#ifdef CONFIG_RESET_CONTROLLER
>>>> +int __init hisi_reset_init(struct device_node *np);
>>>
>>> We don't need __init in header files.
>>>
>> OK. I'll remove it. Thank you.
>>
>> Jiancheng
>> .
>>
> 
> .
>
Jiancheng Xue Jan. 15, 2016, 7:57 a.m. UTC | #8 
On 2016/1/14 21:16, xuejiancheng wrote:
> Hi Mike,
> 
> On 2016/1/14 2:57, Michael Turquette wrote:
>> Quoting xuejiancheng (2016-01-12 19:03:01)
>>> Hi Stephen,
>>>    Thank you very much for your reply.
>>>
>>> On 2016/1/13 6:12, Stephen Boyd wrote:
>>>> On 01/08, Jiancheng Xue wrote:
>>>>> diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
>>>>> index e434854..b6baebf 100644
>>>>> --- a/drivers/clk/hisilicon/Kconfig
>>>>> +++ b/drivers/clk/hisilicon/Kconfig
>>>>> @@ -1,3 +1,10 @@
>>>>> +config COMMON_CLK_HI3519
>>>>> +    tristate "Clock Driver for Hi3519"
>>>>
>>>> It looks like this has to be bool. Otherwise it needs to be a
>>>> platform driver and the hisilicon APIs need to be exported and
>>>> lose their __init markings.
>>>>
>>> Yes,it's a problem. I will fix it in next version. Thank you.
>>
>> The best solution would be to make this clock driver a real platform
>> driver.
>>
> Now the work clock of the clocksource timer-sp804 is provided by this driver. So
> it need to be registered early by CLK_OF_DECLARE. If the timer clock is treated
> as a fixed-clock provider, this driver can be implemented as a platform driver.
> Then the crg device must be registered before other clock consumer devices.Accordingly
> the crg device node must be written above all other clock consumer devices node in dts files.
> I think it is also a dependence.
> 
> Can you help me understand why it is better to make this driver a platform driver?
> Thank you very much!
> 
arch_initcall(customize_machine)
-->of_platform_populate
   -->of_platform_bus_create
     -->of_amba_device_create
	-->amba_device_add
	   -->amba_get_enable_pclk
The call sequence above shows that the clock of the amba device must be registered before
amba_device_add. The clock of "arm,pl011" uart is registered in the probe function of the
platform driver "hi3519-crg". So the platform device "hi3519-crg" must be created before
the amba device "arm,pl011" uart.

If this is not a problem, I'll change this to a platform driver in next version.

Thank you.

Regards?
Jiancheng

>> Regards,
>> Mike
>>
>>>
>>>>> +    depends on ARCH_HISI
>>>>> +    default y
>>>>> +    help
>>>>> +      Build the clock driver for hi3519.
>>>>> +
>>>>>  config COMMON_CLK_HI6220
>>>>>      bool "Hi6220 Clock Driver"
>>>>>      depends on ARCH_HISI || COMPILE_TEST
>>>>> diff --git a/drivers/clk/hisilicon/clk-hi3519.c b/drivers/clk/hisilicon/clk-hi3519.c
>>>>> new file mode 100644
>>>>> index 0000000..72d3a7b0
>>>>> --- /dev/null
>>>>> +++ b/drivers/clk/hisilicon/clk-hi3519.c
>>>>> @@ -0,0 +1,105 @@
>>>>> +
>>>>> +#define HI3519_FIXED_24M    (HI3519_EXT_CLKS + 1)
>>>>> +#define HI3519_FIXED_50M    (HI3519_EXT_CLKS + 2)
>>>>> +#define HI3519_FIXED_75M    (HI3519_EXT_CLKS + 3)
>>>>> +#define HI3519_FIXED_125M   (HI3519_EXT_CLKS + 4)
>>>>> +#define HI3519_FIXED_150M   (HI3519_EXT_CLKS + 5)
>>>>> +#define HI3519_FIXED_200M   (HI3519_EXT_CLKS + 6)
>>>>> +#define HI3519_FIXED_250M   (HI3519_EXT_CLKS + 7)
>>>>> +#define HI3519_FIXED_300M   (HI3519_EXT_CLKS + 8)
>>>>> +#define HI3519_FIXED_400M   (HI3519_EXT_CLKS + 9)
>>>>> +#define HI3519_FMC_MUX              (HI3519_EXT_CLKS + 10)
>>>>> +
>>>>> +#define HI3519_NR_CLKS      128
>>>>
>>>> Is this the same clock provider as the external clocks? I don't
>>>> understand why we're offsetting the clock numbering if we have
>>>> different providers. And if these are truly fixed clocks (except
>>>> for the mux) perhaps they're not even provided by this hardware
>>>> block, and are clocks that come from the board? If that's true
>>>> then I would expect them to be described in DT as fixed rate
>>>> clocks.
>>>>
>>> External clocks mentioned here are used directly as work clocks of other modules.
>>> Clocks defined in this file (internal clocks) are used as parents of external
>>> clocks. Internal clocks won't be referred by dts files and are just used in this driver.
>>> So they are moved here from the header file.
>>>
>>> External clocks and internal clocks are all generated by this CRG block. The input clock
>>> of the CRG block is always connected to a crystal oscillator on the board. So only one
>>> clock provider is defined here.
>>>
>>> Some clocks generated by CRG won't change their rate during the system running. These clocks
>>> are treated as fixed clocks here.
>>>
>>>>> +
>>>>> +static struct hisi_fixed_rate_clock hi3519_fixed_rate_clks[] __initdata = {
>>>>> +    { HI3519_FIXED_3M, "3m", NULL, CLK_IS_ROOT, 3000000, },
>>>>> +    { HI3519_FIXED_24M, "24m", NULL, CLK_IS_ROOT, 24000000, },
>>>>> +    { HI3519_FIXED_50M, "50m", NULL, CLK_IS_ROOT, 50000000, },
>>>>> +    { HI3519_FIXED_75M, "75m", NULL, CLK_IS_ROOT, 75000000, },
>>>>> +    { HI3519_FIXED_125M, "125m", NULL, CLK_IS_ROOT, 125000000, },
>>>>> +    { HI3519_FIXED_150M, "150m", NULL, CLK_IS_ROOT, 150000000, },
>>>>> +    { HI3519_FIXED_200M, "200m", NULL, CLK_IS_ROOT, 200000000, },
>>>>> +    { HI3519_FIXED_250M, "250m", NULL, CLK_IS_ROOT, 250000000, },
>>>>> +    { HI3519_FIXED_300M, "300m", NULL, CLK_IS_ROOT, 300000000, },
>>>>> +    { HI3519_FIXED_400M, "400m", NULL, CLK_IS_ROOT, 400000000, },
>>>>> +};
>>>>> +
>>>>> +static const char *fmc_mux_p[] __initconst = {
>>>>
>>>> const char * const ?
>>>>
>>>
>>> OK.
>>>
>>>>> +            "24m", "75m", "125m", "150m", "200m", "250m", "300m", "400m", };
>>>>> +static u32 fmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6, 7};
>>>>> +
>>>>> +static struct hisi_mux_clock hi3519_mux_clks[] __initdata = {
>>>>> +    { HI3519_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
>>>>> +            CLK_SET_RATE_PARENT, 0xc0, 2, 3, 0, fmc_mux_table, },
>>>>> +};
>>>>> +
>>>>> +static struct hisi_gate_clock hi3519_gate_clks[] __initdata = {
>>>>
>>>> We should look into making these things const.
>>>>
>>> OK. I'll add this in next version.
>>>
>>>>> +    /* fmc */
>>>>> +    { HI3519_FMC_CLK, "clk_fmc", "fmc_mux",
>>>>> +            CLK_SET_RATE_PARENT, 0xc0, 1, 0, },
>>>>> +    /* uart */
>>>>> +    { HI3519_UART0_CLK, "clk_uart0", "24m",
>>>>> +            CLK_SET_RATE_PARENT, 0xe4, 20, 0, },
>>>>> +    { HI3519_UART1_CLK, "clk_uart1", "24m",
>>>>> +            CLK_SET_RATE_PARENT, 0xe4, 21, 0, },
>>>>> +    { HI3519_UART2_CLK, "clk_uart2", "24m",
>>>>> +            CLK_SET_RATE_PARENT, 0xe4, 22, 0, },
>>>>> +    { HI3519_UART3_CLK, "clk_uart3", "24m",
>>>>> +            CLK_SET_RATE_PARENT, 0xe4, 23, 0, },
>>>>> +    { HI3519_UART4_CLK, "clk_uart4", "24m",
>>>>> +            CLK_SET_RATE_PARENT, 0xe4, 24, 0, },
>>>>> +    { HI3519_SPI0_CLK, "clk_spi0", "50m",
>>>>> +            CLK_SET_RATE_PARENT, 0xe4, 16, 0, },
>>>>> +    { HI3519_SPI1_CLK, "clk_spi1", "50m",
>>>>> +            CLK_SET_RATE_PARENT, 0xe4, 17, 0, },
>>>>> +    { HI3519_SPI2_CLK, "clk_spi2", "50m",
>>>>> +            CLK_SET_RATE_PARENT, 0xe4, 18, 0, },
>>>>> +};
>>>>> +
>>>>> +static void __init hi3519_clk_init(struct device_node *np)
>>>>> +{
>>>>> +    struct hisi_clock_data *clk_data;
>>>>> +
>>>>> +
>>>>> +    clk_data = hisi_clk_init(np, HI3519_NR_CLKS);
>>>>> +    if (!clk_data)
>>>>> +            return;
>>>>> +
>>>>> +    hisi_clk_register_fixed_rate(hi3519_fixed_rate_clks,
>>>>> +                                 ARRAY_SIZE(hi3519_fixed_rate_clks),
>>>>> +                                 clk_data);
>>>>> +    hisi_clk_register_mux(hi3519_mux_clks, ARRAY_SIZE(hi3519_mux_clks),
>>>>> +                                    clk_data);
>>>>> +    hisi_clk_register_gate(hi3519_gate_clks,
>>>>> +                    ARRAY_SIZE(hi3519_gate_clks), clk_data);
>>>>> +
>>>>> +    hisi_reset_init(np);
>>>>> +}
>>>>> +
>>>>> +CLK_OF_DECLARE(hi3519_clk, "hisilicon,hi3519-crg", hi3519_clk_init);
>>>>> diff --git a/drivers/clk/hisilicon/reset.h b/drivers/clk/hisilicon/reset.h
>>>>> new file mode 100644
>>>>> index 0000000..37856089
>>>>> --- /dev/null
>>>>> +++ b/drivers/clk/hisilicon/reset.h
>>>>> @@ -0,0 +1,32 @@
>>>>> +/*
>>>>> + * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
>>>>> + *
>>>>> + * This program is free software; you can redistribute it and/or modify
>>>>> + * it under the terms of the GNU General Public License as published by
>>>>> + * the Free Software Foundation; either version 2 of the License, or
>>>>> + * (at your option) any later version.
>>>>> + *
>>>>> + * This program is distributed in the hope that it will be useful,
>>>>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>>>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>>>>> + * GNU General Public License for more details.
>>>>> + *
>>>>> + * You should have received a copy of the GNU General Public License
>>>>> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
>>>>> + */
>>>>> +
>>>>> +#ifndef     __HISI_RESET_H
>>>>> +#define     __HISI_RESET_H
>>>>> +
>>>>> +#include <linux/of.h>
>>>>
>>>> Drop this include and forward declare struct device_node instead.
>>>>
>>>
>>> OK.
>>>
>>>>> +
>>>>> +#ifdef CONFIG_RESET_CONTROLLER
>>>>> +int __init hisi_reset_init(struct device_node *np);
>>>>
>>>> We don't need __init in header files.
>>>>
>>> OK. I'll remove it. Thank you.
>>>
>>> Jiancheng
>>> .
>>>
>>
>> .
>>
> 
> 
> .
>
Rob Herring Jan. 19, 2016, 6:20 p.m. UTC | #9 
On Fri, Jan 15, 2016 at 1:57 AM, xuejiancheng <xuejiancheng@huawei.com> wrote:
>
> On 2016/1/14 21:16, xuejiancheng wrote:
>> Hi Mike,
>>
>> On 2016/1/14 2:57, Michael Turquette wrote:
>>> Quoting xuejiancheng (2016-01-12 19:03:01)
>>>> Hi Stephen,
>>>>    Thank you very much for your reply.
>>>>
>>>> On 2016/1/13 6:12, Stephen Boyd wrote:
>>>>> On 01/08, Jiancheng Xue wrote:
>>>>>> diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
>>>>>> index e434854..b6baebf 100644
>>>>>> --- a/drivers/clk/hisilicon/Kconfig
>>>>>> +++ b/drivers/clk/hisilicon/Kconfig
>>>>>> @@ -1,3 +1,10 @@
>>>>>> +config COMMON_CLK_HI3519
>>>>>> +    tristate "Clock Driver for Hi3519"
>>>>>
>>>>> It looks like this has to be bool. Otherwise it needs to be a
>>>>> platform driver and the hisilicon APIs need to be exported and
>>>>> lose their __init markings.
>>>>>
>>>> Yes,it's a problem. I will fix it in next version. Thank you.
>>>
>>> The best solution would be to make this clock driver a real platform
>>> driver.
>>>
>> Now the work clock of the clocksource timer-sp804 is provided by this driver. So
>> it need to be registered early by CLK_OF_DECLARE. If the timer clock is treated
>> as a fixed-clock provider, this driver can be implemented as a platform driver.
>> Then the crg device must be registered before other clock consumer devices.Accordingly
>> the crg device node must be written above all other clock consumer devices node in dts files.
>> I think it is also a dependence.
>>
>> Can you help me understand why it is better to make this driver a platform driver?
>> Thank you very much!
>>
> arch_initcall(customize_machine)
> -->of_platform_populate
>    -->of_platform_bus_create
>      -->of_amba_device_create
>         -->amba_device_add
>            -->amba_get_enable_pclk
> The call sequence above shows that the clock of the amba device must be registered before
> amba_device_add. The clock of "arm,pl011" uart is registered in the probe function of the
> platform driver "hi3519-crg". So the platform device "hi3519-crg" must be created before
> the amba device "arm,pl011" uart.

It is a problem, but Tomeu had a fix to support deferred probes here.
That was part of the on-demand probing series, but maybe it needs to
be applied separately if we are moving clock drivers to platform
drivers.

Rob
Tomeu Vizoso Jan. 20, 2016, 6:38 a.m. UTC | #10 
On 19 January 2016 at 19:20, Rob Herring <robh+dt@kernel.org> wrote:
> On Fri, Jan 15, 2016 at 1:57 AM, xuejiancheng <xuejiancheng@huawei.com> wrote:
>>
>> On 2016/1/14 21:16, xuejiancheng wrote:
>>> Hi Mike,
>>>
>>> On 2016/1/14 2:57, Michael Turquette wrote:
>>>> Quoting xuejiancheng (2016-01-12 19:03:01)
>>>>> Hi Stephen,
>>>>>    Thank you very much for your reply.
>>>>>
>>>>> On 2016/1/13 6:12, Stephen Boyd wrote:
>>>>>> On 01/08, Jiancheng Xue wrote:
>>>>>>> diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
>>>>>>> index e434854..b6baebf 100644
>>>>>>> --- a/drivers/clk/hisilicon/Kconfig
>>>>>>> +++ b/drivers/clk/hisilicon/Kconfig
>>>>>>> @@ -1,3 +1,10 @@
>>>>>>> +config COMMON_CLK_HI3519
>>>>>>> +    tristate "Clock Driver for Hi3519"
>>>>>>
>>>>>> It looks like this has to be bool. Otherwise it needs to be a
>>>>>> platform driver and the hisilicon APIs need to be exported and
>>>>>> lose their __init markings.
>>>>>>
>>>>> Yes,it's a problem. I will fix it in next version. Thank you.
>>>>
>>>> The best solution would be to make this clock driver a real platform
>>>> driver.
>>>>
>>> Now the work clock of the clocksource timer-sp804 is provided by this driver. So
>>> it need to be registered early by CLK_OF_DECLARE. If the timer clock is treated
>>> as a fixed-clock provider, this driver can be implemented as a platform driver.
>>> Then the crg device must be registered before other clock consumer devices.Accordingly
>>> the crg device node must be written above all other clock consumer devices node in dts files.
>>> I think it is also a dependence.
>>>
>>> Can you help me understand why it is better to make this driver a platform driver?
>>> Thank you very much!
>>>
>> arch_initcall(customize_machine)
>> -->of_platform_populate
>>    -->of_platform_bus_create
>>      -->of_amba_device_create
>>         -->amba_device_add
>>            -->amba_get_enable_pclk
>> The call sequence above shows that the clock of the amba device must be registered before
>> amba_device_add. The clock of "arm,pl011" uart is registered in the probe function of the
>> platform driver "hi3519-crg". So the platform device "hi3519-crg" must be created before
>> the amba device "arm,pl011" uart.
>
> It is a problem, but Tomeu had a fix to support deferred probes here.
> That was part of the on-demand probing series, but maybe it needs to
> be applied separately if we are moving clock drivers to platform
> drivers.

Hi,

Marek Szyprowski has kindly taken those two patches as part of a series of him:

http://lkml.kernel.org/g/1450868368-5650-1-git-send-email-m.szyprowski@samsung.com

I think it would be great if you could test them and report.

Thanks,

Tomeu
Jiancheng Xue Jan. 22, 2016, 8:50 a.m. UTC | #11 
On 2016/1/20 14:38, Tomeu Vizoso wrote:
> On 19 January 2016 at 19:20, Rob Herring <robh+dt@kernel.org> wrote:
>> On Fri, Jan 15, 2016 at 1:57 AM, xuejiancheng <xuejiancheng@huawei.com> wrote:
>>>
>>> On 2016/1/14 21:16, xuejiancheng wrote:
>>>> Hi Mike,
>>>>
>>>> On 2016/1/14 2:57, Michael Turquette wrote:
>>>>> Quoting xuejiancheng (2016-01-12 19:03:01)
>>>>>> Hi Stephen,
>>>>>>    Thank you very much for your reply.
>>>>>>
>>>>>> On 2016/1/13 6:12, Stephen Boyd wrote:
>>>>>>> On 01/08, Jiancheng Xue wrote:
>>>>>>>> diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
>>>>>>>> index e434854..b6baebf 100644
>>>>>>>> --- a/drivers/clk/hisilicon/Kconfig
>>>>>>>> +++ b/drivers/clk/hisilicon/Kconfig
>>>>>>>> @@ -1,3 +1,10 @@
>>>>>>>> +config COMMON_CLK_HI3519
>>>>>>>> +    tristate "Clock Driver for Hi3519"
>>>>>>>
>>>>>>> It looks like this has to be bool. Otherwise it needs to be a
>>>>>>> platform driver and the hisilicon APIs need to be exported and
>>>>>>> lose their __init markings.
>>>>>>>
>>>>>> Yes,it's a problem. I will fix it in next version. Thank you.
>>>>>
>>>>> The best solution would be to make this clock driver a real platform
>>>>> driver.
>>>>>
>>>> Now the work clock of the clocksource timer-sp804 is provided by this driver. So
>>>> it need to be registered early by CLK_OF_DECLARE. If the timer clock is treated
>>>> as a fixed-clock provider, this driver can be implemented as a platform driver.
>>>> Then the crg device must be registered before other clock consumer devices.Accordingly
>>>> the crg device node must be written above all other clock consumer devices node in dts files.
>>>> I think it is also a dependence.
>>>>
>>>> Can you help me understand why it is better to make this driver a platform driver?
>>>> Thank you very much!
>>>>
>>> arch_initcall(customize_machine)
>>> -->of_platform_populate
>>>    -->of_platform_bus_create
>>>      -->of_amba_device_create
>>>         -->amba_device_add
>>>            -->amba_get_enable_pclk
>>> The call sequence above shows that the clock of the amba device must be registered before
>>> amba_device_add. The clock of "arm,pl011" uart is registered in the probe function of the
>>> platform driver "hi3519-crg". So the platform device "hi3519-crg" must be created before
>>> the amba device "arm,pl011" uart.
>>
>> It is a problem, but Tomeu had a fix to support deferred probes here.
>> That was part of the on-demand probing series, but maybe it needs to
>> be applied separately if we are moving clock drivers to platform
>> drivers.
> 
> Hi,
> 
> Marek Szyprowski has kindly taken those two patches as part of a series of him:
> 
> http://lkml.kernel.org/g/1450868368-5650-1-git-send-email-m.szyprowski@samsung.com
> 
> I think it would be great if you could test them and report.
> 
Hi Tomeu,

I have applied the patch "https://lkml.org/lkml/2015/12/23/105" and tested on my hi3519-demb board.
It works even if the apb_pclk is registered later than the amba-pl011 device being registered.

But I think it is a problem if amba_read_periphid() returns -ENOMEM or -ENODEV when apb_pclk is available.
In this condition?amba_match() returns a non zero value which means the driver and device matches
and the amba_probe() will be called, but amba_device->periphid remains as 0. Then amba_lookup() called in
amba_probe() will return a null id pointer.The null pointer will be passed to amba_driver->probe() and
this may cause a segment fault.

Regards,

Jiancheng

> Thanks,
> 
> Tomeu
> 
> .
>
Tomeu Vizoso Jan. 22, 2016, 9:55 a.m. UTC | #12 
On 22 January 2016 at 09:50, xuejiancheng <xuejiancheng@huawei.com> wrote:
> On 2016/1/20 14:38, Tomeu Vizoso wrote:
>> On 19 January 2016 at 19:20, Rob Herring <robh+dt@kernel.org> wrote:
>>> On Fri, Jan 15, 2016 at 1:57 AM, xuejiancheng <xuejiancheng@huawei.com> wrote:
>>>>
>>>> On 2016/1/14 21:16, xuejiancheng wrote:
>>>>> Hi Mike,
>>>>>
>>>>> On 2016/1/14 2:57, Michael Turquette wrote:
>>>>>> Quoting xuejiancheng (2016-01-12 19:03:01)
>>>>>>> Hi Stephen,
>>>>>>>    Thank you very much for your reply.
>>>>>>>
>>>>>>> On 2016/1/13 6:12, Stephen Boyd wrote:
>>>>>>>> On 01/08, Jiancheng Xue wrote:
>>>>>>>>> diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
>>>>>>>>> index e434854..b6baebf 100644
>>>>>>>>> --- a/drivers/clk/hisilicon/Kconfig
>>>>>>>>> +++ b/drivers/clk/hisilicon/Kconfig
>>>>>>>>> @@ -1,3 +1,10 @@
>>>>>>>>> +config COMMON_CLK_HI3519
>>>>>>>>> +    tristate "Clock Driver for Hi3519"
>>>>>>>>
>>>>>>>> It looks like this has to be bool. Otherwise it needs to be a
>>>>>>>> platform driver and the hisilicon APIs need to be exported and
>>>>>>>> lose their __init markings.
>>>>>>>>
>>>>>>> Yes,it's a problem. I will fix it in next version. Thank you.
>>>>>>
>>>>>> The best solution would be to make this clock driver a real platform
>>>>>> driver.
>>>>>>
>>>>> Now the work clock of the clocksource timer-sp804 is provided by this driver. So
>>>>> it need to be registered early by CLK_OF_DECLARE. If the timer clock is treated
>>>>> as a fixed-clock provider, this driver can be implemented as a platform driver.
>>>>> Then the crg device must be registered before other clock consumer devices.Accordingly
>>>>> the crg device node must be written above all other clock consumer devices node in dts files.
>>>>> I think it is also a dependence.
>>>>>
>>>>> Can you help me understand why it is better to make this driver a platform driver?
>>>>> Thank you very much!
>>>>>
>>>> arch_initcall(customize_machine)
>>>> -->of_platform_populate
>>>>    -->of_platform_bus_create
>>>>      -->of_amba_device_create
>>>>         -->amba_device_add
>>>>            -->amba_get_enable_pclk
>>>> The call sequence above shows that the clock of the amba device must be registered before
>>>> amba_device_add. The clock of "arm,pl011" uart is registered in the probe function of the
>>>> platform driver "hi3519-crg". So the platform device "hi3519-crg" must be created before
>>>> the amba device "arm,pl011" uart.
>>>
>>> It is a problem, but Tomeu had a fix to support deferred probes here.
>>> That was part of the on-demand probing series, but maybe it needs to
>>> be applied separately if we are moving clock drivers to platform
>>> drivers.
>>
>> Hi,
>>
>> Marek Szyprowski has kindly taken those two patches as part of a series of him:
>>
>> http://lkml.kernel.org/g/1450868368-5650-1-git-send-email-m.szyprowski@samsung.com
>>
>> I think it would be great if you could test them and report.
>>
> Hi Tomeu,
>
> I have applied the patch "https://lkml.org/lkml/2015/12/23/105" and tested on my hi3519-demb board.
> It works even if the apb_pclk is registered later than the amba-pl011 device being registered.
>
> But I think it is a problem if amba_read_periphid() returns -ENOMEM or -ENODEV when apb_pclk is available.
> In this condition?amba_match() returns a non zero value which means the driver and device matches
> and the amba_probe() will be called, but amba_device->periphid remains as 0. Then amba_lookup() called in
> amba_probe() will return a null id pointer.The null pointer will be passed to amba_driver->probe() and
> this may cause a segment fault.

But, have you applied the other patches in the series? There's one
that should handle the other error codes.

In any case, any feedback you have on that series should be given in
the other thread.

Regards,

Tomeu

> Regards,
>
> Jiancheng
>
>> Thanks,
>>
>> Tomeu
>>
>> .
>>
>
diff mbox

Patch

diff --git a/Documentation/devicetree/bindings/clock/hi3519-crg.txt b/Documentation/devicetree/bindings/clock/hi3519-crg.txt
new file mode 100644
index 0000000..2d23950
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/hi3519-crg.txt
@@ -0,0 +1,46 @@ 
+* Hisilicon Hi3519 Clock and Reset Generator(CRG)
+
+The Hi3519 CRG module provides clock and reset signals to various
+controllers within the SoC.
+
+This binding uses the following bindings:
+    Documentation/devicetree/bindings/clock/clock-bindings.txt
+    Documentation/devicetree/bindings/reset/reset.txt
+
+Required Properties:
+
+- compatible: should be one of the following.
+  - "hisilicon,hi3519-crg" - controller compatible with Hi3519 SoC.
+
+- reg: physical base address of the controller and length of memory mapped
+  region.
+
+- #clock-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes use this identifier
+to specify the clock which they consume.
+
+All these identifier could be found in <dt-bindings/clock/hi3519-clock.h>.
+
+- #reset-cells: should be 2.
+
+A reset signal can be controlled by writing a bit register in the CRG module.
+The reset specifier consists of two cells. The first cell represents the
+register offset relative to the base address. The second cell represents the
+bit index in the register.
+
+Example: CRG nodes
+CRG: clock-reset-controller@12010000 {
+	compatible = "hisilicon,hi3519-crg";
+        reg = <0x12010000 0x10000>;
+        #clock-cells = <1>;
+        #reset-cells = <2>;
+};
+
+Example: consumer nodes
+i2c0: i2c@12110000 {
+	compatible = "hisilicon,hi3519-i2c";
+        reg = <0x12110000 0x1000>;
+        clocks = <&CRG HI3519_I2C0_RST>;*/
+        resets = <&CRG 0xe4 0>;
+};
diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
index e434854..b6baebf 100644
--- a/drivers/clk/hisilicon/Kconfig
+++ b/drivers/clk/hisilicon/Kconfig
@@ -1,3 +1,10 @@ 
+config COMMON_CLK_HI3519
+	tristate "Clock Driver for Hi3519"
+	depends on ARCH_HISI
+	default y
+	help
+	  Build the clock driver for hi3519.
+
 config COMMON_CLK_HI6220
 	bool "Hi6220 Clock Driver"
 	depends on ARCH_HISI || COMPILE_TEST
diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
index 74dba31..3f57b09 100644
--- a/drivers/clk/hisilicon/Makefile
+++ b/drivers/clk/hisilicon/Makefile
@@ -4,8 +4,10 @@ 
 
 obj-y	+= clk.o clkgate-separated.o clkdivider-hi6220.o
 
+obj-$(CONFIG_RESET_CONTROLLER)	+= reset.o
 obj-$(CONFIG_ARCH_HI3xxx)	+= clk-hi3620.o
 obj-$(CONFIG_ARCH_HIP04)	+= clk-hip04.o
 obj-$(CONFIG_ARCH_HIX5HD2)	+= clk-hix5hd2.o
 obj-$(CONFIG_COMMON_CLK_HI6220)	+= clk-hi6220.o
 obj-$(CONFIG_STUB_CLK_HI6220)	+= clk-hi6220-stub.o
+obj-$(CONFIG_COMMON_CLK_HI3519)	+= clk-hi3519.o
diff --git a/drivers/clk/hisilicon/clk-hi3519.c b/drivers/clk/hisilicon/clk-hi3519.c
new file mode 100644
index 0000000..72d3a7b0
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hi3519.c
@@ -0,0 +1,105 @@ 
+/*
+ * Hi3519 Clock Driver
+ *
+ * Copyright (c) 2015-2016 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <dt-bindings/clock/hi3519-clock.h>
+#include <linux/delay.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+#include "clk.h"
+#include "reset.h"
+
+#define HI3519_FIXED_24M	(HI3519_EXT_CLKS + 1)
+#define HI3519_FIXED_50M	(HI3519_EXT_CLKS + 2)
+#define HI3519_FIXED_75M	(HI3519_EXT_CLKS + 3)
+#define HI3519_FIXED_125M	(HI3519_EXT_CLKS + 4)
+#define HI3519_FIXED_150M	(HI3519_EXT_CLKS + 5)
+#define HI3519_FIXED_200M	(HI3519_EXT_CLKS + 6)
+#define HI3519_FIXED_250M	(HI3519_EXT_CLKS + 7)
+#define HI3519_FIXED_300M	(HI3519_EXT_CLKS + 8)
+#define HI3519_FIXED_400M	(HI3519_EXT_CLKS + 9)
+#define HI3519_FMC_MUX		(HI3519_EXT_CLKS + 10)
+
+#define HI3519_NR_CLKS	128
+
+static struct hisi_fixed_rate_clock hi3519_fixed_rate_clks[] __initdata = {
+	{ HI3519_FIXED_3M, "3m", NULL, CLK_IS_ROOT, 3000000, },
+	{ HI3519_FIXED_24M, "24m", NULL, CLK_IS_ROOT, 24000000, },
+	{ HI3519_FIXED_50M, "50m", NULL, CLK_IS_ROOT, 50000000, },
+	{ HI3519_FIXED_75M, "75m", NULL, CLK_IS_ROOT, 75000000, },
+	{ HI3519_FIXED_125M, "125m", NULL, CLK_IS_ROOT, 125000000, },
+	{ HI3519_FIXED_150M, "150m", NULL, CLK_IS_ROOT, 150000000, },
+	{ HI3519_FIXED_200M, "200m", NULL, CLK_IS_ROOT, 200000000, },
+	{ HI3519_FIXED_250M, "250m", NULL, CLK_IS_ROOT, 250000000, },
+	{ HI3519_FIXED_300M, "300m", NULL, CLK_IS_ROOT, 300000000, },
+	{ HI3519_FIXED_400M, "400m", NULL, CLK_IS_ROOT, 400000000, },
+};
+
+static const char *fmc_mux_p[] __initconst = {
+		"24m", "75m", "125m", "150m", "200m", "250m", "300m", "400m", };
+static u32 fmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6, 7};
+
+static struct hisi_mux_clock hi3519_mux_clks[] __initdata = {
+	{ HI3519_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
+		CLK_SET_RATE_PARENT, 0xc0, 2, 3, 0, fmc_mux_table, },
+};
+
+static struct hisi_gate_clock hi3519_gate_clks[] __initdata = {
+	/* fmc */
+	{ HI3519_FMC_CLK, "clk_fmc", "fmc_mux",
+		CLK_SET_RATE_PARENT, 0xc0, 1, 0, },
+	/* uart */
+	{ HI3519_UART0_CLK, "clk_uart0", "24m",
+		CLK_SET_RATE_PARENT, 0xe4, 20, 0, },
+	{ HI3519_UART1_CLK, "clk_uart1", "24m",
+		CLK_SET_RATE_PARENT, 0xe4, 21, 0, },
+	{ HI3519_UART2_CLK, "clk_uart2", "24m",
+		CLK_SET_RATE_PARENT, 0xe4, 22, 0, },
+	{ HI3519_UART3_CLK, "clk_uart3", "24m",
+		CLK_SET_RATE_PARENT, 0xe4, 23, 0, },
+	{ HI3519_UART4_CLK, "clk_uart4", "24m",
+		CLK_SET_RATE_PARENT, 0xe4, 24, 0, },
+	{ HI3519_SPI0_CLK, "clk_spi0", "50m",
+		CLK_SET_RATE_PARENT, 0xe4, 16, 0, },
+	{ HI3519_SPI1_CLK, "clk_spi1", "50m",
+		CLK_SET_RATE_PARENT, 0xe4, 17, 0, },
+	{ HI3519_SPI2_CLK, "clk_spi2", "50m",
+		CLK_SET_RATE_PARENT, 0xe4, 18, 0, },
+};
+
+static void __init hi3519_clk_init(struct device_node *np)
+{
+	struct hisi_clock_data *clk_data;
+
+
+	clk_data = hisi_clk_init(np, HI3519_NR_CLKS);
+	if (!clk_data)
+		return;
+
+	hisi_clk_register_fixed_rate(hi3519_fixed_rate_clks,
+				     ARRAY_SIZE(hi3519_fixed_rate_clks),
+				     clk_data);
+	hisi_clk_register_mux(hi3519_mux_clks, ARRAY_SIZE(hi3519_mux_clks),
+					clk_data);
+	hisi_clk_register_gate(hi3519_gate_clks,
+			ARRAY_SIZE(hi3519_gate_clks), clk_data);
+
+	hisi_reset_init(np);
+}
+
+CLK_OF_DECLARE(hi3519_clk, "hisilicon,hi3519-crg", hi3519_clk_init);
diff --git a/drivers/clk/hisilicon/reset.c b/drivers/clk/hisilicon/reset.c
new file mode 100644
index 0000000..f11561c
--- /dev/null
+++ b/drivers/clk/hisilicon/reset.c
@@ -0,0 +1,129 @@ 
+/*
+ * Hisilicon Reset Controller Driver
+ *
+ * Copyright (c) 2015-2016 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+
+#define	HISI_RESET_BIT_MASK	0x1f
+#define	HISI_RESET_OFFSET_SHIFT	8
+#define	HISI_RESET_OFFSET_MASK	0xffff00
+
+struct hisi_reset_controller {
+	spinlock_t	lock;
+	void __iomem	*membase;
+	struct reset_controller_dev	rcdev;
+};
+
+
+#define to_hisi_reset_controller(rcdev)  \
+	container_of(rcdev, struct hisi_reset_controller, rcdev)
+
+static int hisi_reset_of_xlate(struct reset_controller_dev *rcdev,
+			const struct of_phandle_args *reset_spec)
+{
+	u32 offset;
+	u8 bit;
+
+	if (WARN_ON(reset_spec->args_count != rcdev->of_reset_n_cells))
+		return -EINVAL;
+
+	offset = (reset_spec->args[0] << HISI_RESET_OFFSET_SHIFT)
+		& HISI_RESET_OFFSET_MASK;
+	bit = reset_spec->args[1] & HISI_RESET_BIT_MASK;
+	return (offset | bit);
+}
+
+static int hisi_reset_assert(struct reset_controller_dev *rcdev,
+			      unsigned long id)
+{
+	struct hisi_reset_controller *rstc = to_hisi_reset_controller(rcdev);
+	unsigned long flags;
+	u32 offset, reg;
+	u8 bit;
+
+	offset = (id & HISI_RESET_OFFSET_MASK) >> HISI_RESET_OFFSET_SHIFT;
+	bit = id & HISI_RESET_BIT_MASK;
+
+	spin_lock_irqsave(&rstc->lock, flags);
+
+	reg = readl(rstc->membase + offset);
+	writel(reg | BIT(bit), rstc->membase + offset);
+
+	spin_unlock_irqrestore(&rstc->lock, flags);
+
+	return 0;
+}
+
+static int hisi_reset_deassert(struct reset_controller_dev *rcdev,
+				unsigned long id)
+{
+	struct hisi_reset_controller *rstc = to_hisi_reset_controller(rcdev);
+	unsigned long flags;
+	u32 offset, reg;
+	u8 bit;
+
+	offset = (id & HISI_RESET_OFFSET_MASK) >> HISI_RESET_OFFSET_SHIFT;
+	bit = id & HISI_RESET_BIT_MASK;
+
+	spin_lock_irqsave(&rstc->lock, flags);
+
+	reg = readl(rstc->membase + offset);
+	writel(reg & ~BIT(bit), rstc->membase + offset);
+
+	spin_unlock_irqrestore(&rstc->lock, flags);
+
+	return 0;
+}
+
+static struct reset_control_ops hisi_reset_ops = {
+	.assert		= hisi_reset_assert,
+	.deassert	= hisi_reset_deassert,
+};
+
+int __init hisi_reset_init(struct device_node *np)
+{
+	struct hisi_reset_controller *rstc;
+
+	rstc = kzalloc(sizeof(*rstc), GFP_KERNEL);
+	if (!rstc)
+		return -ENOMEM;
+
+	rstc->membase = of_iomap(np, 0);
+	if (!rstc->membase)
+		return -EINVAL;
+
+	spin_lock_init(&rstc->lock);
+
+	rstc->rcdev.owner = THIS_MODULE;
+	rstc->rcdev.ops = &hisi_reset_ops;
+	rstc->rcdev.of_node = np;
+	rstc->rcdev.of_reset_n_cells = 2;
+	rstc->rcdev.of_xlate = hisi_reset_of_xlate;
+
+	return reset_controller_register(&rstc->rcdev);
+}
diff --git a/drivers/clk/hisilicon/reset.h b/drivers/clk/hisilicon/reset.h
new file mode 100644
index 0000000..37856089
--- /dev/null
+++ b/drivers/clk/hisilicon/reset.h
@@ -0,0 +1,32 @@ 
+/*
+ * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef	__HISI_RESET_H
+#define	__HISI_RESET_H
+
+#include <linux/of.h>
+
+#ifdef CONFIG_RESET_CONTROLLER
+int __init hisi_reset_init(struct device_node *np);
+#else
+static inline int __init hisi_reset_init(struct device_node *np)
+{
+	return 0;
+}
+#endif
+
+#endif	/* __HISI_RESET_H */
diff --git a/include/dt-bindings/clock/hi3519-clock.h b/include/dt-bindings/clock/hi3519-clock.h
new file mode 100644
index 0000000..1e4a3c1
--- /dev/null
+++ b/include/dt-bindings/clock/hi3519-clock.h
@@ -0,0 +1,43 @@ 
+/*
+ * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __DTS_HI3519_CLOCK_H
+#define __DTS_HI3519_CLOCK_H
+
+#define HI3519_FIXED_3M			1
+#define HI3519_FMC_CLK			2
+#define HI3519_USB2_BUS_CLK		3
+#define HI3519_USB2_PORT_CLK		4
+#define HI3519_USB3_CLK			5
+#define HI3519_ETH_PHY_CLK		6
+#define HI3519_ETH_MAC_CLK		7
+#define HI3519_ETH_MACIF_CLK		8
+#define HI3519_PWM_CLK			9
+#define HI3519_DMA_CLK			10
+#define HI3519_SPI0_CLK			11
+#define HI3519_SPI1_CLK			12
+#define HI3519_SPI2_CLK			13
+#define HI3519_IR_CLK			14
+#define HI3519_UART0_CLK		15
+#define HI3519_UART1_CLK		16
+#define HI3519_UART2_CLK		17
+#define HI3519_UART3_CLK		18
+#define HI3519_UART4_CLK		19
+
+#define HI3519_EXT_CLKS			19
+
+#endif	/* __DTS_HI3519_CLOCK_H */