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[1/3] ARM: dts: sun8i: Enable timer node for A83T

Message ID 1452961497-10804-2-git-send-email-wens@csie.org (mailing list archive)
State New, archived
Headers show

Commit Message

Chen-Yu Tsai Jan. 16, 2016, 4:24 p.m. UTC 
From: Vishnu Patekar <vishnupatekar0510@gmail.com>

A83T timer is compatible with that of earlier SOCs.
Just add timer node to enable and re-use it.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

Comments

Maxime Ripard Jan. 17, 2016, 12:22 p.m. UTC | #1 
Hi,

On Sun, Jan 17, 2016 at 12:24:55AM +0800, Chen-Yu Tsai wrote:
> From: Vishnu Patekar <vishnupatekar0510@gmail.com>
> 
> A83T timer is compatible with that of earlier SOCs.
> Just add timer node to enable and re-use it.
> 
> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Applied, thanks!

Maxime
diff mbox

Patch

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index bad5df7175b4..08df5598df9c 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -174,6 +174,14 @@ 
 			};
 		};
 
+		timer@01c20c00 {
+			compatible = "allwinner,sun4i-a10-timer";
+			reg = <0x01c20c00 0xa0>;
+			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&osc24M>;
+		};
+
 		uart0: serial@01c28000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x01c28000 0x400>;