[v3] arm: irq: l2c: do not print error in case of missing l2c from dtb

Commit Message

Andi Shyti Jan. 12, 2016, 10:11 a.m. UTC

In some architectures the L2 cache controller is integrated in the
processor's block itself and it doesn't use any external cache
controller. This means that an entry in the board's dtb related
to the l2c is not necessary.

Distinguish between error codes and do not print anything in case
l2x0_of_init() doesn't find any L2C DTB entry and returns -ENODEV.

This patch mutes the following error message:

   L2C: failed to init: -19

on boards like odroid-xu4, cortex A7/A15, which don't have
external cache controller.

Signed-off-by: Andi Shyti <[e-mail]>
Reported-by: Krzysztof Kozlowski <[e-mail]>
Reviewed-by: Krzysztof Kozlowski <[e-mail]>
---
Hi,

here is a second version. An alternative would be to print with
pr_dbg, but then it's a matter of taste.

V1, and V2 print a message in case the l2c dtb entry is not found
(the V2 has a better print rephrase suggested by Joe)

V3 ignores the case of -enodev for l2c and doesn't print anything

Thanks,
Andi

 arch/arm/kernel/irq.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Krzysztof Kozlowski Jan. 12, 2016, 11:55 p.m. UTC | #1

On 12.01.2016 19:11, Andi Shyti wrote:
> In some architectures the L2 cache controller is integrated in the
> processor's block itself and it doesn't use any external cache
> controller. This means that an entry in the board's dtb related
> to the l2c is not necessary.
> 
> Distinguish between error codes and do not print anything in case
> l2x0_of_init() doesn't find any L2C DTB entry and returns -ENODEV.
> 
> This patch mutes the following error message:
> 
>    L2C: failed to init: -19
> 
> on boards like odroid-xu4, cortex A7/A15, which don't have
> external cache controller.
> 
> Signed-off-by: Andi Shyti <[e-mail]>
> Reported-by: Krzysztof Kozlowski <[e-mail]>
> Reviewed-by: Krzysztof Kozlowski <[e-mail]>
> ---
> Hi,
> 
> here is a second version. An alternative would be to print with
> pr_dbg, but then it's a matter of taste.
> 
> V1, and V2 print a message in case the l2c dtb entry is not found
> (the V2 has a better print rephrase suggested by Joe)
> 
> V3 ignores the case of -enodev for l2c and doesn't print anything
> 
> Thanks,
> Andi

Looks good to me, as v2 did. Works fine:
Tested-by: Krzysztof Kozlowski <[e-mail]>

BR,
KRzysztof

Javier Martinez Canillas Jan. 20, 2016, 6:02 p.m. UTC | #2

Hello Andi,

On Tue, Jan 12, 2016 at 7:11 AM, Andi Shyti <[e-mail]> wrote:
> In some architectures the L2 cache controller is integrated in the
> processor's block itself and it doesn't use any external cache
> controller. This means that an entry in the board's dtb related
> to the l2c is not necessary.
>
> Distinguish between error codes and do not print anything in case
> l2x0_of_init() doesn't find any L2C DTB entry and returns -ENODEV.
>
> This patch mutes the following error message:
>
>    L2C: failed to init: -19
>
> on boards like odroid-xu4, cortex A7/A15, which don't have
> external cache controller.
>

The patch also looks good to me and makes the error message to go away
in my Exynos5800 Peach Pi.

Reviewed-by: Javier Martinez Canillas <[e-mail]>
Tested-by: Javier Martinez Canillas <[e-mail]>

Best regards,
Javier

Patch

diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index 1d45320..ece04a4 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -95,7 +95,7 @@  void __init init_IRQ(void)
 			outer_cache.write_sec = machine_desc->l2c_write_sec;
 		ret = l2x0_of_init(machine_desc->l2c_aux_val,
 				   machine_desc->l2c_aux_mask);
-		if (ret)
+		if (ret && ret != -ENODEV)
 			pr_err("L2C: failed to init: %d\n", ret);
 	}