[1/2] drm/i915: add Ivybridge clock gating init function

Commit Message

Jesse Barnes May 11, 2011, 4:52 p.m. UTC

Some of the bits have changed, including one we were setting that enables
a VGA test mode, preventing pipe B from working at all.  So add a new
IVB specific function with the right bits.

Signed-off-by: Jesse Barnes <[e-mail]>
---
 drivers/gpu/drm/i915/i915_reg.h      |    1 +
 drivers/gpu/drm/i915/intel_display.c |   29 ++++++++++++++++++++++++++++-
 2 files changed, 29 insertions(+), 1 deletions(-)

Comments

Adam Jackson May 11, 2011, 5:20 p.m. UTC | #1

On Wed, 2011-05-11 at 09:52 -0700, Jesse Barnes wrote:

> +	/*
> +	 * On Ibex Peak and Cougar Point, we need to disable clock
> +	 * gating for the panel power sequencer or it will fail to
> +	 * start up when no ports are active.
> +	 */

Nitpick: Probably either this comment (and its mate in
gen6_init_clock_gating) should just refer to PCH generically if this is
going to keep being true, or this instance of it should read Panther
Point instead of ibx/cpt.  Assuming wikipedia isn't lying to me about
chipset names, anyway.

- ajax

Jesse Barnes May 11, 2011, 5:26 p.m. UTC | #2

On Wed, 11 May 2011 13:20:55 -0400
Adam Jackson <[e-mail]> wrote:

> On Wed, 2011-05-11 at 09:52 -0700, Jesse Barnes wrote:
> 
> > +	/*
> > +	 * On Ibex Peak and Cougar Point, we need to disable clock
> > +	 * gating for the panel power sequencer or it will fail to
> > +	 * start up when no ports are active.
> > +	 */
> 
> Nitpick: Probably either this comment (and its mate in
> gen6_init_clock_gating) should just refer to PCH generically if this is
> going to keep being true, or this instance of it should read Panther
> Point instead of ibx/cpt.  Assuming wikipedia isn't lying to me about
> chipset names, anyway.

I hope it's not true for PPT (my current IVB system uses CPT), but it
gets split out in the next patch anyway...

Adam Jackson May 11, 2011, 7:24 p.m. UTC | #3

On Wed, 2011-05-11 at 10:26 -0700, Jesse Barnes wrote:
> On Wed, 11 May 2011 13:20:55 -0400
> Adam Jackson <[e-mail]> wrote:
> > Nitpick: Probably either this comment (and its mate in
> > gen6_init_clock_gating) should just refer to PCH generically if this is
> > going to keep being true, or this instance of it should read Panther
> > Point instead of ibx/cpt.  Assuming wikipedia isn't lying to me about
> > chipset names, anyway.
> 
> I hope it's not true for PPT (my current IVB system uses CPT), but it
> gets split out in the next patch anyway...

Fair. Wasn't sure if there were ivb/cpt machines. Objection cheerfully
withdrawn!

- ajax

Patch

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9cb6353..9de1a56 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2825,6 +2825,7 @@ 
 #define  ILK_eDP_A_DISABLE		(1<<24)
 #define  ILK_DESKTOP			(1<<23)
 #define ILK_DSPCLK_GATE		0x42020
+#define  IVB_VRHUNIT_CLK_GATE	(1<<28)
 #define  ILK_DPARB_CLK_GATE	(1<<5)
 #define  ILK_DPFD_CLK_GATE	(1<<7)
 
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0e746ba..eaf6f87 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7208,6 +7208,33 @@  static void gen6_init_clock_gating(struct drm_device *dev)
 			   DISPPLANE_TRICKLE_FEED_DISABLE);
 }
 
+static void ivybridge_init_clock_gating(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int pipe;
+	uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
+
+	I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
+
+	/*
+	 * On Ibex Peak and Cougar Point, we need to disable clock
+	 * gating for the panel power sequencer or it will fail to
+	 * start up when no ports are active.
+	 */
+	I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
+
+	I915_WRITE(WM3_LP_ILK, 0);
+	I915_WRITE(WM2_LP_ILK, 0);
+	I915_WRITE(WM1_LP_ILK, 0);
+
+	I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
+
+	for_each_pipe(pipe)
+		I915_WRITE(DSPCNTR(pipe),
+			   I915_READ(DSPCNTR(pipe)) |
+			   DISPPLANE_TRICKLE_FEED_DISABLE);
+}
+
 static void g4x_init_clock_gating(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -7475,7 +7502,7 @@  static void intel_init_display(struct drm_device *dev)
 					      "Disable CxSR\n");
 				dev_priv->display.update_wm = NULL;
 			}
-			dev_priv->display.init_clock_gating = gen6_init_clock_gating;
+			dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
 
 		} else
 			dev_priv->display.update_wm = NULL;