Message ID | 1453808801-12510-2-git-send-email-wsa@the-dreams.de (mailing list archive) |
---|---|
State | RFC |
Delegated to: | Geert Uytterhoeven |
Headers | show |
On 26.01.2016 12:46, Wolfram Sang wrote: > From: Wolfram Sang <wsa+renesas@sang-engineering.com> > > RCar implementations of TMIO/SDHI have their own set of additions. > FAST_CLK_CHG is just one of them and I see a few others being added > soon. Instead of adding a bunch of flags which all RCars share anyhow, > add a global one and add new flags only for real differences. > > Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> > --- > drivers/mmc/host/sh_mobile_sdhi.c | 4 ++-- > drivers/mmc/host/tmio_mmc_pio.c | 6 +++--- > include/linux/mfd/tmio.h | 4 ++-- > 3 files changed, 7 insertions(+), 7 deletions(-) > > diff --git a/drivers/mmc/host/sh_mobile_sdhi.c b/drivers/mmc/host/sh_mobile_sdhi.c > index f7eff5f53e0013..12419acb8ac9f5 100644 > --- a/drivers/mmc/host/sh_mobile_sdhi.c > +++ b/drivers/mmc/host/sh_mobile_sdhi.c > @@ -62,7 +62,7 @@ static const struct sh_mobile_sdhi_of_data of_rcar_gen1_compatible = { > > static const struct sh_mobile_sdhi_of_data of_rcar_gen2_compatible = { > .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE | > - TMIO_MMC_CLK_ACTUAL | TMIO_MMC_FAST_CLK_CHG, > + TMIO_MMC_CLK_ACTUAL | TMIO_MMC_IS_RCAR, I understood http://www.spinics.net/lists/linux-renesas-soc/msg00167.html that we shall use CBSY only on Gen3, not on Gen2? On Gen2 we should still use SCLKDIVEN? Best regards Dirk > .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ, > .dma_buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES, > .dma_rx_offset = 0x2000, > @@ -70,7 +70,7 @@ static const struct sh_mobile_sdhi_of_data of_rcar_gen2_compatible = { > > static const struct sh_mobile_sdhi_of_data of_rcar_gen3_compatible = { > .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE | > - TMIO_MMC_CLK_ACTUAL | TMIO_MMC_FAST_CLK_CHG, > + TMIO_MMC_CLK_ACTUAL | TMIO_MMC_IS_RCAR, > .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_WAIT_WHILE_BUSY, > .bus_shift = 2, > }; > diff --git a/drivers/mmc/host/tmio_mmc_pio.c b/drivers/mmc/host/tmio_mmc_pio.c > index 03f6e74c190691..a564517f25d90a 100644 > --- a/drivers/mmc/host/tmio_mmc_pio.c > +++ b/drivers/mmc/host/tmio_mmc_pio.c > @@ -177,7 +177,7 @@ static void tmio_mmc_set_clock(struct tmio_mmc_host *host, > sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & > sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); > sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK); > - if (!(host->pdata->flags & TMIO_MMC_FAST_CLK_CHG)) > + if (!(host->pdata->flags & TMIO_MMC_IS_RCAR)) > msleep(10); > } > > @@ -190,14 +190,14 @@ static void tmio_mmc_clk_stop(struct tmio_mmc_host *host) > > sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & > sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); > - msleep(host->pdata->flags & TMIO_MMC_FAST_CLK_CHG ? 5 : 10); > + msleep(host->pdata->flags & TMIO_MMC_IS_RCAR ? 5 : 10); > } > > static void tmio_mmc_clk_start(struct tmio_mmc_host *host) > { > sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | > sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); > - msleep(host->pdata->flags & TMIO_MMC_FAST_CLK_CHG ? 1 : 10); > + msleep(host->pdata->flags & TMIO_MMC_IS_RCAR ? 1 : 10); > > if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG) { > sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0100); > diff --git a/include/linux/mfd/tmio.h b/include/linux/mfd/tmio.h > index 05d58ee5e6a78f..3d5cc6e0b40e32 100644 > --- a/include/linux/mfd/tmio.h > +++ b/include/linux/mfd/tmio.h > @@ -66,8 +66,8 @@ > */ > #define TMIO_MMC_SDIO_IRQ (1 << 2) > > -/* Some controllers don't need to wait 10ms for clock changes */ > -#define TMIO_MMC_FAST_CLK_CHG (1 << 3) > +/* Controller is on Renesas RCar SoC having special features */ > +#define TMIO_MMC_IS_RCAR (1 << 3) > > /* > * Some controllers require waiting for the SD bus to become >
> that we shall use CBSY only on Gen3, not on Gen2? On Gen2 we should still > use SCLKDIVEN? The datasheets I have also mention CBUSY for Gen2, so it is not new on Gen3 (and not using it seems to work there nonetheless; which adds to my impression this is a micro-optimization ;)). I think Shimoda-san refers to SoCs older than RCar, like real SuperH (non-ARM) chips, for example.
diff --git a/drivers/mmc/host/sh_mobile_sdhi.c b/drivers/mmc/host/sh_mobile_sdhi.c index f7eff5f53e0013..12419acb8ac9f5 100644 --- a/drivers/mmc/host/sh_mobile_sdhi.c +++ b/drivers/mmc/host/sh_mobile_sdhi.c @@ -62,7 +62,7 @@ static const struct sh_mobile_sdhi_of_data of_rcar_gen1_compatible = { static const struct sh_mobile_sdhi_of_data of_rcar_gen2_compatible = { .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE | - TMIO_MMC_CLK_ACTUAL | TMIO_MMC_FAST_CLK_CHG, + TMIO_MMC_CLK_ACTUAL | TMIO_MMC_IS_RCAR, .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ, .dma_buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES, .dma_rx_offset = 0x2000, @@ -70,7 +70,7 @@ static const struct sh_mobile_sdhi_of_data of_rcar_gen2_compatible = { static const struct sh_mobile_sdhi_of_data of_rcar_gen3_compatible = { .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE | - TMIO_MMC_CLK_ACTUAL | TMIO_MMC_FAST_CLK_CHG, + TMIO_MMC_CLK_ACTUAL | TMIO_MMC_IS_RCAR, .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_WAIT_WHILE_BUSY, .bus_shift = 2, }; diff --git a/drivers/mmc/host/tmio_mmc_pio.c b/drivers/mmc/host/tmio_mmc_pio.c index 03f6e74c190691..a564517f25d90a 100644 --- a/drivers/mmc/host/tmio_mmc_pio.c +++ b/drivers/mmc/host/tmio_mmc_pio.c @@ -177,7 +177,7 @@ static void tmio_mmc_set_clock(struct tmio_mmc_host *host, sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK); - if (!(host->pdata->flags & TMIO_MMC_FAST_CLK_CHG)) + if (!(host->pdata->flags & TMIO_MMC_IS_RCAR)) msleep(10); } @@ -190,14 +190,14 @@ static void tmio_mmc_clk_stop(struct tmio_mmc_host *host) sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); - msleep(host->pdata->flags & TMIO_MMC_FAST_CLK_CHG ? 5 : 10); + msleep(host->pdata->flags & TMIO_MMC_IS_RCAR ? 5 : 10); } static void tmio_mmc_clk_start(struct tmio_mmc_host *host) { sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); - msleep(host->pdata->flags & TMIO_MMC_FAST_CLK_CHG ? 1 : 10); + msleep(host->pdata->flags & TMIO_MMC_IS_RCAR ? 1 : 10); if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG) { sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0100); diff --git a/include/linux/mfd/tmio.h b/include/linux/mfd/tmio.h index 05d58ee5e6a78f..3d5cc6e0b40e32 100644 --- a/include/linux/mfd/tmio.h +++ b/include/linux/mfd/tmio.h @@ -66,8 +66,8 @@ */ #define TMIO_MMC_SDIO_IRQ (1 << 2) -/* Some controllers don't need to wait 10ms for clock changes */ -#define TMIO_MMC_FAST_CLK_CHG (1 << 3) +/* Controller is on Renesas RCar SoC having special features */ +#define TMIO_MMC_IS_RCAR (1 << 3) /* * Some controllers require waiting for the SD bus to become