| Message ID | 1453300280-10661-1-git-send-email-patrik.jakobsson@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, Jan 20, 2016 at 03:31:20PM +0100, Patrik Jakobsson wrote: > On SKL and KBL we can have pipe A/B/C disabled by fuse settings. The > pipes must be fused in descending order (e.g. C, B+C, A+B+C). We simply > decrease info->num_pipes if we find a valid fused out config. > > v2: Don't store the pipe disabled mask in device info (Damien) > > v3: Don't check FUSE_STRAP register for pipe c disabled > > Cc: Damien Lespiau <damien.lespiau@intel.com> > Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> (listing the valid cases would have made things simpler?)
On Thu, 28 Jan 2016, Damien Lespiau <damien.lespiau@intel.com> wrote: > On Wed, Jan 20, 2016 at 03:31:20PM +0100, Patrik Jakobsson wrote: >> On SKL and KBL we can have pipe A/B/C disabled by fuse settings. The >> pipes must be fused in descending order (e.g. C, B+C, A+B+C). We simply >> decrease info->num_pipes if we find a valid fused out config. >> >> v2: Don't store the pipe disabled mask in device info (Damien) >> >> v3: Don't check FUSE_STRAP register for pipe c disabled >> >> Cc: Damien Lespiau <damien.lespiau@intel.com> >> Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com> > > Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Pushed to drm-intel-next-queued, thanks for the patch and review. BR, Jani. > > (listing the valid cases would have made things simpler?)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 44a896c..daaa67f 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -814,6 +814,37 @@ static void intel_device_info_runtime_init(struct drm_device *dev) DRM_INFO("Display fused off, disabling\n"); info->num_pipes = 0; } + } else if (info->num_pipes > 0 && INTEL_INFO(dev)->gen == 9) { + u32 dfsm = I915_READ(SKL_DFSM); + u8 disabled_mask = 0; + bool invalid; + int num_bits; + + if (dfsm & SKL_DFSM_PIPE_A_DISABLE) + disabled_mask |= BIT(PIPE_A); + if (dfsm & SKL_DFSM_PIPE_B_DISABLE) + disabled_mask |= BIT(PIPE_B); + if (dfsm & SKL_DFSM_PIPE_C_DISABLE) + disabled_mask |= BIT(PIPE_C); + + num_bits = hweight8(disabled_mask); + + switch (disabled_mask) { + case BIT(PIPE_A): + case BIT(PIPE_B): + case BIT(PIPE_A) | BIT(PIPE_B): + case BIT(PIPE_A) | BIT(PIPE_C): + invalid = true; + break; + default: + invalid = false; + } + + if (num_bits > info->num_pipes || invalid) + DRM_ERROR("invalid pipe fuse configuration: 0x%x\n", + disabled_mask); + else + info->num_pipes -= num_bits; } /* Initialize slice/subslice/EU info */ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 556a458..c6e6a24 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5991,6 +5991,9 @@ enum skl_disp_power_wells { #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23) #define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23) #define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23) +#define SKL_DFSM_PIPE_A_DISABLE (1 << 30) +#define SKL_DFSM_PIPE_B_DISABLE (1 << 21) +#define SKL_DFSM_PIPE_C_DISABLE (1 << 28) #define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4) #define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8)
On SKL and KBL we can have pipe A/B/C disabled by fuse settings. The pipes must be fused in descending order (e.g. C, B+C, A+B+C). We simply decrease info->num_pipes if we find a valid fused out config. v2: Don't store the pipe disabled mask in device info (Damien) v3: Don't check FUSE_STRAP register for pipe c disabled Cc: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com> --- drivers/gpu/drm/i915/i915_dma.c | 31 +++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 3 +++ 2 files changed, 34 insertions(+)