| Message ID | 1454322472-6696-1-git-send-email-yoshihiro.shimoda.uh@renesas.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Simon Horman |
| Headers | show |
Hi Shimoda-san, On Mon, Feb 1, 2016 at 11:27 AM, Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> wrote: > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Thanks for your patch! > --- > This patch is based on the renesas-drivers.git / > renesas-devel-20160126-v4.5-rc1 tag. > (commit id = f834955ea55e4bed01d55339a4428eef219e8313) > > Reference: > http://thread.gmane.org/gmane.linux.kernel.clk/3337/focus=184 > > drivers/clk/shmobile/r8a7795-cpg-mssr.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/clk/shmobile/r8a7795-cpg-mssr.c b/drivers/clk/shmobile/r8a7795-cpg-mssr.c > index fc260b3..13d59d1 100644 > --- a/drivers/clk/shmobile/r8a7795-cpg-mssr.c > +++ b/drivers/clk/shmobile/r8a7795-cpg-mssr.c > @@ -124,6 +124,8 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = { > DEF_MOD("pcie0", 319, R8A7795_CLK_S3D1), > DEF_MOD("usb3-if1", 327, R8A7795_CLK_S3D1), > DEF_MOD("usb3-if0", 328, R8A7795_CLK_S3D1), > + DEF_MOD("usb-dmac0", 330, R8A7795_CLK_S3D2), > + DEF_MOD("usb-dmac1", 331, R8A7795_CLK_S3D2), The datasheet is not very clear about whether the module clock is based of s3d1 (266 MHz) or s3d2 (133 MHz), but given the comment "... it is recommended to allow several tens of clocks if operating at 260 MHz ..." in section 75.2.2 "DMA0/1 Software Reset Register" of the datasheet, I'm inclined to believe s3d1 would be correct. I don't think it matters much though, as we're not interested in the actual rate of the module clock, and both s3d1 and s3d2 cannot be gated. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Geert-san, > From: geert.uytterhoeven@gmail.com [mailto:geert.uytterhoeven@gmail.com] On Behalf Of Geert Uytterhoeven > Sent: Monday, February 01, 2016 7:41 PM > > Hi Shimoda-san, > > On Mon, Feb 1, 2016 at 11:27 AM, Yoshihiro Shimoda > <yoshihiro.shimoda.uh@renesas.com> wrote: > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> > > Thanks for your patch! > > > --- > > This patch is based on the renesas-drivers.git / > > renesas-devel-20160126-v4.5-rc1 tag. > > (commit id = f834955ea55e4bed01d55339a4428eef219e8313) > > > > Reference: > > http://thread.gmane.org/gmane.linux.kernel.clk/3337/focus=184 > > > > drivers/clk/shmobile/r8a7795-cpg-mssr.c | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/drivers/clk/shmobile/r8a7795-cpg-mssr.c b/drivers/clk/shmobile/r8a7795-cpg-mssr.c > > index fc260b3..13d59d1 100644 > > --- a/drivers/clk/shmobile/r8a7795-cpg-mssr.c > > +++ b/drivers/clk/shmobile/r8a7795-cpg-mssr.c > > @@ -124,6 +124,8 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = { > > DEF_MOD("pcie0", 319, R8A7795_CLK_S3D1), > > DEF_MOD("usb3-if1", 327, R8A7795_CLK_S3D1), > > DEF_MOD("usb3-if0", 328, R8A7795_CLK_S3D1), > > + DEF_MOD("usb-dmac0", 330, R8A7795_CLK_S3D2), > > + DEF_MOD("usb-dmac1", 331, R8A7795_CLK_S3D2), > > The datasheet is not very clear about whether the module clock is based of s3d1 > (266 MHz) or s3d2 (133 MHz), but given the comment "... it is recommended to > allow several tens of clocks if operating at 260 MHz ..." in section 75.2.2 > "DMA0/1 Software Reset Register" of the datasheet, I'm inclined to believe s3d1 > would be correct. According to the HW team (in case of gen2 though): In gen2 (In gen3 I assumed) ZS (S3D1) : For using DRAM access HP (S3D2) : For using register access 48MHz (50MHz) : For using USB transfer So, I also think that s3d1 would be correct. What do you think? > I don't think it matters much though, as we're not interested in the actual > rate of the module clock, and both s3d1 and s3d2 cannot be gated. I agree with you. Best regards, Yoshihiro Shimoda > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds
Hi Shimoda-san, On Mon, Feb 1, 2016 at 12:06 PM, Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> wrote: >> From: geert.uytterhoeven@gmail.com [mailto:geert.uytterhoeven@gmail.com] On Behalf Of Geert Uytterhoeven >> > --- a/drivers/clk/shmobile/r8a7795-cpg-mssr.c >> > +++ b/drivers/clk/shmobile/r8a7795-cpg-mssr.c >> > @@ -124,6 +124,8 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = { >> > DEF_MOD("pcie0", 319, R8A7795_CLK_S3D1), >> > DEF_MOD("usb3-if1", 327, R8A7795_CLK_S3D1), >> > DEF_MOD("usb3-if0", 328, R8A7795_CLK_S3D1), >> > + DEF_MOD("usb-dmac0", 330, R8A7795_CLK_S3D2), >> > + DEF_MOD("usb-dmac1", 331, R8A7795_CLK_S3D2), >> >> The datasheet is not very clear about whether the module clock is based of s3d1 >> (266 MHz) or s3d2 (133 MHz), but given the comment "... it is recommended to >> allow several tens of clocks if operating at 260 MHz ..." in section 75.2.2 >> "DMA0/1 Software Reset Register" of the datasheet, I'm inclined to believe s3d1 >> would be correct. > > According to the HW team (in case of gen2 though): > > In gen2 (In gen3 I assumed) > ZS (S3D1) : For using DRAM access > HP (S3D2) : For using register access > 48MHz (50MHz) : For using USB transfer > > So, I also think that s3d1 would be correct. > What do you think? Thanks, that makes two of us :-) Hence please use s3d1. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Geert-san, > From: geert.uytterhoeven@gmail.com [mailto:geert.uytterhoeven@gmail.com] On Behalf Of Geert Uytterhoeven > Sent: Monday, February 01, 2016 8:16 PM > > Hi Shimoda-san, > > On Mon, Feb 1, 2016 at 12:06 PM, Yoshihiro Shimoda > <yoshihiro.shimoda.uh@renesas.com> wrote: > >> From: geert.uytterhoeven@gmail.com [mailto:geert.uytterhoeven@gmail.com] On Behalf Of Geert Uytterhoeven > >> > --- a/drivers/clk/shmobile/r8a7795-cpg-mssr.c > >> > +++ b/drivers/clk/shmobile/r8a7795-cpg-mssr.c > >> > @@ -124,6 +124,8 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = { > >> > DEF_MOD("pcie0", 319, R8A7795_CLK_S3D1), > >> > DEF_MOD("usb3-if1", 327, R8A7795_CLK_S3D1), > >> > DEF_MOD("usb3-if0", 328, R8A7795_CLK_S3D1), > >> > + DEF_MOD("usb-dmac0", 330, R8A7795_CLK_S3D2), > >> > + DEF_MOD("usb-dmac1", 331, R8A7795_CLK_S3D2), > >> > >> The datasheet is not very clear about whether the module clock is based of s3d1 > >> (266 MHz) or s3d2 (133 MHz), but given the comment "... it is recommended to > >> allow several tens of clocks if operating at 260 MHz ..." in section 75.2.2 > >> "DMA0/1 Software Reset Register" of the datasheet, I'm inclined to believe s3d1 > >> would be correct. > > > > According to the HW team (in case of gen2 though): > > > > In gen2 (In gen3 I assumed) > > ZS (S3D1) : For using DRAM access > > HP (S3D2) : For using register access > > 48MHz (50MHz) : For using USB transfer > > > > So, I also think that s3d1 would be correct. > > What do you think? > > Thanks, that makes two of us :-) > Hence please use s3d1. Thank you for the comment :) I will submit v2 patch soon. Best regards, Yoshihiro Shimoda > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds
diff --git a/drivers/clk/shmobile/r8a7795-cpg-mssr.c b/drivers/clk/shmobile/r8a7795-cpg-mssr.c index fc260b3..13d59d1 100644 --- a/drivers/clk/shmobile/r8a7795-cpg-mssr.c +++ b/drivers/clk/shmobile/r8a7795-cpg-mssr.c @@ -124,6 +124,8 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = { DEF_MOD("pcie0", 319, R8A7795_CLK_S3D1), DEF_MOD("usb3-if1", 327, R8A7795_CLK_S3D1), DEF_MOD("usb3-if0", 328, R8A7795_CLK_S3D1), + DEF_MOD("usb-dmac0", 330, R8A7795_CLK_S3D2), + DEF_MOD("usb-dmac1", 331, R8A7795_CLK_S3D2), DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1), DEF_MOD("audmac0", 502, R8A7795_CLK_S3D4), DEF_MOD("audmac1", 501, R8A7795_CLK_S3D4),
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> --- This patch is based on the renesas-drivers.git / renesas-devel-20160126-v4.5-rc1 tag. (commit id = f834955ea55e4bed01d55339a4428eef219e8313) Reference: http://thread.gmane.org/gmane.linux.kernel.clk/3337/focus=184 drivers/clk/shmobile/r8a7795-cpg-mssr.c | 2 ++ 1 file changed, 2 insertions(+)