| Message ID | 1454401807-28751-1-git-send-email-Minghuan.Lian@nxp.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tuesday 02 February 2016 16:30:07 Minghuan Lian wrote: > LS1021a contains two PCIe controllers. The patch adds their node to > dts file. > > Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> > --- > arch/arm/boot/dts/ls1021a.dtsi | 44 ++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 44 insertions(+) > Looks ok to me, please submit to the ARM imx maintainers for merging. Arnd
Hi Shawn, Could you please help to review the patch? Thank you very much. There is only one patch not a set of patch, please ignore [1/4] :( Arnd has given a ack. Thanks, Minghuan > -----Original Message----- > From: Minghuan Lian [mailto:Minghuan.Lian@nxp.com] > Sent: Tuesday, February 02, 2016 4:30 PM > To: linux-pci@vger.kernel.org > Cc: linux-arm-kernel@lists.infradead.org; Roy Zang <roy.zang@nxp.com>; > Mingkai Hu <mingkai.hu@nxp.com>; Stuart Yoder <stuart.yoder@nxp.com>; > Yang-Leo Li <leoyang.li@nxp.com>; Arnd Bergmann <arnd@arndb.de>; Bjorn > Helgaas <bhelgaas@google.com>; Minghuan Lian <minghuan.lian@nxp.com> > Subject: [PATCH 1/4] ARM: dts: ls1021a: add PCIe dts node > > LS1021a contains two PCIe controllers. The patch adds their node to dts file. > > Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> > --- > arch/arm/boot/dts/ls1021a.dtsi | 44 > ++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 44 insertions(+) > > diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi > index 2c84ca2..274d647 100644 > --- a/arch/arm/boot/dts/ls1021a.dtsi > +++ b/arch/arm/boot/dts/ls1021a.dtsi > @@ -560,5 +560,49 @@ > dr_mode = "host"; > snps,quirk-frame-length-adjustment = <0x20>; > }; > + > + pcie@3400000 { > + compatible = "fsl,ls1021a-pcie", "snps,dw-pcie"; > + reg = <0x00 0x03400000 0x0 0x00010000 /* controller > registers */ > + 0x40 0x00000000 0x0 0x00002000>; /* configuration > space */ > + reg-names = "regs", "config"; > + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* > controller interrupt */ > + fsl,pcie-scfg = <&scfg 0>; > + #address-cells = <3>; > + #size-cells = <2>; > + device_type = "pci"; > + num-lanes = <4>; > + bus-range = <0x0 0xff>; > + ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 > 0x00010000 /* downstream I/O */ > + 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 > 0x40000000>; /* non-prefetchable memory */ > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 7>; > + interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 > IRQ_TYPE_LEVEL_HIGH>, > + <0000 0 0 2 &gic GIC_SPI 188 > IRQ_TYPE_LEVEL_HIGH>, > + <0000 0 0 3 &gic GIC_SPI 190 > IRQ_TYPE_LEVEL_HIGH>, > + <0000 0 0 4 &gic GIC_SPI 192 > IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + pcie@3500000 { > + compatible = "fsl,ls1021a-pcie", "snps,dw-pcie"; > + reg = <0x00 0x03500000 0x0 0x00010000 /* controller > registers */ > + 0x48 0x00000000 0x0 0x00002000>; /* configuration > space */ > + reg-names = "regs", "config"; > + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; > + fsl,pcie-scfg = <&scfg 1>; > + #address-cells = <3>; > + #size-cells = <2>; > + device_type = "pci"; > + num-lanes = <4>; > + bus-range = <0x0 0xff>; > + ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 > 0x00010000 /* downstream I/O */ > + 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 > 0x40000000>; /* non-prefetchable memory */ > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 7>; > + interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 > IRQ_TYPE_LEVEL_HIGH>, > + <0000 0 0 2 &gic GIC_SPI 189 > IRQ_TYPE_LEVEL_HIGH>, > + <0000 0 0 3 &gic GIC_SPI 191 > IRQ_TYPE_LEVEL_HIGH>, > + <0000 0 0 4 &gic GIC_SPI 193 > IRQ_TYPE_LEVEL_HIGH>; > + }; > }; > }; > -- > 1.9.1
On Tuesday 02 February 2016 08:48:36 Minghuan Lian wrote: > Hi Shawn, > > Could you please help to review the patch? Thank you very much. > There is only one patch not a set of patch, please ignore [1/4] > > Arnd has given a ack. For some reason, I did not get the other three patches though, I was going to look at them, but I can't tell if this was a series of patches doing PCI support, or patches doing other dts changes. If you have additional patches for the PCI driver, let's review it all together first. Arnd
Hi Arnd, I am sorry. Other patches are for MSI test, and not need to be summited. There is only one patch, should be [1/1] not [1/4]. I forgot to remove "1/4" :( Should I re-summit to fix it? Thanks, Minghuan > -----Original Message----- > From: Arnd Bergmann [mailto:arnd@arndb.de] > Sent: Tuesday, February 02, 2016 5:32 PM > To: linux-arm-kernel@lists.infradead.org > Cc: Minghuan Lian <minghuan.lian@nxp.com>; linux-pci@vger.kernel.org; > Shawn Guo <shawnguo@kernel.org>; Sascha Hauer <kernel@pengutronix.de>; > Roy Zang <roy.zang@nxp.com>; Stuart Yoder <stuart.yoder@nxp.com>; > Yang-Leo Li <leoyang.li@nxp.com>; Bjorn Helgaas <bhelgaas@google.com>; > Mingkai Hu <mingkai.hu@nxp.com> > Subject: Re: [PATCH 1/4] ARM: dts: ls1021a: add PCIe dts node > > On Tuesday 02 February 2016 08:48:36 Minghuan Lian wrote: > > Hi Shawn, > > > > Could you please help to review the patch? Thank you very much. > > There is only one patch not a set of patch, please ignore [1/4] > > > > Arnd has given a ack. > > For some reason, I did not get the other three patches though, I was going to > look at them, but I can't tell if this was a series of patches doing PCI support, or > patches doing other dts changes. > > If you have additional patches for the PCI driver, let's review it all together first. > > Arnd
On Wednesday 03 February 2016 02:11:06 Minghuan Lian wrote: > Hi Arnd, > > I am sorry. > Other patches are for MSI test, and not need to be summited. > There is only one patch, should be [1/1] not [1/4]. I forgot to remove "1/4" > Should I re-summit to fix it? > Ok, I see. It's up to Shawn then, I guess he can pick it up from this submission if he's ok with the patch. Arnd
On Tue, Feb 02, 2016 at 04:30:07PM +0800, Minghuan Lian wrote: > LS1021a contains two PCIe controllers. The patch adds their node to > dts file. > > Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Applied, thanks.
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 2c84ca2..274d647 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -560,5 +560,49 @@ dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; }; + + pcie@3400000 { + compatible = "fsl,ls1021a-pcie", "snps,dw-pcie"; + reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */ + 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ + fsl,pcie-scfg = <&scfg 0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; + }; + + pcie@3500000 { + compatible = "fsl,ls1021a-pcie", "snps,dw-pcie"; + reg = <0x00 0x03500000 0x0 0x00010000 /* controller registers */ + 0x48 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; + fsl,pcie-scfg = <&scfg 1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; + }; }; };
LS1021a contains two PCIe controllers. The patch adds their node to dts file. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> --- arch/arm/boot/dts/ls1021a.dtsi | 44 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+)