| Message ID | 1454581857-12921-2-git-send-email-jarkko.nikula@linux.intel.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 7a8d44bc89e5cddcd5c0704a11a90484d36ba6ba |
| Headers | show |
Jarkko Nikula <jarkko.nikula@linux.intel.com> writes: > There is a chance that chipselect is deasserted too early while the last > clock cycle is still running. Protocol analyzers will see this as a failed > last byte. This is more likely to occur with slow bitrates, for instance > at 25 kbps. > > Reason for this is when using SPI mode 0 that both SPI host controller and > SPI slave will drive the data lines at the falling edge of clock signal > and sample at the rising edge. Receive FIFO gets the last bit now at the > rising edge and code sees transfer to be finished either by the interrupt > in PIO mode or by the DMA completion in DMA mode. > > The SSP Time Out register SSTO should take care of delaying the > completion but it does not seems to have effect at least on Intel > Skylake and Broxton even when using long enough values. Depending on > timing code may get into point where chipselect is deasserted while the > last clock cycle is still running at its second half cycle. > > Fix this by adding a wait loop in giveback() that waits until SSP becomes > idle before deasserting the chipselect. > > Reported-by: Weifeng Voon <weifeng.voon@intel.com> > Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> > --- > For normal development cycle. This is not a fatal issue and I guess real SPI > slaves may not hickup because of it. But you never know. I feel quite nervous about this one, as it will affect all pxa variants, for a Skylake and Broxton issues. What makes me even more nervous is that I don't have a way to test it yet ... I will neither ack nor block it, let's have others judge it first. Cheers.
On 02/04/2016 11:01 PM, Robert Jarzmik wrote: > Jarkko Nikula <jarkko.nikula@linux.intel.com> writes: > >> There is a chance that chipselect is deasserted too early while the last >> clock cycle is still running. Protocol analyzers will see this as a failed >> last byte. This is more likely to occur with slow bitrates, for instance >> at 25 kbps. >> >> Reason for this is when using SPI mode 0 that both SPI host controller and >> SPI slave will drive the data lines at the falling edge of clock signal >> and sample at the rising edge. Receive FIFO gets the last bit now at the >> rising edge and code sees transfer to be finished either by the interrupt >> in PIO mode or by the DMA completion in DMA mode. >> >> The SSP Time Out register SSTO should take care of delaying the >> completion but it does not seems to have effect at least on Intel >> Skylake and Broxton even when using long enough values. Depending on >> timing code may get into point where chipselect is deasserted while the >> last clock cycle is still running at its second half cycle. >> >> Fix this by adding a wait loop in giveback() that waits until SSP becomes >> idle before deasserting the chipselect. >> >> Reported-by: Weifeng Voon <weifeng.voon@intel.com> >> Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> >> --- >> For normal development cycle. This is not a fatal issue and I guess real SPI >> slaves may not hickup because of it. But you never know. > > I feel quite nervous about this one, as it will affect all pxa variants, for a > Skylake and Broxton issues. > > What makes me even more nervous is that I don't have a way to test it yet ... > > I will neither ack nor block it, let's have others judge it first. > I didn't see reason to do this conditionally as pxa2xx_spi_flush() is polling the busy bit too. However your question reminded me I haven't looked the PXA data sheets at all but just the code only that changes don't break the existing PXA cases. According to PXA3xx datasheet the busy bit is defined as in Intel platforms.
diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c index 9b9a528a9fbd..ce66cf44bba5 100644 --- a/drivers/spi/spi-pxa2xx.c +++ b/drivers/spi/spi-pxa2xx.c @@ -496,6 +496,7 @@ static void giveback(struct driver_data *drv_data) { struct spi_transfer* last_transfer; struct spi_message *msg; + unsigned long timeout; msg = drv_data->cur_msg; drv_data->cur_msg = NULL; @@ -508,6 +509,12 @@ static void giveback(struct driver_data *drv_data) if (last_transfer->delay_usecs) udelay(last_transfer->delay_usecs); + /* Wait until SSP becomes idle before deasserting the CS */ + timeout = jiffies + msecs_to_jiffies(10); + while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY && + !time_after(jiffies, timeout)) + cpu_relax(); + /* Drop chip select UNLESS cs_change is true or we are returning * a message with an error, or next message is for another chip */
There is a chance that chipselect is deasserted too early while the last clock cycle is still running. Protocol analyzers will see this as a failed last byte. This is more likely to occur with slow bitrates, for instance at 25 kbps. Reason for this is when using SPI mode 0 that both SPI host controller and SPI slave will drive the data lines at the falling edge of clock signal and sample at the rising edge. Receive FIFO gets the last bit now at the rising edge and code sees transfer to be finished either by the interrupt in PIO mode or by the DMA completion in DMA mode. The SSP Time Out register SSTO should take care of delaying the completion but it does not seems to have effect at least on Intel Skylake and Broxton even when using long enough values. Depending on timing code may get into point where chipselect is deasserted while the last clock cycle is still running at its second half cycle. Fix this by adding a wait loop in giveback() that waits until SSP becomes idle before deasserting the chipselect. Reported-by: Weifeng Voon <weifeng.voon@intel.com> Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> --- For normal development cycle. This is not a fatal issue and I guess real SPI slaves may not hickup because of it. But you never know. --- drivers/spi/spi-pxa2xx.c | 7 +++++++ 1 file changed, 7 insertions(+)