| Message ID | 1454922699-16785-3-git-send-email-antoine.tenart@free-electrons.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi, > + chosen { > + stdout-path = "console0:115200n8"; > + }; There is no console0 alias, so this cannot work. Did you mean serial0? [...] > + aliases { > + serial0 = &uart0; > + serial1 = &uart1; > + serial2 = &uart2; > + serial3 = &uart3; > + }; [...] > + psci { > + compatible = "arm,psci-0.2", "arm,psci"; > + method = "smc"; > + cpu_on = <0x84000003>; > + }; If you have PSCI 0.2, the cpu_on ID (and all other mandatory function IDs) are implicit. If you want to have "arm,psci" as a fallback, then please add the IDs for functions mandatory in PSCI 0.2 which existed in the "arm,psci" binding. Otherwise, drop "arm,psci" from the compatible list, along with the cpu_on function ID. THanks, Mark.
Hi Mark, On Mon, Feb 08, 2016 at 10:51:05AM +0000, Mark Rutland wrote: > > > + chosen { > > + stdout-path = "console0:115200n8"; > > + }; > > There is no console0 alias, so this cannot work. > > Did you mean serial0? Oops... Yes, I meant serial0. I'll fix this. > [...] > > > + aliases { > > + serial0 = &uart0; > > + serial1 = &uart1; > > + serial2 = &uart2; > > + serial3 = &uart3; > > + }; > > [...] > > > + psci { > > + compatible = "arm,psci-0.2", "arm,psci"; > > + method = "smc"; > > + cpu_on = <0x84000003>; > > + }; > > If you have PSCI 0.2, the cpu_on ID (and all other mandatory function > IDs) are implicit. > > If you want to have "arm,psci" as a fallback, then please add the IDs > for functions mandatory in PSCI 0.2 which existed in the "arm,psci" > binding. Otherwise, drop "arm,psci" from the compatible list, along > with the cpu_on function ID. OK. I'll make some tests and update. Thanks or the review! Antoine
On Monday 08 February 2016 10:11:38 Antoine Tenart wrote: > index 000000000000..3e3080fa45e4 > --- /dev/null > + > +#include <dt-bindings/interrupt-controller/arm-gic.h> > + > +/ { > + model = "Annapurna Labs Alpine v2"; > + compatible = "al,alpine-v2"; > + #address-cells = <2>; > + #size-cells = <2>; > + > + aliases { > + serial0 = &uart0; > + serial1 = &uart1; > + serial2 = &uart2; > + serial3 = &uart3; > + }; Move the aliases to the .dts files and drop the ones that are disabled. > + > + pcie-internal@0xfbc00000 { make this pci@fbc00000 { > + compatible = "pci-host-ecam-generic"; > + device_type = "pci"; > + #size-cells = <2>; > + #address-cells = <3>; > + #interrupt-cells = <1>; > + reg = <0x0 0xfbc00000 0x0 0x100000>; > + interrupt-map-mask = <0xf800 0 0 7>; > + /* add legacy interrupts for SATA only */ > + interrupt-map = <0x4000 0 0 1 &gic 0 53 4>, > + <0x4800 0 0 1 &gic 0 54 4>; What's wrong with the other IRQs? Not connected? > + > + uart0: uart@fd883000 { serial@fd883000 Almost all devices are in the 0xfd000000 range. Could this be a bus in the SoC that has all the devices attached to it? Maybe use a "ranges" property to reflect that. In doubt, use the register numbers from the data sheet if you have one. Arnd
On 08/02/16 09:11, Antoine Tenart wrote: > This patch adds the initial support for the Alpine v2 EVP board from > Annapurna Labs (Amazon). > > Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> > Signed-off-by: Barak Wasserstrom <barak@annapurnalabs.com> > Signed-off-by: Tsahee Zidenberg <tsahee@annapurnalabs.com> > --- > arch/arm64/boot/dts/Makefile | 1 + > arch/arm64/boot/dts/al/Makefile | 5 + > arch/arm64/boot/dts/al/alpine-v2-evp.dts | 46 +++++++ > arch/arm64/boot/dts/al/alpine-v2.dtsi | 221 +++++++++++++++++++++++++++++++ > 4 files changed, 273 insertions(+) > create mode 100644 arch/arm64/boot/dts/al/Makefile > create mode 100644 arch/arm64/boot/dts/al/alpine-v2-evp.dts > create mode 100644 arch/arm64/boot/dts/al/alpine-v2.dtsi > > diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile > index f832b8a7453a..fd80617a9c6f 100644 > --- a/arch/arm64/boot/dts/Makefile > +++ b/arch/arm64/boot/dts/Makefile > @@ -1,3 +1,4 @@ > +dts-dirs += al > dts-dirs += altera > dts-dirs += amd > dts-dirs += apm > diff --git a/arch/arm64/boot/dts/al/Makefile b/arch/arm64/boot/dts/al/Makefile > new file mode 100644 > index 000000000000..8a6cde4f9b23 > --- /dev/null > +++ b/arch/arm64/boot/dts/al/Makefile > @@ -0,0 +1,5 @@ > +dtb-$(CONFIG_ARCH_ALPINE) += alpine-v2-evp.dtb > + > +always := $(dtb-y) > +subdir-y := $(dts-dirs) > +clean-files := *.dtb > diff --git a/arch/arm64/boot/dts/al/alpine-v2-evp.dts b/arch/arm64/boot/dts/al/alpine-v2-evp.dts > new file mode 100644 > index 000000000000..3e3080fa45e4 > --- /dev/null > +++ b/arch/arm64/boot/dts/al/alpine-v2-evp.dts > @@ -0,0 +1,46 @@ > +/* > + * Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. > + * > + * Antoine Tenart <antoine.tenart@free-electrons.com> > + * > + * This software is available to you under a choice of one of two > + * licenses. You may choose to be licensed under the terms of the GNU > + * General Public License (GPL) Version 2, available from the file > + * COPYING in the main directory of this source tree, or the > + * BSD license below: > + * > + * Redistribution and use in source and binary forms, with or > + * without modification, are permitted provided that the following > + * conditions are met: > + * > + * - Redistributions of source code must retain the above > + * copyright notice, this list of conditions and the following > + * disclaimer. > + * > + * - Redistributions in binary form must reproduce the above > + * copyright notice, this list of conditions and the following > + * disclaimer in the documentation and/or other materials > + * provided with the distribution. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF > + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND > + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS > + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN > + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN > + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE > + * SOFTWARE. > + */ > + > +#include "alpine-v2.dtsi" > + > +/ { > + model = "Annapurna Labs Alpine v2 EVP"; > + compatible = "al,alpine-v2-evp", "al,alpine-v2"; > + > + chosen { > + stdout-path = "console0:115200n8"; > + }; > +}; > + > +&uart0 { status = "okay"; }; > diff --git a/arch/arm64/boot/dts/al/alpine-v2.dtsi b/arch/arm64/boot/dts/al/alpine-v2.dtsi > new file mode 100644 > index 000000000000..eb7a03b71456 > --- /dev/null > +++ b/arch/arm64/boot/dts/al/alpine-v2.dtsi > @@ -0,0 +1,221 @@ > +/* > + * Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. > + * > + * Antoine Tenart <antoine.tenart@free-electrons.com> > + * > + * This software is available to you under a choice of one of two > + * licenses. You may choose to be licensed under the terms of the GNU > + * General Public License (GPL) Version 2, available from the file > + * COPYING in the main directory of this source tree, or the > + * BSD license below: > + * > + * Redistribution and use in source and binary forms, with or > + * without modification, are permitted provided that the following > + * conditions are met: > + * > + * - Redistributions of source code must retain the above > + * copyright notice, this list of conditions and the following > + * disclaimer. > + * > + * - Redistributions in binary form must reproduce the above > + * copyright notice, this list of conditions and the following > + * disclaimer in the documentation and/or other materials > + * provided with the distribution. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF > + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND > + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS > + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN > + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN > + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE > + * SOFTWARE. > + */ > + > +/dts-v1/; > + > +#include <dt-bindings/interrupt-controller/arm-gic.h> > + > +/ { > + model = "Annapurna Labs Alpine v2"; > + compatible = "al,alpine-v2"; > + #address-cells = <2>; > + #size-cells = <2>; > + > + aliases { > + serial0 = &uart0; > + serial1 = &uart1; > + serial2 = &uart2; > + serial3 = &uart3; > + }; > + > + cpus { > + #address-cells = <2>; > + #size-cells = <0>; > + > + cpu@0 { > + compatible = "arm,cortex-a57", "arm,armv8"; > + device_type = "cpu"; > + reg = <0x0 0x0>; > + enable-method = "psci"; > + }; > + > + cpu@1 { > + compatible = "arm,cortex-a57", "arm,armv8"; > + device_type = "cpu"; > + reg = <0x0 0x1>; > + enable-method = "psci"; > + }; > + > + cpu@2 { > + compatible = "arm,cortex-a57", "arm,armv8"; > + device_type = "cpu"; > + reg = <0x0 0x2>; > + enable-method = "psci"; > + }; > + > + cpu@3 { > + compatible = "arm,cortex-a57", "arm,armv8"; > + device_type = "cpu"; > + reg = <0x0 0x3>; > + enable-method = "psci"; > + }; > + }; > + > + psci { > + compatible = "arm,psci-0.2", "arm,psci"; > + method = "smc"; > + cpu_on = <0x84000003>; > + }; > + > + sbclk: sbclk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <1000000>; > + }; > + > + soc { > + compatible = "simple-bus"; > + #address-cells = <2>; > + #size-cells = <2>; > + > + interrupt-parent = <&gic>; > + ranges; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = <GIC_PPI 0xd 0xff08>, > + <GIC_PPI 0xe 0xff08>, > + <GIC_PPI 0xb 0xff08>, > + <GIC_PPI 0xa 0xff08>; > + }; This is not a valid interrupt specifier for GICv3, as the 3rd field shouldn't bear this 0xff thing. > + gic: gic@f0100000 { > + compatible = "arm,gic-v3"; > + reg = <0x0 0xf0200000 0x0 0x10000>, /* GIC Dist */ > + <0x0 0xf0280000 0x0 0x200000>, /* GICR */ > + <0x0 0xf0100000 0x0 0x2000>; /* GICC */ > + interrupt-controller; > + #interrupt-cells = <3>; > + }; Something is wrong here. Either you are missing GICH and GICV (assuming you have legacy support), or you have an extra GICC region (which doesn't make sense on its own). You're also missing the maintenance interrupt. Has Anapurna really built a GICv3 without an ITS? Thanks, M.
Hi Marc, On Mon, Feb 08, 2016 at 03:29:33PM +0000, Marc Zyngier wrote: > On 08/02/16 09:11, Antoine Tenart wrote: > > > + gic: gic@f0100000 { > > + compatible = "arm,gic-v3"; > > + reg = <0x0 0xf0200000 0x0 0x10000>, /* GIC Dist */ > > + <0x0 0xf0280000 0x0 0x200000>, /* GICR */ > > + <0x0 0xf0100000 0x0 0x2000>; /* GICC */ > > + interrupt-controller; > > + #interrupt-cells = <3>; > > + }; > > Something is wrong here. Either you are missing GICH and GICV (assuming > you have legacy support), or you have an extra GICC region (which > doesn't make sense on its own). > > You're also missing the maintenance interrupt. > > Has Anapurna really built a GICv3 without an ITS? I documented myself and Annapurna's GIC really doesn't have an ITS. I'll add the missing regions. Antoine
On Tue, Feb 09, 2016 at 09:56:33AM +0100, Antoine Tenart wrote: > Hi Marc, > > On Mon, Feb 08, 2016 at 03:29:33PM +0000, Marc Zyngier wrote: > > On 08/02/16 09:11, Antoine Tenart wrote: > > > > > + gic: gic@f0100000 { > > > + compatible = "arm,gic-v3"; > > > + reg = <0x0 0xf0200000 0x0 0x10000>, /* GIC Dist */ > > > + <0x0 0xf0280000 0x0 0x200000>, /* GICR */ > > > + <0x0 0xf0100000 0x0 0x2000>; /* GICC */ > > > + interrupt-controller; > > > + #interrupt-cells = <3>; > > > + }; > > > > Something is wrong here. Either you are missing GICH and GICV (assuming > > you have legacy support), or you have an extra GICC region (which > > doesn't make sense on its own). > > I'll add the missing regions. Hmm, in fact the GICC region shouldn't be there. I'll make some tests and remove it. Antoine
On 09/02/16 09:01, Antoine Tenart wrote: > On Tue, Feb 09, 2016 at 09:56:33AM +0100, Antoine Tenart wrote: >> Hi Marc, >> >> On Mon, Feb 08, 2016 at 03:29:33PM +0000, Marc Zyngier wrote: >>> On 08/02/16 09:11, Antoine Tenart wrote: >>> >>>> + gic: gic@f0100000 { >>>> + compatible = "arm,gic-v3"; >>>> + reg = <0x0 0xf0200000 0x0 0x10000>, /* GIC Dist */ >>>> + <0x0 0xf0280000 0x0 0x200000>, /* GICR */ >>>> + <0x0 0xf0100000 0x0 0x2000>; /* GICC */ >>>> + interrupt-controller; >>>> + #interrupt-cells = <3>; >>>> + }; >>> >>> Something is wrong here. Either you are missing GICH and GICV (assuming >>> you have legacy support), or you have an extra GICC region (which >>> doesn't make sense on its own). >> >> I'll add the missing regions. > > Hmm, in fact the GICC region shouldn't be there. I'll make some tests > and remove it. If you have a GICv3 with legacy support, you will probably have GICC, GICH and GICV. Linux itself will only use GICD and GICR, but it needs at least GICV to be able to virtualize GICv2 guests. And GICV is not allowed to exist without GICC and GICH, so I really recommend that you keep GICC around. Thanks, M.
On 09/02/16 09:14, Tsahee Zidenberg wrote: > > > On 9 February 2016 at 11:09, Marc Zyngier <marc.zyngier@arm.com > <mailto:marc.zyngier@arm.com>> wrote: > > On 09/02/16 09:01, Antoine Tenart wrote: > > On Tue, Feb 09, 2016 at 09:56:33AM +0100, Antoine Tenart wrote: > >> Hi Marc, > >> > >> On Mon, Feb 08, 2016 at 03:29:33PM +0000, Marc Zyngier wrote: > >>> On 08/02/16 09:11, Antoine Tenart wrote: > >>> > >>>> + gic: gic@f0100000 { > >>>> + compatible = "arm,gic-v3"; > >>>> + reg = <0x0 0xf0200000 0x0 0x10000>, /* GIC Dist */ > >>>> + <0x0 0xf0280000 0x0 0x200000>, /* GICR */ > >>>> + <0x0 0xf0100000 0x0 0x2000>; /* GICC */ > >>>> + interrupt-controller; > >>>> + #interrupt-cells = <3>; > >>>> + }; > >>> > >>> Something is wrong here. Either you are missing GICH and GICV (assuming > >>> you have legacy support), or you have an extra GICC region (which > >>> doesn't make sense on its own). > >> > >> I'll add the missing regions. > > > > Hmm, in fact the GICC region shouldn't be there. I'll make some tests > > and remove it. > > If you have a GICv3 with legacy support, you will probably have GICC, > GICH and GICV. Linux itself will only use GICD and GICR, but it needs at > least GICV to be able to virtualize GICv2 guests. And GICV is not > allowed to exist without GICC and GICH, so I really recommend that you > keep GICC around. > > > We use the GIC without legacy support (we disable it in early boot > stages), so I think removing the GICC region is the better solution. Disabling legacy support doesn't mean that: - the HW isn't present - the associated regions are not useful Here, we describe the HW, not the usage you make of it. And unless you think that having working virtualization is completely useless, I strongly suggest that you properly document the HW in the device tree. Thanks, M.
On 9 February 2016 at 11:30, Marc Zyngier <marc.zyngier@arm.com> wrote: > > On 09/02/16 09:14, Tsahee Zidenberg wrote: > > > > > > On 9 February 2016 at 11:09, Marc Zyngier <marc.zyngier@arm.com > > <mailto:marc.zyngier@arm.com>> wrote: > > > > On 09/02/16 09:01, Antoine Tenart wrote: > > > On Tue, Feb 09, 2016 at 09:56:33AM +0100, Antoine Tenart wrote: > > >> Hi Marc, > > >> > > >> On Mon, Feb 08, 2016 at 03:29:33PM +0000, Marc Zyngier wrote: > > >>> On 08/02/16 09:11, Antoine Tenart wrote: > > >>> > > >>>> + gic: gic@f0100000 { > > >>>> + compatible = "arm,gic-v3"; > > >>>> + reg = <0x0 0xf0200000 0x0 0x10000>, /* GIC Dist */ > > >>>> + <0x0 0xf0280000 0x0 0x200000>, /* GICR */ > > >>>> + <0x0 0xf0100000 0x0 0x2000>; /* GICC */ > > >>>> + interrupt-controller; > > >>>> + #interrupt-cells = <3>; > > >>>> + }; > > >>> > > >>> Something is wrong here. Either you are missing GICH and GICV (assuming > > >>> you have legacy support), or you have an extra GICC region (which > > >>> doesn't make sense on its own). > > >> > > >> I'll add the missing regions. > > > > > > Hmm, in fact the GICC region shouldn't be there. I'll make some tests > > > and remove it. > > > > If you have a GICv3 with legacy support, you will probably have GICC, > > GICH and GICV. Linux itself will only use GICD and GICR, but it needs at > > least GICV to be able to virtualize GICv2 guests. And GICV is not > > allowed to exist without GICC and GICH, so I really recommend that you > > keep GICC around. > > > > > > We use the GIC without legacy support (we disable it in early boot > > stages), so I think removing the GICC region is the better solution. > > Disabling legacy support doesn't mean that: > - the HW isn't present > - the associated regions are not useful > By "disabling lecgacy support in early boot" I don't just mean that ARE bit will be set, but it will actually be RAO/WI. There will be no way for SW to enable it and use these registers (which, sadly, means that there will be no way to enable gicv2 virtualization). If you insist - I will dig up the supposed location of GICV and GICH - yet it will be both untested and entirely unusable. We will add an entry for the maintenance interrupt, as it really can be used by future configurations. > Here, we describe the HW, not the usage you make of it. > > And unless you think that having working virtualization is completely > useless, I strongly suggest that you properly document the HW in the > device tree. > > Thanks, > > M. > -- > Jazz is not dead. It just smells funny...
Hello Arnd, On Mon, Feb 08, 2016 at 01:20:40PM +0100, Arnd Bergmann wrote: > On Monday 08 February 2016 10:11:38 Antoine Tenart wrote: > > index 000000000000..3e3080fa45e4 > > --- /dev/null > > + > > +#include <dt-bindings/interrupt-controller/arm-gic.h> > > + > > +/ { > > + model = "Annapurna Labs Alpine v2"; > > + compatible = "al,alpine-v2"; > > + #address-cells = <2>; > > + #size-cells = <2>; > > + > > + aliases { > > + serial0 = &uart0; > > + serial1 = &uart1; > > + serial2 = &uart2; > > + serial3 = &uart3; > > + }; > > Move the aliases to the .dts files and drop the ones that are disabled. Sure. > > + > > + pcie-internal@0xfbc00000 { > > make this > > pci@fbc00000 { Will do. > > > + compatible = "pci-host-ecam-generic"; > > + device_type = "pci"; > > + #size-cells = <2>; > > + #address-cells = <3>; > > + #interrupt-cells = <1>; > > + reg = <0x0 0xfbc00000 0x0 0x100000>; > > + interrupt-map-mask = <0xf800 0 0 7>; > > + /* add legacy interrupts for SATA only */ > > + interrupt-map = <0x4000 0 0 1 &gic 0 53 4>, > > + <0x4800 0 0 1 &gic 0 54 4>; > > What's wrong with the other IRQs? Not connected? From what I know the other IRQs are disconnected. > > + > > + uart0: uart@fd883000 { > > serial@fd883000 > > > Almost all devices are in the 0xfd000000 range. Could this be a bus in the > SoC that has all the devices attached to it? Maybe use a "ranges" property > to reflect that. In doubt, use the register numbers from the data sheet if you > have one. I'll try using a range property in the v2 of the series. Thanks for the review! Antoine
On 09/02/16 10:13, Tsahee Zidenberg wrote: > On 9 February 2016 at 11:30, Marc Zyngier <marc.zyngier@arm.com> wrote: >> >> On 09/02/16 09:14, Tsahee Zidenberg wrote: >>> >>> >>> On 9 February 2016 at 11:09, Marc Zyngier <marc.zyngier@arm.com >>> <mailto:marc.zyngier@arm.com>> wrote: >>> >>> On 09/02/16 09:01, Antoine Tenart wrote: >>> > On Tue, Feb 09, 2016 at 09:56:33AM +0100, Antoine Tenart wrote: >>> >> Hi Marc, >>> >> >>> >> On Mon, Feb 08, 2016 at 03:29:33PM +0000, Marc Zyngier wrote: >>> >>> On 08/02/16 09:11, Antoine Tenart wrote: >>> >>> >>> >>>> + gic: gic@f0100000 { >>> >>>> + compatible = "arm,gic-v3"; >>> >>>> + reg = <0x0 0xf0200000 0x0 0x10000>, /* GIC Dist */ >>> >>>> + <0x0 0xf0280000 0x0 0x200000>, /* GICR */ >>> >>>> + <0x0 0xf0100000 0x0 0x2000>; /* GICC */ >>> >>>> + interrupt-controller; >>> >>>> + #interrupt-cells = <3>; >>> >>>> + }; >>> >>> >>> >>> Something is wrong here. Either you are missing GICH and GICV (assuming >>> >>> you have legacy support), or you have an extra GICC region (which >>> >>> doesn't make sense on its own). >>> >> >>> >> I'll add the missing regions. >>> > >>> > Hmm, in fact the GICC region shouldn't be there. I'll make some tests >>> > and remove it. >>> >>> If you have a GICv3 with legacy support, you will probably have GICC, >>> GICH and GICV. Linux itself will only use GICD and GICR, but it needs at >>> least GICV to be able to virtualize GICv2 guests. And GICV is not >>> allowed to exist without GICC and GICH, so I really recommend that you >>> keep GICC around. >>> >>> >>> We use the GIC without legacy support (we disable it in early boot >>> stages), so I think removing the GICC region is the better solution. >> >> Disabling legacy support doesn't mean that: >> - the HW isn't present >> - the associated regions are not useful >> > By "disabling lecgacy support in early boot" I don't just mean that > ARE bit will be set, but it will actually be RAO/WI. There will be no > way for SW to enable it and use these registers (which, sadly, means > that there will be no way to enable gicv2 virtualization). If you > insist - I will dig up the supposed location of GICV and GICH - yet it > will be both untested and entirely unusable. That's quite sad indeed. You are pointlessly breaking existing software. But hey, that's your choice. At that point, I can't be bothered to care. > We will add an entry for the maintenance interrupt, as it really can > be used by future configurations. Well, at least you'll be able to run GICv3 guests, assuming everything else is usable. M.
On 09/02/16 10:13, Tsahee Zidenberg wrote: > On 9 February 2016 at 11:30, Marc Zyngier <marc.zyngier@arm.com> wrote: >> >> On 09/02/16 09:14, Tsahee Zidenberg wrote: >>> >>> >>> On 9 February 2016 at 11:09, Marc Zyngier <marc.zyngier@arm.com >>> <mailto:marc.zyngier@arm.com>> wrote: >>> >>> On 09/02/16 09:01, Antoine Tenart wrote: >>> > On Tue, Feb 09, 2016 at 09:56:33AM +0100, Antoine Tenart wrote: >>> >> Hi Marc, >>> >> >>> >> On Mon, Feb 08, 2016 at 03:29:33PM +0000, Marc Zyngier wrote: >>> >>> On 08/02/16 09:11, Antoine Tenart wrote: >>> >>> >>> >>>> + gic: gic@f0100000 { >>> >>>> + compatible = "arm,gic-v3"; >>> >>>> + reg = <0x0 0xf0200000 0x0 0x10000>, /* GIC Dist */ >>> >>>> + <0x0 0xf0280000 0x0 0x200000>, /* GICR */ >>> >>>> + <0x0 0xf0100000 0x0 0x2000>; /* GICC */ >>> >>>> + interrupt-controller; >>> >>>> + #interrupt-cells = <3>; >>> >>>> + }; >>> >>> >>> >>> Something is wrong here. Either you are missing GICH and GICV (assuming >>> >>> you have legacy support), or you have an extra GICC region (which >>> >>> doesn't make sense on its own). >>> >> >>> >> I'll add the missing regions. >>> > >>> > Hmm, in fact the GICC region shouldn't be there. I'll make some tests >>> > and remove it. >>> >>> If you have a GICv3 with legacy support, you will probably have GICC, >>> GICH and GICV. Linux itself will only use GICD and GICR, but it needs at >>> least GICV to be able to virtualize GICv2 guests. And GICV is not >>> allowed to exist without GICC and GICH, so I really recommend that you >>> keep GICC around. >>> >>> >>> We use the GIC without legacy support (we disable it in early boot >>> stages), so I think removing the GICC region is the better solution. >> >> Disabling legacy support doesn't mean that: >> - the HW isn't present >> - the associated regions are not useful >> > By "disabling lecgacy support in early boot" I don't just mean that > ARE bit will be set, but it will actually be RAO/WI. There will be no > way for SW to enable it and use these registers (which, sadly, means > that there will be no way to enable gicv2 virtualization). If you > insist - I will dig up the supposed location of GICV and GICH - yet it > will be both untested and entirely unusable. Just to make sure you are not missing the point: ARE==1 does *not* mean that GICV is unusable. Quite the opposite. It only makes it illegal to use GICC and GICH, but leaves GICV usable for a guest. So the real question is: do you have any additional HW that would actively prevent GICV from being used? If the answer to that is "no", and assuming your GICv3 implementation is compliant with the architecture, then GICV will be usable, and you should document all 3 regions. Thanks, M.
On 9 February 2016 at 13:48, Marc Zyngier <marc.zyngier@arm.com> wrote: > On 09/02/16 10:13, Tsahee Zidenberg wrote: >> On 9 February 2016 at 11:30, Marc Zyngier <marc.zyngier@arm.com> wrote: >>> >>> On 09/02/16 09:14, Tsahee Zidenberg wrote: >>>> >>>> >>>> On 9 February 2016 at 11:09, Marc Zyngier <marc.zyngier@arm.com >>>> <mailto:marc.zyngier@arm.com>> wrote: >>>> >>>> On 09/02/16 09:01, Antoine Tenart wrote: >>>> > On Tue, Feb 09, 2016 at 09:56:33AM +0100, Antoine Tenart wrote: >>>> >> Hi Marc, >>>> >> >>>> >> On Mon, Feb 08, 2016 at 03:29:33PM +0000, Marc Zyngier wrote: >>>> >>> On 08/02/16 09:11, Antoine Tenart wrote: >>>> >>> >>>> >>>> + gic: gic@f0100000 { >>>> >>>> + compatible = "arm,gic-v3"; >>>> >>>> + reg = <0x0 0xf0200000 0x0 0x10000>, /* GIC Dist */ >>>> >>>> + <0x0 0xf0280000 0x0 0x200000>, /* GICR */ >>>> >>>> + <0x0 0xf0100000 0x0 0x2000>; /* GICC */ >>>> >>>> + interrupt-controller; >>>> >>>> + #interrupt-cells = <3>; >>>> >>>> + }; >>>> >>> >>>> >>> Something is wrong here. Either you are missing GICH and GICV (assuming >>>> >>> you have legacy support), or you have an extra GICC region (which >>>> >>> doesn't make sense on its own). >>>> >> >>>> >> I'll add the missing regions. >>>> > >>>> > Hmm, in fact the GICC region shouldn't be there. I'll make some tests >>>> > and remove it. >>>> >>>> If you have a GICv3 with legacy support, you will probably have GICC, >>>> GICH and GICV. Linux itself will only use GICD and GICR, but it needs at >>>> least GICV to be able to virtualize GICv2 guests. And GICV is not >>>> allowed to exist without GICC and GICH, so I really recommend that you >>>> keep GICC around. >>>> >>>> >>>> We use the GIC without legacy support (we disable it in early boot >>>> stages), so I think removing the GICC region is the better solution. >>> >>> Disabling legacy support doesn't mean that: >>> - the HW isn't present >>> - the associated regions are not useful >>> >> By "disabling lecgacy support in early boot" I don't just mean that >> ARE bit will be set, but it will actually be RAO/WI. There will be no >> way for SW to enable it and use these registers (which, sadly, means >> that there will be no way to enable gicv2 virtualization). If you >> insist - I will dig up the supposed location of GICV and GICH - yet it >> will be both untested and entirely unusable. > > Just to make sure you are not missing the point: ARE==1 does *not* mean > that GICV is unusable. Quite the opposite. It only makes it illegal to > use GICC and GICH, but leaves GICV usable for a guest. > > So the real question is: do you have any additional HW that would > actively prevent GICV from being used? If the answer to that is "no", > and assuming your GICv3 implementation is compliant with the > architecture, then GICV will be usable, and you should document all 3 > regions. > O.K. will add to next version. > Thanks, > > M. > -- > Jazz is not dead. It just smells funny...
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index f832b8a7453a..fd80617a9c6f 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -1,3 +1,4 @@ +dts-dirs += al dts-dirs += altera dts-dirs += amd dts-dirs += apm diff --git a/arch/arm64/boot/dts/al/Makefile b/arch/arm64/boot/dts/al/Makefile new file mode 100644 index 000000000000..8a6cde4f9b23 --- /dev/null +++ b/arch/arm64/boot/dts/al/Makefile @@ -0,0 +1,5 @@ +dtb-$(CONFIG_ARCH_ALPINE) += alpine-v2-evp.dtb + +always := $(dtb-y) +subdir-y := $(dts-dirs) +clean-files := *.dtb diff --git a/arch/arm64/boot/dts/al/alpine-v2-evp.dts b/arch/arm64/boot/dts/al/alpine-v2-evp.dts new file mode 100644 index 000000000000..3e3080fa45e4 --- /dev/null +++ b/arch/arm64/boot/dts/al/alpine-v2-evp.dts @@ -0,0 +1,46 @@ +/* + * Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Antoine Tenart <antoine.tenart@free-electrons.com> + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the + * BSD license below: + * + * Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * - Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * + * - Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "alpine-v2.dtsi" + +/ { + model = "Annapurna Labs Alpine v2 EVP"; + compatible = "al,alpine-v2-evp", "al,alpine-v2"; + + chosen { + stdout-path = "console0:115200n8"; + }; +}; + +&uart0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/al/alpine-v2.dtsi b/arch/arm64/boot/dts/al/alpine-v2.dtsi new file mode 100644 index 000000000000..eb7a03b71456 --- /dev/null +++ b/arch/arm64/boot/dts/al/alpine-v2.dtsi @@ -0,0 +1,221 @@ +/* + * Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Antoine Tenart <antoine.tenart@free-electrons.com> + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the + * BSD license below: + * + * Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * - Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * + * - Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/dts-v1/; + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + model = "Annapurna Labs Alpine v2"; + compatible = "al,alpine-v2"; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a57", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x0>; + enable-method = "psci"; + }; + + cpu@1 { + compatible = "arm,cortex-a57", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x1>; + enable-method = "psci"; + }; + + cpu@2 { + compatible = "arm,cortex-a57", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x2>; + enable-method = "psci"; + }; + + cpu@3 { + compatible = "arm,cortex-a57", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x3>; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-0.2", "arm,psci"; + method = "smc"; + cpu_on = <0x84000003>; + }; + + sbclk: sbclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + + interrupt-parent = <&gic>; + ranges; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 0xd 0xff08>, + <GIC_PPI 0xe 0xff08>, + <GIC_PPI 0xb 0xff08>, + <GIC_PPI 0xa 0xff08>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + }; + + gic: gic@f0100000 { + compatible = "arm,gic-v3"; + reg = <0x0 0xf0200000 0x0 0x10000>, /* GIC Dist */ + <0x0 0xf0280000 0x0 0x200000>, /* GICR */ + <0x0 0xf0100000 0x0 0x2000>; /* GICC */ + interrupt-controller; + #interrupt-cells = <3>; + }; + + pcie-internal@0xfbc00000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + #size-cells = <2>; + #address-cells = <3>; + #interrupt-cells = <1>; + reg = <0x0 0xfbc00000 0x0 0x100000>; + interrupt-map-mask = <0xf800 0 0 7>; + /* add legacy interrupts for SATA only */ + interrupt-map = <0x4000 0 0 1 &gic 0 53 4>, + <0x4800 0 0 1 &gic 0 54 4>; + /* 32 bit non prefetchable memory space */ + ranges = <0x2000000 0x0 0xfe000000 0x0 0xfe000000 0x0 0x1000000>; + bus-range = <0x00 0x00>; + }; + + uart0: uart@fd883000 { + compatible = "ns16550a"; + device_type = "serial"; + reg = <0x0 0xfd883000 0x0 0x1000>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <500000000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart1: uart@fd884000 { + compatible = "ns16550a"; + device_type = "serial"; + reg = <0x0 0xfd884000 0x0 0x1000>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <500000000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart2: uart@fd885000 { + compatible = "ns16550a"; + device_type = "serial"; + reg = <0x0 0xfd885000 0x0 0x1000>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <500000000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart3: uart@fd886000 { + compatible = "ns16550a"; + device_type = "serial"; + reg = <0x0 0xfd886000 0x0 0x1000>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <500000000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + timer0: timer@fd890000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x0 0xfd890000 0x0 0x1000>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sbclk>; + }; + + timer1: timer@fd891000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x0 0xfd891000 0x0 0x1000>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sbclk>; + status = "disabled"; + }; + + timer2: timer@fd892000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x0 0xfd892000 0x0 0x1000>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sbclk>; + status = "disabled"; + }; + + timer3: timer@fd893000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x0 0xfd893000 0x0 0x1000>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sbclk>; + status = "disabled"; + }; + }; +};