| Message ID | 1458974276-10325-3-git-send-email-zhengxing@rock-chips.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi Xing, Am Samstag, 26. März 2016, 14:37:54 schrieb Xing Zheng: > Add devicetree bindings for Rockchip cru which found on > Rockchip SoCs. > > Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> > Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> > Acked-by: Rob Herring <robh@kernel.org> > --- > > Changes in v5: None > Changes in v3: None > Changes in v2: None > > .../bindings/clock/rockchip,rk3399-cru.txt | 83 > ++++++++++++++++++++ 1 file changed, 83 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt > > diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3399- cru.txt > b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt new file > mode 100644 > index 0000000..9427caa > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt > @@ -0,0 +1,83 @@ > +* Rockchip RK3399 Clock and Reset Unit > + > +The RK3399 clock controller generates and supplies clock to various > +controllers within the SoC and also implements a reset controller for SoC > +peripherals. > + > +Required Properties: > + > +- compatible: PMU for CRU should be "rockchip,rk3399-pmucru" > +- compatible: CRU should be "rockchip,rk3399-cru" > +- reg: physical base address of the controller and length of memory mapped > + region. > +- #clock-cells: should be 1. > +- #reset-cells: should be 1. > + > +Optional Properties: > + > +- rockchip,grf: phandle to the syscon managing the "general register files" > + If missing, pll rates are not changeable, due to the missing pll lock > status. + the rk3399 doesn't need the GRF, so we should drop this block for now > +Each clock is assigned an identifier and client nodes can use this > identifier +to specify the clock which they consume. All available clocks > are defined as +preprocessor macros in the dt-bindings/clock/rk3399-cru.h > headers and can be +used in device tree sources. Similar macros exist for > the reset sources in +these files. > + > +External clocks: > + > +There are several clocks that are generated outside the SoC. It is expected > +that they are defined using standard clock bindings with following > +clock-output-names: > + - "xin24m" - crystal input - required, > + - "xin32k" - rtc clock - optional, > + - "ext_i2s" - external I2S clock - optional, > + - "ext_gmac" - external GMAC clock - optional > + - "ext_hsadc" - external HSADC clock - optional, > + - "ext_isp" - external ISP clock - optional, > + - "ext_jtag" - external JTAG clock - optional > + - "ext_vip" - external VIP clock - optional, > + - "usbotg_out" - output clock of the pll in the otg phy external clock listing needs adjusting, something like - clkin_i2s - clkin_gmac --> remove ext_hsadc - clkin_cif --> remove ext_jtag --> remove ext_vip - clk_usbphy0_480m - clk_usbphy0_480m maybe? > + > +Example: General Register Files > + > + pmugrf: syscon@ff320000 { > + compatible = "rockchip,rk3399-pmugrf", "syscon"; > + reg = <0x0 0xff320000 0x0 0x1000>; > + }; > + > + grf: syscon@ff770000 { > + compatible = "rockchip,rk3399-grf", "syscon"; > + reg = <0x0 0xff770000 0x0 0x10000>; > + }; > + > +Example: Clock controller node: > + > + pmucru: pmu-clock-controller@ff750000 { > + compatible = "rockchip,rk3399-pmucru"; > + reg = <0x0 0xff750000 0x0 0x1000>; > + rockchip,grf = <&pmugrf>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; > + > + cru: clock-controller@ff760000 { > + compatible = "rockchip,rk3399-cru"; > + reg = <0x0 0xff760000 0x0 0x1000>; > + rockchip,grf = <&grf>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; also here drop grf nodes and rockchip,grf properties? > + > +Example: UART controller node that consumes the clock generated by the > clock + controller: > + > + uart0: serial@ff1a0000 { > + compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; > + reg = <0x0 0xff180000 0x0 0x100>; > + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; > + clock-names = "baudclk", "apb_pclk"; > + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; > + reg-shift = <2>; > + reg-io-width = <4>; > + };
Hi Xing, Am Montag, 28. März 2016, 01:52:12 schrieb Heiko Stübner: > Am Samstag, 26. März 2016, 14:37:54 schrieb Xing Zheng: > > Add devicetree bindings for Rockchip cru which found on > > Rockchip SoCs. > > > > Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> > > Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> > > Acked-by: Rob Herring <robh@kernel.org> > > --- > > > > Changes in v5: None > > Changes in v3: None > > Changes in v2: None > > > > .../bindings/clock/rockchip,rk3399-cru.txt | 83 > > > > ++++++++++++++++++++ 1 file changed, 83 insertions(+) > > > > create mode 100644 > > > > Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt > > > > diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3399- > > cru.txt > > > b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt new > > file mode 100644 > > index 0000000..9427caa > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt > > @@ -0,0 +1,83 @@ > > +* Rockchip RK3399 Clock and Reset Unit > > + > > +The RK3399 clock controller generates and supplies clock to various > > +controllers within the SoC and also implements a reset controller for > > SoC +peripherals. > > + > > +Required Properties: > > + > > +- compatible: PMU for CRU should be "rockchip,rk3399-pmucru" > > +- compatible: CRU should be "rockchip,rk3399-cru" > > +- reg: physical base address of the controller and length of memory > > mapped > > > + region. > > +- #clock-cells: should be 1. > > +- #reset-cells: should be 1. > > + > > +Optional Properties: > > + > > +- rockchip,grf: phandle to the syscon managing the "general register > > files" > > > + If missing, pll rates are not changeable, due to the missing pll lock > > status. + > > the rk3399 doesn't need the GRF, so we should drop this block for now actually, I just saw that the GRF is needed for the static settings during init. So the rockchip,grf should stay but also move up to required properties? Same for the grf-comment in the examples-section. Heiko > > > +Each clock is assigned an identifier and client nodes can use this > > identifier +to specify the clock which they consume. All available > > clocks > > are defined as +preprocessor macros in the > > dt-bindings/clock/rk3399-cru.h > > headers and can be +used in device tree sources. Similar macros exist > > for > > the reset sources in +these files. > > + > > +External clocks: > > + > > +There are several clocks that are generated outside the SoC. It is > > expected > > > +that they are defined using standard clock bindings with following > > +clock-output-names: > > + - "xin24m" - crystal input - required, > > + - "xin32k" - rtc clock - optional, > > + - "ext_i2s" - external I2S clock - optional, > > + - "ext_gmac" - external GMAC clock - optional > > + - "ext_hsadc" - external HSADC clock - optional, > > + - "ext_isp" - external ISP clock - optional, > > + - "ext_jtag" - external JTAG clock - optional > > + - "ext_vip" - external VIP clock - optional, > > + - "usbotg_out" - output clock of the pll in the otg phy > > external clock listing needs adjusting, something like > > - clkin_i2s > - clkin_gmac > --> remove ext_hsadc > - clkin_cif > --> remove ext_jtag > --> remove ext_vip > - clk_usbphy0_480m > - clk_usbphy0_480m > > maybe? > > > + > > +Example: General Register Files > > + > > + pmugrf: syscon@ff320000 { > > + compatible = "rockchip,rk3399-pmugrf", "syscon"; > > + reg = <0x0 0xff320000 0x0 0x1000>; > > + }; > > + > > + grf: syscon@ff770000 { > > + compatible = "rockchip,rk3399-grf", "syscon"; > > + reg = <0x0 0xff770000 0x0 0x10000>; > > + }; > > + > > +Example: Clock controller node: > > + > > + pmucru: pmu-clock-controller@ff750000 { > > + compatible = "rockchip,rk3399-pmucru"; > > + reg = <0x0 0xff750000 0x0 0x1000>; > > + rockchip,grf = <&pmugrf>; > > + #clock-cells = <1>; > > + #reset-cells = <1>; > > + }; > > + > > + cru: clock-controller@ff760000 { > > + compatible = "rockchip,rk3399-cru"; > > + reg = <0x0 0xff760000 0x0 0x1000>; > > + rockchip,grf = <&grf>; > > + #clock-cells = <1>; > > + #reset-cells = <1>; > > + }; > > also here drop grf nodes and rockchip,grf properties? > > > + > > +Example: UART controller node that consumes the clock generated by the > > clock + controller: > > + > > + uart0: serial@ff1a0000 { > > + compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; > > + reg = <0x0 0xff180000 0x0 0x100>; > > + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; > > + clock-names = "baudclk", "apb_pclk"; > > + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; > > + reg-shift = <2>; > > + reg-io-width = <4>; > > + };
Hi Heiko, On 2016?03?28? 07:52, Heiko Stübner wrote: > Hi Xing, > > Am Samstag, 26. März 2016, 14:37:54 schrieb Xing Zheng: >> Add devicetree bindings for Rockchip cru which found on >> Rockchip SoCs. >> >> Signed-off-by: Xing Zheng<zhengxing@rock-chips.com> >> Signed-off-by: Jianqun Xu<jay.xu@rock-chips.com> >> Acked-by: Rob Herring<robh@kernel.org> >> --- >> >> Changes in v5: None >> Changes in v3: None >> Changes in v2: None >> >> .../bindings/clock/rockchip,rk3399-cru.txt | 83 >> ++++++++++++++++++++ 1 file changed, 83 insertions(+) >> create mode 100644 >> Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt >> >> diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3399- > cru.txt >> b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt new file >> mode 100644 >> index 0000000..9427caa >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt >> @@ -0,0 +1,83 @@ >> +* Rockchip RK3399 Clock and Reset Unit >> + >> +The RK3399 clock controller generates and supplies clock to various >> +controllers within the SoC and also implements a reset controller for SoC >> +peripherals. >> + >> +Required Properties: >> + >> +- compatible: PMU for CRU should be "rockchip,rk3399-pmucru" >> +- compatible: CRU should be "rockchip,rk3399-cru" >> +- reg: physical base address of the controller and length of memory > mapped >> + region. >> +- #clock-cells: should be 1. >> +- #reset-cells: should be 1. >> + >> +Optional Properties: >> + >> +- rockchip,grf: phandle to the syscon managing the "general register > files" >> + If missing, pll rates are not changeable, due to the missing pll lock >> status. + > the rk3399 doesn't need the GRF, so we should drop this block for now > >> +Each clock is assigned an identifier and client nodes can use this >> identifier +to specify the clock which they consume. All available clocks >> are defined as +preprocessor macros in the dt-bindings/clock/rk3399-cru.h >> headers and can be +used in device tree sources. Similar macros exist for >> the reset sources in +these files. >> + >> +External clocks: >> + >> +There are several clocks that are generated outside the SoC. It is > expected >> +that they are defined using standard clock bindings with following >> +clock-output-names: >> + - "xin24m" - crystal input - required, >> + - "xin32k" - rtc clock - optional, >> + - "ext_i2s" - external I2S clock - optional, >> + - "ext_gmac" - external GMAC clock - optional >> + - "ext_hsadc" - external HSADC clock - optional, >> + - "ext_isp" - external ISP clock - optional, >> + - "ext_jtag" - external JTAG clock - optional >> + - "ext_vip" - external VIP clock - optional, >> + - "usbotg_out" - output clock of the pll in the otg phy > external clock listing needs adjusting, something like > > - clkin_i2s > - clkin_gmac > --> remove ext_hsadc > - clkin_cif > --> remove ext_jtag > --> remove ext_vip > - clk_usbphy0_480m > - clk_usbphy0_480m > > maybe? Thanks, now they like this: clock-output-names: - "xin24m" - crystal input - required, - "xin32k" - rtc clock - optional, - "clkin_gmac" - external GMAC clock - optional, - "gmac_phy_rx_clk" - external GMAC RX clock - optional, - "clkin_i2s" - external I2S clock - optional, - "pclkin_cif" - external ISP clock - optional, - "clk_usbphy0_480m" - output clock of the pll in the usbphy0 - "clk_usbphy1_480m" - output clock of the pll in the usbphy1 > >> + >> +Example: General Register Files >> + >> + pmugrf: syscon@ff320000 { >> + compatible = "rockchip,rk3399-pmugrf", "syscon"; >> + reg =<0x0 0xff320000 0x0 0x1000>; >> + }; >> + >> + grf: syscon@ff770000 { >> + compatible = "rockchip,rk3399-grf", "syscon"; >> + reg =<0x0 0xff770000 0x0 0x10000>; >> + }; >> + >> +Example: Clock controller node: >> + >> + pmucru: pmu-clock-controller@ff750000 { >> + compatible = "rockchip,rk3399-pmucru"; >> + reg =<0x0 0xff750000 0x0 0x1000>; >> + rockchip,grf =<&pmugrf>; >> + #clock-cells =<1>; >> + #reset-cells =<1>; >> + }; >> + >> + cru: clock-controller@ff760000 { >> + compatible = "rockchip,rk3399-cru"; >> + reg =<0x0 0xff760000 0x0 0x1000>; >> + rockchip,grf =<&grf>; >> + #clock-cells =<1>; >> + #reset-cells =<1>; >> + }; > also here drop grf nodes and rockchip,grf properties? Done. > > >> + >> +Example: UART controller node that consumes the clock generated by the >> clock + controller: >> + >> + uart0: serial@ff1a0000 { >> + compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; >> + reg =<0x0 0xff180000 0x0 0x100>; >> + clocks =<&cru SCLK_UART0>,<&cru PCLK_UART0>; >> + clock-names = "baudclk", "apb_pclk"; >> + interrupts =<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; >> + reg-shift =<2>; >> + reg-io-width =<4>; >> + }; > > Thanks.
Hi Heiko, On 2016?03?28? 08:07, Heiko Stuebner wrote: > Hi Xing, > > Am Montag, 28. März 2016, 01:52:12 schrieb Heiko Stübner: >> Am Samstag, 26. März 2016, 14:37:54 schrieb Xing Zheng: >>> Add devicetree bindings for Rockchip cru which found on >>> Rockchip SoCs. >>> >>> Signed-off-by: Xing Zheng<zhengxing@rock-chips.com> >>> Signed-off-by: Jianqun Xu<jay.xu@rock-chips.com> >>> Acked-by: Rob Herring<robh@kernel.org> >>> --- >>> >>> Changes in v5: None >>> Changes in v3: None >>> Changes in v2: None >>> >>> .../bindings/clock/rockchip,rk3399-cru.txt | 83 >>> >>> ++++++++++++++++++++ 1 file changed, 83 insertions(+) >>> >>> create mode 100644 >>> >>> Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt >>> >>> diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3399- >> cru.txt >> >>> b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt new >>> file mode 100644 >>> index 0000000..9427caa >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt >>> @@ -0,0 +1,83 @@ >>> +* Rockchip RK3399 Clock and Reset Unit >>> + >>> +The RK3399 clock controller generates and supplies clock to various >>> +controllers within the SoC and also implements a reset controller for >>> SoC +peripherals. >>> + >>> +Required Properties: >>> + >>> +- compatible: PMU for CRU should be "rockchip,rk3399-pmucru" >>> +- compatible: CRU should be "rockchip,rk3399-cru" >>> +- reg: physical base address of the controller and length of memory >> mapped >> >>> + region. >>> +- #clock-cells: should be 1. >>> +- #reset-cells: should be 1. >>> + >>> +Optional Properties: >>> + >>> +- rockchip,grf: phandle to the syscon managing the "general register >> files" >> >>> + If missing, pll rates are not changeable, due to the missing pll lock >>> status. + >> the rk3399 doesn't need the GRF, so we should drop this block for now > actually, I just saw that the GRF is needed for the static settings during > init. So the rockchip,grf should stay but also move up to required > properties? > > Same for the grf-comment in the examples-section. > > I check the setting of the pclk_alive and pclk_pmu_src are not gating default on the PMUGRF_SOC_CON0, so I think that we don't need to do the static settings to re-enable them in the clock driver any more. Thanks.
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt new file mode 100644 index 0000000..9427caa --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt @@ -0,0 +1,83 @@ +* Rockchip RK3399 Clock and Reset Unit + +The RK3399 clock controller generates and supplies clock to various +controllers within the SoC and also implements a reset controller for SoC +peripherals. + +Required Properties: + +- compatible: PMU for CRU should be "rockchip,rk3399-pmucru" +- compatible: CRU should be "rockchip,rk3399-cru" +- reg: physical base address of the controller and length of memory mapped + region. +- #clock-cells: should be 1. +- #reset-cells: should be 1. + +Optional Properties: + +- rockchip,grf: phandle to the syscon managing the "general register files" + If missing, pll rates are not changeable, due to the missing pll lock status. + +Each clock is assigned an identifier and client nodes can use this identifier +to specify the clock which they consume. All available clocks are defined as +preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be +used in device tree sources. Similar macros exist for the reset sources in +these files. + +External clocks: + +There are several clocks that are generated outside the SoC. It is expected +that they are defined using standard clock bindings with following +clock-output-names: + - "xin24m" - crystal input - required, + - "xin32k" - rtc clock - optional, + - "ext_i2s" - external I2S clock - optional, + - "ext_gmac" - external GMAC clock - optional + - "ext_hsadc" - external HSADC clock - optional, + - "ext_isp" - external ISP clock - optional, + - "ext_jtag" - external JTAG clock - optional + - "ext_vip" - external VIP clock - optional, + - "usbotg_out" - output clock of the pll in the otg phy + +Example: General Register Files + + pmugrf: syscon@ff320000 { + compatible = "rockchip,rk3399-pmugrf", "syscon"; + reg = <0x0 0xff320000 0x0 0x1000>; + }; + + grf: syscon@ff770000 { + compatible = "rockchip,rk3399-grf", "syscon"; + reg = <0x0 0xff770000 0x0 0x10000>; + }; + +Example: Clock controller node: + + pmucru: pmu-clock-controller@ff750000 { + compatible = "rockchip,rk3399-pmucru"; + reg = <0x0 0xff750000 0x0 0x1000>; + rockchip,grf = <&pmugrf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + cru: clock-controller@ff760000 { + compatible = "rockchip,rk3399-cru"; + reg = <0x0 0xff760000 0x0 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + +Example: UART controller node that consumes the clock generated by the clock + controller: + + uart0: serial@ff1a0000 { + compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff180000 0x0 0x100>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + };