| Message ID | 1458542560-24242-1-git-send-email-vandana.kannan@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Mon, 21 Mar 2016, Vandana Kannan <vandana.kannan@intel.com> wrote: > According to the BSpec update, bit 7 of PORT_CL1CM_DW0 register needs to be > checked to ensure that the register is in accessible state. *sigh* the bspec is still not updated, and I didn't get the BUN. > Also, based on a BSpec update, changing the timeout value to > check iphypwrgood, from 10ms to wait for up to 100us. > > Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> > Reported-by: Philippe Lecluse <Philippe.Lecluse@intel.com> > Cc: Deak, Imre <imre.deak@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_ddi.c | 11 +++++++++-- > 2 files changed, 10 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 7dfc400..9a02bfc 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1318,6 +1318,7 @@ enum skl_disp_power_wells { > #define _PORT_CL1CM_DW0_A 0x162000 > #define _PORT_CL1CM_DW0_BC 0x6C000 > #define PHY_POWER_GOOD (1 << 16) > +#define PHY_RESERVED (1 << 7) > #define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC, \ > _PORT_CL1CM_DW0_A) > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c > index 62de9f4..354f949 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -2669,9 +2669,16 @@ static void broxton_phy_init(struct drm_i915_private *dev_priv, > val |= GT_DISPLAY_POWER_ON(phy); > I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); > > - /* Considering 10ms timeout until BSpec is updated */ > - if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10)) > + /* > + * HW team confirmed that the time to reach phypowergood status is > + * anywhere between 50 us and 100us. > + */ > + if (wait_for_atomic_us(((!(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & > + PHY_RESERVED)) && > + ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) & > + PHY_POWER_GOOD) == PHY_POWER_GOOD)), 100)) { Is there any reason why you'd need to do the read twice? Why not just write it as: (I915_READ(BXT_PORT_CL1CM_DW0(phy)) & (PHY_RESERVED | PHY_POWER_GOOD)) == PHY_POWER_GOOD BR, Jani. > DRM_ERROR("timeout during PHY%d power on\n", phy); > + } > > for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A); > port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) {
On Mon, Mar 21, 2016 at 12:12:40PM +0530, Vandana Kannan wrote: > According to the BSpec update, bit 7 of PORT_CL1CM_DW0 register needs to be > checked to ensure that the register is in accessible state. > Also, based on a BSpec update, changing the timeout value to > check iphypwrgood, from 10ms to wait for up to 100us. > > Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> > Reported-by: Philippe Lecluse <Philippe.Lecluse@intel.com> > Cc: Deak, Imre <imre.deak@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_ddi.c | 11 +++++++++-- > 2 files changed, 10 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 7dfc400..9a02bfc 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1318,6 +1318,7 @@ enum skl_disp_power_wells { > #define _PORT_CL1CM_DW0_A 0x162000 > #define _PORT_CL1CM_DW0_BC 0x6C000 > #define PHY_POWER_GOOD (1 << 16) > +#define PHY_RESERVED (1 << 7) > #define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC, \ > _PORT_CL1CM_DW0_A) > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c > index 62de9f4..354f949 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -2669,9 +2669,16 @@ static void broxton_phy_init(struct drm_i915_private *dev_priv, > val |= GT_DISPLAY_POWER_ON(phy); > I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); > > - /* Considering 10ms timeout until BSpec is updated */ > - if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10)) > + /* > + * HW team confirmed that the time to reach phypowergood status is > + * anywhere between 50 us and 100us. > + */ > + if (wait_for_atomic_us(((!(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & Switching to atomic wait seems silly. > + PHY_RESERVED)) && > + ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) & > + PHY_POWER_GOOD) == PHY_POWER_GOOD)), 100)) { > DRM_ERROR("timeout during PHY%d power on\n", phy); > + } > > for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A); > port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) { > -- > 1.9.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Mon, 21 Mar 2016, Jani Nikula <jani.nikula@linux.intel.com> wrote: > [ text/plain ] > On Mon, 21 Mar 2016, Vandana Kannan <vandana.kannan@intel.com> wrote: >> According to the BSpec update, bit 7 of PORT_CL1CM_DW0 register needs to be >> checked to ensure that the register is in accessible state. > > *sigh* the bspec is still not updated, and I didn't get the BUN. > >> Also, based on a BSpec update, changing the timeout value to >> check iphypwrgood, from 10ms to wait for up to 100us. >> >> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> >> Reported-by: Philippe Lecluse <Philippe.Lecluse@intel.com> >> Cc: Deak, Imre <imre.deak@intel.com> >> --- >> drivers/gpu/drm/i915/i915_reg.h | 1 + >> drivers/gpu/drm/i915/intel_ddi.c | 11 +++++++++-- >> 2 files changed, 10 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h >> index 7dfc400..9a02bfc 100644 >> --- a/drivers/gpu/drm/i915/i915_reg.h >> +++ b/drivers/gpu/drm/i915/i915_reg.h >> @@ -1318,6 +1318,7 @@ enum skl_disp_power_wells { >> #define _PORT_CL1CM_DW0_A 0x162000 >> #define _PORT_CL1CM_DW0_BC 0x6C000 >> #define PHY_POWER_GOOD (1 << 16) >> +#define PHY_RESERVED (1 << 7) >> #define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC, \ >> _PORT_CL1CM_DW0_A) >> >> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c >> index 62de9f4..354f949 100644 >> --- a/drivers/gpu/drm/i915/intel_ddi.c >> +++ b/drivers/gpu/drm/i915/intel_ddi.c >> @@ -2669,9 +2669,16 @@ static void broxton_phy_init(struct drm_i915_private *dev_priv, >> val |= GT_DISPLAY_POWER_ON(phy); >> I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); >> >> - /* Considering 10ms timeout until BSpec is updated */ >> - if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10)) >> + /* >> + * HW team confirmed that the time to reach phypowergood status is >> + * anywhere between 50 us and 100us. >> + */ Interesting, the spec section (now that I found it, thanks again!) says, "recommended poll time interval = 100 us". Interval, not timeout. >> + if (wait_for_atomic_us(((!(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & >> + PHY_RESERVED)) && >> + ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) & >> + PHY_POWER_GOOD) == PHY_POWER_GOOD)), 100)) { > > Is there any reason why you'd need to do the read twice? Why not just > write it as: > > (I915_READ(BXT_PORT_CL1CM_DW0(phy)) & (PHY_RESERVED | PHY_POWER_GOOD)) == PHY_POWER_GOOD AFAICT this should be fine. BR, Jani. > > BR, > Jani. > >> DRM_ERROR("timeout during PHY%d power on\n", phy); >> + } >> >> for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A); >> port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) {
> -----Original Message----- > From: Ville Syrjälä [mailto:ville.syrjala@linux.intel.com] > Sent: Monday, March 21, 2016 7:34 PM > To: Kannan, Vandana <vandana.kannan@intel.com> > Cc: intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH] drm/i915: BXT DDI PHY sequence BUN > > On Mon, Mar 21, 2016 at 12:12:40PM +0530, Vandana Kannan wrote: > > According to the BSpec update, bit 7 of PORT_CL1CM_DW0 register > needs > > to be checked to ensure that the register is in accessible state. > > Also, based on a BSpec update, changing the timeout value to check > > iphypwrgood, from 10ms to wait for up to 100us. > > > > Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> > > Reported-by: Philippe Lecluse <Philippe.Lecluse@intel.com> > > Cc: Deak, Imre <imre.deak@intel.com> > > --- > > drivers/gpu/drm/i915/i915_reg.h | 1 + > > drivers/gpu/drm/i915/intel_ddi.c | 11 +++++++++-- > > 2 files changed, 10 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > b/drivers/gpu/drm/i915/i915_reg.h index 7dfc400..9a02bfc 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -1318,6 +1318,7 @@ enum skl_disp_power_wells { > > #define _PORT_CL1CM_DW0_A 0x162000 > > #define _PORT_CL1CM_DW0_BC 0x6C000 > > #define PHY_POWER_GOOD (1 << 16) > > +#define PHY_RESERVED (1 << 7) > > #define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), > _PORT_CL1CM_DW0_BC, \ > > _PORT_CL1CM_DW0_A) > > > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c > > b/drivers/gpu/drm/i915/intel_ddi.c > > index 62de9f4..354f949 100644 > > --- a/drivers/gpu/drm/i915/intel_ddi.c > > +++ b/drivers/gpu/drm/i915/intel_ddi.c > > @@ -2669,9 +2669,16 @@ static void broxton_phy_init(struct > drm_i915_private *dev_priv, > > val |= GT_DISPLAY_POWER_ON(phy); > > I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); > > > > - /* Considering 10ms timeout until BSpec is updated */ > > - if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & > PHY_POWER_GOOD, 10)) > > + /* > > + * HW team confirmed that the time to reach phypowergood status > is > > + * anywhere between 50 us and 100us. > > + */ > > + if (wait_for_atomic_us(((!(I915_READ(BXT_PORT_CL1CM_DW0(phy)) > & > > Switching to atomic wait seems silly. > [Vandana] You think wait_for_us should suffice here? > > + PHY_RESERVED)) && > > + ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) & > > + PHY_POWER_GOOD) == > PHY_POWER_GOOD)), 100)) { > > DRM_ERROR("timeout during PHY%d power on\n", phy); > > + } > > > > for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A); > > port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) { > > -- > > 1.9.1 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Ville Syrjälä > Intel OTC
On ke, 2016-03-23 at 04:43 +0000, Kannan, Vandana wrote: > > -----Original Message----- > > From: Ville Syrjälä [mailto:ville.syrjala@linux.intel.com] > > Sent: Monday, March 21, 2016 7:34 PM > > To: Kannan, Vandana <vandana.kannan@intel.com> > > Cc: intel-gfx@lists.freedesktop.org > > Subject: Re: [Intel-gfx] [PATCH] drm/i915: BXT DDI PHY sequence BUN > > > > On Mon, Mar 21, 2016 at 12:12:40PM +0530, Vandana Kannan wrote: > > > According to the BSpec update, bit 7 of PORT_CL1CM_DW0 register > > needs > > > to be checked to ensure that the register is in accessible state. > > > Also, based on a BSpec update, changing the timeout value to check > > > iphypwrgood, from 10ms to wait for up to 100us. > > > > > > Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> > > > Reported-by: Philippe Lecluse <Philippe.Lecluse@intel.com> > > > Cc: Deak, Imre <imre.deak@intel.com> > > > --- > > > drivers/gpu/drm/i915/i915_reg.h | 1 + > > > drivers/gpu/drm/i915/intel_ddi.c | 11 +++++++++-- > > > 2 files changed, 10 insertions(+), 2 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > > b/drivers/gpu/drm/i915/i915_reg.h index 7dfc400..9a02bfc 100644 > > > --- a/drivers/gpu/drm/i915/i915_reg.h > > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > > @@ -1318,6 +1318,7 @@ enum skl_disp_power_wells { > > > #define _PORT_CL1CM_DW0_A 0x162000 > > > #define _PORT_CL1CM_DW0_BC 0x6C000 > > > #define PHY_POWER_GOOD (1 << 16) > > > +#define PHY_RESERVED (1 << 7) > > > #define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), > > _PORT_CL1CM_DW0_BC, \ > > > _PORT_CL1CM_DW0_A) > > > > > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c > > > b/drivers/gpu/drm/i915/intel_ddi.c > > > index 62de9f4..354f949 100644 > > > --- a/drivers/gpu/drm/i915/intel_ddi.c > > > +++ b/drivers/gpu/drm/i915/intel_ddi.c > > > @@ -2669,9 +2669,16 @@ static void broxton_phy_init(struct > > drm_i915_private *dev_priv, > > > val |= GT_DISPLAY_POWER_ON(phy); > > > I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); > > > > > > - /* Considering 10ms timeout until BSpec is updated */ > > > - if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & > > PHY_POWER_GOOD, 10)) > > > + /* > > > + * HW team confirmed that the time to reach phypowergood status > > is > > > + * anywhere between 50 us and 100us. > > > + */ > > > + if (wait_for_atomic_us(((!(I915_READ(BXT_PORT_CL1CM_DW0(phy)) > > & > > > > Switching to atomic wait seems silly. > > > [Vandana] You think wait_for_us should suffice here? Yes. > > > + PHY_RESERVED)) && > > > + ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) & > > > + PHY_POWER_GOOD) == > > PHY_POWER_GOOD)), 100)) { > > > DRM_ERROR("timeout during PHY%d power on\n", phy); > > > + } Please also add a comment on how the detection magic works: Reading any PHY register while the PHY is powered down will result in all register bits set, while the reserved bit 7 is guaranteed to be 0 when the PHY is powered up. --Imre > > > > > > for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A); > > > port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) { > > > -- > > > 1.9.1 > > > > > > _______________________________________________ > > > Intel-gfx mailing list > > > Intel-gfx@lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > > -- > > Ville Syrjälä > > Intel OTC > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On ti, 2016-03-29 at 15:03 +0300, Imre Deak wrote: > On ke, 2016-03-23 at 04:43 +0000, Kannan, Vandana wrote: > > > -----Original Message----- > > > From: Ville Syrjälä [mailto:ville.syrjala@linux.intel.com] > > > Sent: Monday, March 21, 2016 7:34 PM > > > To: Kannan, Vandana <vandana.kannan@intel.com> > > > Cc: intel-gfx@lists.freedesktop.org > > > Subject: Re: [Intel-gfx] [PATCH] drm/i915: BXT DDI PHY sequence > > > BUN > > > > > > On Mon, Mar 21, 2016 at 12:12:40PM +0530, Vandana Kannan wrote: > > > > According to the BSpec update, bit 7 of PORT_CL1CM_DW0 register > > > needs > > > > to be checked to ensure that the register is in accessible > > > > state. > > > > Also, based on a BSpec update, changing the timeout value to > > > > check > > > > iphypwrgood, from 10ms to wait for up to 100us. > > > > > > > > Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> > > > > Reported-by: Philippe Lecluse <Philippe.Lecluse@intel.com> > > > > Cc: Deak, Imre <imre.deak@intel.com> > > > > --- > > > > drivers/gpu/drm/i915/i915_reg.h | 1 + > > > > drivers/gpu/drm/i915/intel_ddi.c | 11 +++++++++-- > > > > 2 files changed, 10 insertions(+), 2 deletions(-) > > > > > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > > > b/drivers/gpu/drm/i915/i915_reg.h index 7dfc400..9a02bfc 100644 > > > > --- a/drivers/gpu/drm/i915/i915_reg.h > > > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > > > @@ -1318,6 +1318,7 @@ enum skl_disp_power_wells { > > > > #define _PORT_CL1CM_DW0_A 0x162000 > > > > #define _PORT_CL1CM_DW0_BC 0x6C000 > > > > #define PHY_POWER_GOOD (1 << 16) > > > > +#define PHY_RESERVED (1 << 7) > > > > #define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), > > > _PORT_CL1CM_DW0_BC, \ > > > > _PORT_ > > > > CL1CM_DW0_A) > > > > > > > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c > > > > b/drivers/gpu/drm/i915/intel_ddi.c > > > > index 62de9f4..354f949 100644 > > > > --- a/drivers/gpu/drm/i915/intel_ddi.c > > > > +++ b/drivers/gpu/drm/i915/intel_ddi.c > > > > @@ -2669,9 +2669,16 @@ static void broxton_phy_init(struct > > > drm_i915_private *dev_priv, > > > > val |= GT_DISPLAY_POWER_ON(phy); > > > > I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); > > > > > > > > - /* Considering 10ms timeout until BSpec is updated */ > > > > - if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & > > > PHY_POWER_GOOD, 10)) > > > > + /* > > > > + * HW team confirmed that the time to reach > > > > phypowergood status > > > is > > > > + * anywhere between 50 us and 100us. > > > > + */ > > > > + if > > > > (wait_for_atomic_us(((!(I915_READ(BXT_PORT_CL1CM_DW0(phy)) > > > & > > > > > > Switching to atomic wait seems silly. > > > > > [Vandana] You think wait_for_us should suffice here? > > Yes. > > > > > + PHY_RESERVED)) && > > > > + ((I915_READ(BXT_PORT_CL1CM_DW0 > > > > (phy)) & > > > > + PHY_POWER_GOOD) == > > > PHY_POWER_GOOD)), 100)) { > > > > DRM_ERROR("timeout during PHY%d power on\n", > > > > phy); > > > > + } > > Please also add a comment on how the detection magic works: Reading > any > PHY register while the PHY is powered down will result in all > register > bits set, while the reserved bit 7 is guaranteed to be 0 when the PHY > is powered up. Vandana, could you resend this patch with the comments addressed? --Imre
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 7dfc400..9a02bfc 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1318,6 +1318,7 @@ enum skl_disp_power_wells { #define _PORT_CL1CM_DW0_A 0x162000 #define _PORT_CL1CM_DW0_BC 0x6C000 #define PHY_POWER_GOOD (1 << 16) +#define PHY_RESERVED (1 << 7) #define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC, \ _PORT_CL1CM_DW0_A) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 62de9f4..354f949 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -2669,9 +2669,16 @@ static void broxton_phy_init(struct drm_i915_private *dev_priv, val |= GT_DISPLAY_POWER_ON(phy); I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); - /* Considering 10ms timeout until BSpec is updated */ - if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10)) + /* + * HW team confirmed that the time to reach phypowergood status is + * anywhere between 50 us and 100us. + */ + if (wait_for_atomic_us(((!(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & + PHY_RESERVED)) && + ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) & + PHY_POWER_GOOD) == PHY_POWER_GOOD)), 100)) { DRM_ERROR("timeout during PHY%d power on\n", phy); + } for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A); port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) {
According to the BSpec update, bit 7 of PORT_CL1CM_DW0 register needs to be checked to ensure that the register is in accessible state. Also, based on a BSpec update, changing the timeout value to check iphypwrgood, from 10ms to wait for up to 100us. Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> Reported-by: Philippe Lecluse <Philippe.Lecluse@intel.com> Cc: Deak, Imre <imre.deak@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_ddi.c | 11 +++++++++-- 2 files changed, 10 insertions(+), 2 deletions(-)