| Message ID | 1461767754-12189-3-git-send-email-boris.brezillon@free-electrons.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, Apr 27, 2016 at 04:35:54PM +0200, Boris Brezillon wrote: > The EBI (External Bus Interface) is used to access external peripherals > (NOR, SRAM, NAND, and other specific devices like ethernet controllers). > Each device is assigned a CS line and an address range and can have its > own configuration (timings, access mode, bus width, ...). > This driver provides a generic DT binding to configure a device according > to its requirements. > For specific device controllers (like the NAND one) the SMC timings > should be configured by the controller driver through the matrix and smc > syscon regmaps. > > Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> > --- > .../bindings/memory-controllers/atmel,ebi.txt | 146 +++++++++++++++++++++ > 1 file changed, 146 insertions(+) > create mode 100644 Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt > > diff --git a/Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt b/Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt > new file mode 100644 > index 0000000..0f332d2 > --- /dev/null > +++ b/Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt > @@ -0,0 +1,146 @@ > +* Device tree bindings for Atmel EBI > + > +The External Bus Interface (EBI) controller is a bus where you can connect > +asynchronous (NAND, NOR, SRAM, ....) and synchronous memories (SDR/DDR SDRAMs). > +The EBI provides a glue-less interface to asynchronous memories though the SMC > +(Static Memory Controller). > +Synchronous memories (and some asynchronous memories like NANDs) can be > +attached to specialized controllers which are responsible for configuring the > +bus appropriately according to the connected device. > +In the other hand, the bus interface can be automated for simple asynchronous > +devices. > + > +Required properties: > + > +- compatible: "atmel,at91sam9260-ebi" > + "atmel,at91sam9261-ebi" > + "atmel,at91sam9263-ebi0" > + "atmel,at91sam9263-ebi1" > + "atmel,at91sam9rl-ebi" > + "atmel,at91sam9g45-ebi" > + "atmel,at91sam9x5-ebi" > + "atmel,sama5d3-ebi" > + > +- reg: Contains offset/length value for EBI memory mapping. > + This property might contain several entries if the EBI > + memory range is not contiguous > + > +- #address-cells: Must be 2. > + The first cell encodes the CS. > + The second cell encode the offset into the CS memory > + range. > + > +- #size-cells: Must be set to 1. > + > +- ranges: Encodes CS to memory region association. > + > +- clocks: Clock feeding the EBI controller. > + See clock-bindings.txt > + > +Child chip-select (cs) nodes contain the memory devices nodes connected to > +such as NOR (e.g. cfi-flash) and NAND. > +There might be board specific devices like FPGAs. > +You'll define you device requirements in these child nodes. > + > +Required child cs node properties: > + > +- #address-cells: Must be 2. > + > +- #size-cells: Must be 1. > + > +- ranges: Empty property indicating that child nodes can inherit > + memory layout. > + > +Optional child cs node properties: > +- atmel,bus-width: width of the asynchronous device's data bus > + 8, 16 or 32. > + 8 if not present. > + > +- atmel,byte-access-type "write" or "select" (see Atmel datasheet). > + "select" if not present. > + > +- atmel,read-mode "nrd" or "ncs". > + "ncs" is not present. > + > +- atmel,write-mode "nwe" or "ncs". > + "ncs" is not present. > + > +- atmel,exnw-mode "disabled", "frozen" or "ready". > + "disabled" if not present. > + > +- atmel,page-mode enable page mode if present. The provided value > + defines the page size (supported values: 4, 8, > + 16 and 32). > + > +Optional device timings expressed in nanoseconds (if the property is not > +present 0 is assumed): > + > +- atmel,ncs-rd-setup-ns > +- atmel,nrd-setup-ns > +- atmel,ncs-wr-setup-ns > +- atmel,nwe-setup-ns > +- atmel,ncs-rd-pulse-ns > +- atmel,nrd-pulse-ns > +- atmel,ncs-wr-pulse-ns > +- atmel,nwe-pulse-ns > +- atmel,nwe-cycle-ns > +- atmel,nrd-cycle-ns > +- atmel,tdf-ns I assume that these are defined in a datasheet. It may be worth noting "see datasheet" above this collection of properties. > + > +- atmel,tdf-mode: "normal" or "optimized". If set to "optimized" > + the data float time is optimized depending on > + the next device being accessed (next device > + setup time is subtracted to the current device > + data float time). > + > + > + > +Example: > + > + ebi: ebi@10000000 { > + compatible = "atmel,sama5d3-ebi", "simple-bus"; I don't believe that "simple-bus" should be here. > + #address-cells = <2>; > + #size-cells = <1>; > + atmel,smc = <&hsmc>; > + atmel,matrix = <&matrix>; > + reg = <0x10000000 0x10000000 > + 0x40000000 0x30000000>; > + ranges = <0x0 0x0 0x10000000 0x10000000 > + 0x1 0x0 0x40000000 0x10000000 > + 0x2 0x0 0x50000000 0x10000000 > + 0x3 0x0 0x60000000 0x10000000>; > + clocks = <&mck>; > + > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_ebi_addr>; > + > + cs@0 { I suspect recent DTC will warn here, as the unit-address should match the reg for the node (and no reg is defined). Here the reg would have to be two cells, which means we have to make up an address, no? We can either give the node a name without a unit-address (e.g. cs_0), or define some reg format. > + #address-cells = <2>; > + #size-cells = <1>; > + ranges; > + atmel,generic-dev; The cover letter mentioned this should go. > + atmel,read-mode = "nrd"; > + atmel,write-mode = "nwe"; > + atmel,bus-width = <16>; > + atmel,ncs-rd-setup-ns = <0>; > + atmel,ncs-wr-setup-ns = <0>; > + atmel,nwe-setup-ns = <8>; > + atmel,nrd-setup-ns = <16>; > + atmel,ncs-rd-pulse-ns = <84>; > + atmel,ncs-wr-pulse-ns = <84>; > + atmel,nrd-pulse-ns = <76>; > + atmel,nwe-pulse-ns = <76>; > + atmel,nrd-cycle-ns = <107>; > + atmel,nwe-cycle-ns = <84>; > + atmel,tdf-ns = <16>; > + > + nor: flash@0,0 { > + compatible = "cfi-flash"; > + #address-cells = <1>; > + #size-cells = <1>; > + reg = <0x0 0x0 0x1000000>; It feels odd that in the node for chipselect N, sub-devices have to encode the chipselect number in their reg, when it's obvious from their container. It may make more sense for the cs node to have a non-empty reg (or somehow to make that translation/truncation implicit). Thanks, Mark,
Hi Mark, On Wed, 27 Apr 2016 16:07:38 +0100 Mark Rutland <mark.rutland@arm.com> wrote: > On Wed, Apr 27, 2016 at 04:35:54PM +0200, Boris Brezillon wrote: > > The EBI (External Bus Interface) is used to access external peripherals > > (NOR, SRAM, NAND, and other specific devices like ethernet controllers). > > Each device is assigned a CS line and an address range and can have its > > own configuration (timings, access mode, bus width, ...). > > This driver provides a generic DT binding to configure a device according > > to its requirements. > > For specific device controllers (like the NAND one) the SMC timings > > should be configured by the controller driver through the matrix and smc > > syscon regmaps. > > > > Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> > > --- > > .../bindings/memory-controllers/atmel,ebi.txt | 146 +++++++++++++++++++++ > > 1 file changed, 146 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt > > > > diff --git a/Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt b/Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt > > new file mode 100644 > > index 0000000..0f332d2 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt > > @@ -0,0 +1,146 @@ > > +* Device tree bindings for Atmel EBI > > + > > +The External Bus Interface (EBI) controller is a bus where you can connect > > +asynchronous (NAND, NOR, SRAM, ....) and synchronous memories (SDR/DDR SDRAMs). > > +The EBI provides a glue-less interface to asynchronous memories though the SMC > > +(Static Memory Controller). > > +Synchronous memories (and some asynchronous memories like NANDs) can be > > +attached to specialized controllers which are responsible for configuring the > > +bus appropriately according to the connected device. > > +In the other hand, the bus interface can be automated for simple asynchronous > > +devices. > > + > > +Required properties: > > + > > +- compatible: "atmel,at91sam9260-ebi" > > + "atmel,at91sam9261-ebi" > > + "atmel,at91sam9263-ebi0" > > + "atmel,at91sam9263-ebi1" > > + "atmel,at91sam9rl-ebi" > > + "atmel,at91sam9g45-ebi" > > + "atmel,at91sam9x5-ebi" > > + "atmel,sama5d3-ebi" > > + > > +- reg: Contains offset/length value for EBI memory mapping. > > + This property might contain several entries if the EBI > > + memory range is not contiguous > > + > > +- #address-cells: Must be 2. > > + The first cell encodes the CS. > > + The second cell encode the offset into the CS memory > > + range. > > + > > +- #size-cells: Must be set to 1. > > + > > +- ranges: Encodes CS to memory region association. > > + > > +- clocks: Clock feeding the EBI controller. > > + See clock-bindings.txt > > + > > +Child chip-select (cs) nodes contain the memory devices nodes connected to > > +such as NOR (e.g. cfi-flash) and NAND. > > +There might be board specific devices like FPGAs. > > +You'll define you device requirements in these child nodes. > > + > > +Required child cs node properties: > > + > > +- #address-cells: Must be 2. > > + > > +- #size-cells: Must be 1. > > + > > +- ranges: Empty property indicating that child nodes can inherit > > + memory layout. > > + > > +Optional child cs node properties: > > +- atmel,bus-width: width of the asynchronous device's data bus > > + 8, 16 or 32. > > + 8 if not present. > > + > > +- atmel,byte-access-type "write" or "select" (see Atmel datasheet). > > + "select" if not present. > > + > > +- atmel,read-mode "nrd" or "ncs". > > + "ncs" is not present. > > + > > +- atmel,write-mode "nwe" or "ncs". > > + "ncs" is not present. > > + > > +- atmel,exnw-mode "disabled", "frozen" or "ready". > > + "disabled" if not present. > > + > > +- atmel,page-mode enable page mode if present. The provided value > > + defines the page size (supported values: 4, 8, > > + 16 and 32). > > + > > +Optional device timings expressed in nanoseconds (if the property is not > > +present 0 is assumed): > > + > > +- atmel,ncs-rd-setup-ns > > +- atmel,nrd-setup-ns > > +- atmel,ncs-wr-setup-ns > > +- atmel,nwe-setup-ns > > +- atmel,ncs-rd-pulse-ns > > +- atmel,nrd-pulse-ns > > +- atmel,ncs-wr-pulse-ns > > +- atmel,nwe-pulse-ns > > +- atmel,nwe-cycle-ns > > +- atmel,nrd-cycle-ns > > +- atmel,tdf-ns > > I assume that these are defined in a datasheet. It may be worth noting > "see datasheet" above this collection of properties. Yep. > > > + > > +- atmel,tdf-mode: "normal" or "optimized". If set to "optimized" > > + the data float time is optimized depending on > > + the next device being accessed (next device > > + setup time is subtracted to the current device > > + data float time). > > + > > + > > + > > +Example: > > + > > + ebi: ebi@10000000 { > > + compatible = "atmel,sama5d3-ebi", "simple-bus"; > > I don't believe that "simple-bus" should be here. > > > + #address-cells = <2>; > > + #size-cells = <1>; > > + atmel,smc = <&hsmc>; > > + atmel,matrix = <&matrix>; > > + reg = <0x10000000 0x10000000 > > + 0x40000000 0x30000000>; > > + ranges = <0x0 0x0 0x10000000 0x10000000 > > + 0x1 0x0 0x40000000 0x10000000 > > + 0x2 0x0 0x50000000 0x10000000 > > + 0x3 0x0 0x60000000 0x10000000>; > > + clocks = <&mck>; > > + > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_ebi_addr>; > > + > > + cs@0 { > > I suspect recent DTC will warn here, as the unit-address should match > the reg for the node (and no reg is defined). Here the reg would have to > be two cells, which means we have to make up an address, no? > > We can either give the node a name without a unit-address (e.g. cs_0), > or define some reg format. I think I'll go for the cs_X or csX solution. > > > + #address-cells = <2>; > > + #size-cells = <1>; > > + ranges; > > + atmel,generic-dev; > > The cover letter mentioned this should go. Yes, it's a leftover from the previous version. I'll remove it. > > > + atmel,read-mode = "nrd"; > > + atmel,write-mode = "nwe"; > > + atmel,bus-width = <16>; > > + atmel,ncs-rd-setup-ns = <0>; > > + atmel,ncs-wr-setup-ns = <0>; > > + atmel,nwe-setup-ns = <8>; > > + atmel,nrd-setup-ns = <16>; > > + atmel,ncs-rd-pulse-ns = <84>; > > + atmel,ncs-wr-pulse-ns = <84>; > > + atmel,nrd-pulse-ns = <76>; > > + atmel,nwe-pulse-ns = <76>; > > + atmel,nrd-cycle-ns = <107>; > > + atmel,nwe-cycle-ns = <84>; > > + atmel,tdf-ns = <16>; > > + > > + nor: flash@0,0 { > > + compatible = "cfi-flash"; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + reg = <0x0 0x0 0x1000000>; > > It feels odd that in the node for chipselect N, sub-devices have to > encode the chipselect number in their reg, when it's obvious from their > container. It may make more sense for the cs node to have a non-empty > reg (or somehow to make that translation/truncation implicit). Well, it's using the ranges property to automate reg => struct resource conversion, and the CS number is part of this conversion. Do you see a simpler solution to do that. Also, I'd like to mention that I'm not really happy with the current DT representation: ideally, I'd like to have devices connected to the EBI bus as direct sub-nodes of the ebi node, but that's not possible, because we have to isolate EBI bus config (timings and other bus related configs) from device description (which is driver specific). I considered splitting the subdevices and configs descriptions in two different subnodes, but decided to go for the representation already used by other memory controllers (see TI AEMIF binding). Any suggestions? Regards, Boris
Hi Mark, On Wed, 27 Apr 2016 16:07:38 +0100 Mark Rutland <mark.rutland@arm.com> wrote: > On Wed, Apr 27, 2016 at 04:35:54PM +0200, Boris Brezillon wrote: > > The EBI (External Bus Interface) is used to access external peripherals > > (NOR, SRAM, NAND, and other specific devices like ethernet controllers). > > Each device is assigned a CS line and an address range and can have its > > own configuration (timings, access mode, bus width, ...). > > This driver provides a generic DT binding to configure a device according > > to its requirements. > > For specific device controllers (like the NAND one) the SMC timings > > should be configured by the controller driver through the matrix and smc > > syscon regmaps. > > > > Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> > > --- > > .../bindings/memory-controllers/atmel,ebi.txt | 146 +++++++++++++++++++++ > > 1 file changed, 146 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt > > > > diff --git a/Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt b/Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt > > new file mode 100644 > > index 0000000..0f332d2 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt > > @@ -0,0 +1,146 @@ > > +* Device tree bindings for Atmel EBI > > + > > +The External Bus Interface (EBI) controller is a bus where you can connect > > +asynchronous (NAND, NOR, SRAM, ....) and synchronous memories (SDR/DDR SDRAMs). > > +The EBI provides a glue-less interface to asynchronous memories though the SMC > > +(Static Memory Controller). > > +Synchronous memories (and some asynchronous memories like NANDs) can be > > +attached to specialized controllers which are responsible for configuring the > > +bus appropriately according to the connected device. > > +In the other hand, the bus interface can be automated for simple asynchronous > > +devices. > > + > > +Required properties: > > + > > +- compatible: "atmel,at91sam9260-ebi" > > + "atmel,at91sam9261-ebi" > > + "atmel,at91sam9263-ebi0" > > + "atmel,at91sam9263-ebi1" > > + "atmel,at91sam9rl-ebi" > > + "atmel,at91sam9g45-ebi" > > + "atmel,at91sam9x5-ebi" > > + "atmel,sama5d3-ebi" > > + > > +- reg: Contains offset/length value for EBI memory mapping. > > + This property might contain several entries if the EBI > > + memory range is not contiguous > > + > > +- #address-cells: Must be 2. > > + The first cell encodes the CS. > > + The second cell encode the offset into the CS memory > > + range. > > + > > +- #size-cells: Must be set to 1. > > + > > +- ranges: Encodes CS to memory region association. > > + > > +- clocks: Clock feeding the EBI controller. > > + See clock-bindings.txt > > + > > +Child chip-select (cs) nodes contain the memory devices nodes connected to > > +such as NOR (e.g. cfi-flash) and NAND. > > +There might be board specific devices like FPGAs. > > +You'll define you device requirements in these child nodes. > > + > > +Required child cs node properties: > > + > > +- #address-cells: Must be 2. > > + > > +- #size-cells: Must be 1. > > + > > +- ranges: Empty property indicating that child nodes can inherit > > + memory layout. > > + > > +Optional child cs node properties: > > +- atmel,bus-width: width of the asynchronous device's data bus > > + 8, 16 or 32. > > + 8 if not present. > > + > > +- atmel,byte-access-type "write" or "select" (see Atmel datasheet). > > + "select" if not present. > > + > > +- atmel,read-mode "nrd" or "ncs". > > + "ncs" is not present. > > + > > +- atmel,write-mode "nwe" or "ncs". > > + "ncs" is not present. > > + > > +- atmel,exnw-mode "disabled", "frozen" or "ready". > > + "disabled" if not present. > > + > > +- atmel,page-mode enable page mode if present. The provided value > > + defines the page size (supported values: 4, 8, > > + 16 and 32). > > + > > +Optional device timings expressed in nanoseconds (if the property is not > > +present 0 is assumed): > > + > > +- atmel,ncs-rd-setup-ns > > +- atmel,nrd-setup-ns > > +- atmel,ncs-wr-setup-ns > > +- atmel,nwe-setup-ns > > +- atmel,ncs-rd-pulse-ns > > +- atmel,nrd-pulse-ns > > +- atmel,ncs-wr-pulse-ns > > +- atmel,nwe-pulse-ns > > +- atmel,nwe-cycle-ns > > +- atmel,nrd-cycle-ns > > +- atmel,tdf-ns > > I assume that these are defined in a datasheet. It may be worth noting > "see datasheet" above this collection of properties. > > > + > > +- atmel,tdf-mode: "normal" or "optimized". If set to "optimized" > > + the data float time is optimized depending on > > + the next device being accessed (next device > > + setup time is subtracted to the current device > > + data float time). > > + > > + > > + > > +Example: > > + > > + ebi: ebi@10000000 { > > + compatible = "atmel,sama5d3-ebi", "simple-bus"; > > I don't believe that "simple-bus" should be here. > > > + #address-cells = <2>; > > + #size-cells = <1>; > > + atmel,smc = <&hsmc>; > > + atmel,matrix = <&matrix>; > > + reg = <0x10000000 0x10000000 > > + 0x40000000 0x30000000>; > > + ranges = <0x0 0x0 0x10000000 0x10000000 > > + 0x1 0x0 0x40000000 0x10000000 > > + 0x2 0x0 0x50000000 0x10000000 > > + 0x3 0x0 0x60000000 0x10000000>; > > + clocks = <&mck>; > > + > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_ebi_addr>; > > + > > + cs@0 { > > I suspect recent DTC will warn here, as the unit-address should match > the reg for the node (and no reg is defined). Here the reg would have to > be two cells, which means we have to make up an address, no? > > We can either give the node a name without a unit-address (e.g. cs_0), > or define some reg format. > > > + #address-cells = <2>; > > + #size-cells = <1>; > > + ranges; > > + atmel,generic-dev; > > The cover letter mentioned this should go. > > > + atmel,read-mode = "nrd"; > > + atmel,write-mode = "nwe"; > > + atmel,bus-width = <16>; > > + atmel,ncs-rd-setup-ns = <0>; > > + atmel,ncs-wr-setup-ns = <0>; > > + atmel,nwe-setup-ns = <8>; > > + atmel,nrd-setup-ns = <16>; > > + atmel,ncs-rd-pulse-ns = <84>; > > + atmel,ncs-wr-pulse-ns = <84>; > > + atmel,nrd-pulse-ns = <76>; > > + atmel,nwe-pulse-ns = <76>; > > + atmel,nrd-cycle-ns = <107>; > > + atmel,nwe-cycle-ns = <84>; > > + atmel,tdf-ns = <16>; > > + > > + nor: flash@0,0 { > > + compatible = "cfi-flash"; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + reg = <0x0 0x0 0x1000000>; > > It feels odd that in the node for chipselect N, sub-devices have to > encode the chipselect number in their reg, when it's obvious from their > container. It may make more sense for the cs node to have a non-empty > reg (or somehow to make that translation/truncation implicit). Would you agree with the following representation? ebi: ebi@10000000 { compatible = "atmel,sama5d3-ebi"; #address-cells = <2>; #size-cells = <1>; atmel,smc = <&hsmc>; atmel,matrix = <&matrix>; reg = <0x10000000 0x10000000 0x40000000 0x30000000>; ranges = <0x0 0x0 0x10000000 0x10000000 0x1 0x0 0x40000000 0x10000000 0x2 0x0 0x50000000 0x10000000 0x3 0x0 0x60000000 0x10000000>; clocks = <&mck>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ebi_addr>; configs { config-0 { atmel,read-mode = "nrd"; atmel,write-mode = "nwe"; atmel,bus-width = <16>; atmel,ncs-rd-setup-ns = <0>; atmel,ncs-wr-setup-ns = <0>; atmel,nwe-setup-ns = <8>; atmel,nrd-setup-ns = <16>; atmel,ncs-rd-pulse-ns = <84>; atmel,ncs-wr-pulse-ns = <84>; atmel,nrd-pulse-ns = <76>; atmel,nwe-pulse-ns = <76>; atmel,nrd-cycle-ns = <107>; atmel,nwe-cycle-ns = <84>; atmel,tdf-ns = <16>; }; }; nor: flash@0,0 { compatible = "cfi-flash"; #address-cells = <1>; #size-cells = <1>; reg = <0x0 0x0 0x1000000>; bank-width = <2>; }; }; Regards, Boris
Hi Boris, i haven't seen this code in a while :) I'm glad you're working on it 2016-04-27 16:35 GMT+02:00 Boris Brezillon <boris.brezillon@free-electrons.com>: > The EBI (External Bus Interface) is used to access external peripherals > (NOR, SRAM, NAND, and other specific devices like ethernet controllers). > Each device is assigned a CS line and an address range and can have its > own configuration (timings, access mode, bus width, ...). > This driver provides a generic DT binding to configure a device according > to its requirements. > For specific device controllers (like the NAND one) the SMC timings > should be configured by the controller driver through the matrix and smc > syscon regmaps. > > Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> > --- > .../bindings/memory-controllers/atmel,ebi.txt | 146 +++++++++++++++++++++ > 1 file changed, 146 insertions(+) > create mode 100644 Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt > > diff --git a/Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt b/Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt > new file mode 100644 > index 0000000..0f332d2 > --- /dev/null > +++ b/Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt > @@ -0,0 +1,146 @@ > +* Device tree bindings for Atmel EBI > + > +The External Bus Interface (EBI) controller is a bus where you can connect > +asynchronous (NAND, NOR, SRAM, ....) and synchronous memories (SDR/DDR SDRAMs). > +The EBI provides a glue-less interface to asynchronous memories though the SMC > +(Static Memory Controller). > +Synchronous memories (and some asynchronous memories like NANDs) can be > +attached to specialized controllers which are responsible for configuring the > +bus appropriately according to the connected device. > +In the other hand, the bus interface can be automated for simple asynchronous > +devices. > + > +Required properties: > + > +- compatible: "atmel,at91sam9260-ebi" > + "atmel,at91sam9261-ebi" > + "atmel,at91sam9263-ebi0" > + "atmel,at91sam9263-ebi1" > + "atmel,at91sam9rl-ebi" > + "atmel,at91sam9g45-ebi" > + "atmel,at91sam9x5-ebi" > + "atmel,sama5d3-ebi" > + > +- reg: Contains offset/length value for EBI memory mapping. > + This property might contain several entries if the EBI > + memory range is not contiguous > + > +- #address-cells: Must be 2. > + The first cell encodes the CS. > + The second cell encode the offset into the CS memory > + range. > + > +- #size-cells: Must be set to 1. > + > +- ranges: Encodes CS to memory region association. > + > +- clocks: Clock feeding the EBI controller. > + See clock-bindings.txt > + > +Child chip-select (cs) nodes contain the memory devices nodes connected to > +such as NOR (e.g. cfi-flash) and NAND. > +There might be board specific devices like FPGAs. > +You'll define you device requirements in these child nodes. > + > +Required child cs node properties: > + > +- #address-cells: Must be 2. > + > +- #size-cells: Must be 1. > + > +- ranges: Empty property indicating that child nodes can inherit > + memory layout. > + > +Optional child cs node properties: > +- atmel,bus-width: width of the asynchronous device's data bus > + 8, 16 or 32. > + 8 if not present. > + > +- atmel,byte-access-type "write" or "select" (see Atmel datasheet). > + "select" if not present. > + > +- atmel,read-mode "nrd" or "ncs". > + "ncs" is not present. > + > +- atmel,write-mode "nwe" or "ncs". > + "ncs" is not present. > + > +- atmel,exnw-mode "disabled", "frozen" or "ready". > + "disabled" if not present. > + > +- atmel,page-mode enable page mode if present. The provided value > + defines the page size (supported values: 4, 8, > + 16 and 32). > + > +Optional device timings expressed in nanoseconds (if the property is not > +present 0 is assumed): IMO If no timing information is provided, it's probably better not to change it. It may have been configured by the bootloader or romboot. It may not be the perfect timings but at least it could work, whereas filling up with 0 is most probably going to break the access: it's a kind of very agressive timing optimization > + > +- atmel,ncs-rd-setup-ns > +- atmel,nrd-setup-ns > +- atmel,ncs-wr-setup-ns > +- atmel,nwe-setup-ns > +- atmel,ncs-rd-pulse-ns > +- atmel,nrd-pulse-ns > +- atmel,ncs-wr-pulse-ns > +- atmel,nwe-pulse-ns > +- atmel,nwe-cycle-ns > +- atmel,nrd-cycle-ns > +- atmel,tdf-ns One thought about the configuration in 'ns' unit: Some devices may have requirements expressed in clock cycles (I'm thinking of FPGA here). At a fixed frequency one can always convert manually from 'ns' to 'clocks' but it's a bit tedious and prone to rounding errors. And It 'll break when the EBI frequency is changed JJ > + > +- atmel,tdf-mode: "normal" or "optimized". If set to "optimized" > + the data float time is optimized depending on > + the next device being accessed (next device > + setup time is subtracted to the current device > + data float time). > + > + > + > +Example: > + > + ebi: ebi@10000000 { > + compatible = "atmel,sama5d3-ebi", "simple-bus"; > + #address-cells = <2>; > + #size-cells = <1>; > + atmel,smc = <&hsmc>; > + atmel,matrix = <&matrix>; > + reg = <0x10000000 0x10000000 > + 0x40000000 0x30000000>; > + ranges = <0x0 0x0 0x10000000 0x10000000 > + 0x1 0x0 0x40000000 0x10000000 > + 0x2 0x0 0x50000000 0x10000000 > + 0x3 0x0 0x60000000 0x10000000>; > + clocks = <&mck>; > + > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_ebi_addr>; > + > + cs@0 { > + #address-cells = <2>; > + #size-cells = <1>; > + ranges; > + atmel,generic-dev; > + atmel,read-mode = "nrd"; > + atmel,write-mode = "nwe"; > + atmel,bus-width = <16>; > + atmel,ncs-rd-setup-ns = <0>; > + atmel,ncs-wr-setup-ns = <0>; > + atmel,nwe-setup-ns = <8>; > + atmel,nrd-setup-ns = <16>; > + atmel,ncs-rd-pulse-ns = <84>; > + atmel,ncs-wr-pulse-ns = <84>; > + atmel,nrd-pulse-ns = <76>; > + atmel,nwe-pulse-ns = <76>; > + atmel,nrd-cycle-ns = <107>; > + atmel,nwe-cycle-ns = <84>; > + atmel,tdf-ns = <16>; > + > + nor: flash@0,0 { > + compatible = "cfi-flash"; > + #address-cells = <1>; > + #size-cells = <1>; > + reg = <0x0 0x0 0x1000000>; > + bank-width = <2>; > + }; > + }; > + }; > + > -- > 2.7.4 >
Hi Jean-Jacques, On Thu, 28 Apr 2016 10:32:49 +0200 Jean-Jacques Hiblot <jjhiblot@traphandler.com> wrote: > Hi Boris, > > i haven't seen this code in a while :) I'm glad you're working on it > > 2016-04-27 16:35 GMT+02:00 Boris Brezillon <boris.brezillon@free-electrons.com>: > > The EBI (External Bus Interface) is used to access external peripherals > > (NOR, SRAM, NAND, and other specific devices like ethernet controllers). > > Each device is assigned a CS line and an address range and can have its > > own configuration (timings, access mode, bus width, ...). > > This driver provides a generic DT binding to configure a device according > > to its requirements. > > For specific device controllers (like the NAND one) the SMC timings > > should be configured by the controller driver through the matrix and smc > > syscon regmaps. > > > > Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> > > --- > > .../bindings/memory-controllers/atmel,ebi.txt | 146 +++++++++++++++++++++ > > 1 file changed, 146 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt > > > > diff --git a/Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt b/Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt > > new file mode 100644 > > index 0000000..0f332d2 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt > > @@ -0,0 +1,146 @@ > > +* Device tree bindings for Atmel EBI > > + > > +The External Bus Interface (EBI) controller is a bus where you can connect > > +asynchronous (NAND, NOR, SRAM, ....) and synchronous memories (SDR/DDR SDRAMs). > > +The EBI provides a glue-less interface to asynchronous memories though the SMC > > +(Static Memory Controller). > > +Synchronous memories (and some asynchronous memories like NANDs) can be > > +attached to specialized controllers which are responsible for configuring the > > +bus appropriately according to the connected device. > > +In the other hand, the bus interface can be automated for simple asynchronous > > +devices. > > + > > +Required properties: > > + > > +- compatible: "atmel,at91sam9260-ebi" > > + "atmel,at91sam9261-ebi" > > + "atmel,at91sam9263-ebi0" > > + "atmel,at91sam9263-ebi1" > > + "atmel,at91sam9rl-ebi" > > + "atmel,at91sam9g45-ebi" > > + "atmel,at91sam9x5-ebi" > > + "atmel,sama5d3-ebi" > > + > > +- reg: Contains offset/length value for EBI memory mapping. > > + This property might contain several entries if the EBI > > + memory range is not contiguous > > + > > +- #address-cells: Must be 2. > > + The first cell encodes the CS. > > + The second cell encode the offset into the CS memory > > + range. > > + > > +- #size-cells: Must be set to 1. > > + > > +- ranges: Encodes CS to memory region association. > > + > > +- clocks: Clock feeding the EBI controller. > > + See clock-bindings.txt > > + > > +Child chip-select (cs) nodes contain the memory devices nodes connected to > > +such as NOR (e.g. cfi-flash) and NAND. > > +There might be board specific devices like FPGAs. > > +You'll define you device requirements in these child nodes. > > + > > +Required child cs node properties: > > + > > +- #address-cells: Must be 2. > > + > > +- #size-cells: Must be 1. > > + > > +- ranges: Empty property indicating that child nodes can inherit > > + memory layout. > > + > > +Optional child cs node properties: > > +- atmel,bus-width: width of the asynchronous device's data bus > > + 8, 16 or 32. > > + 8 if not present. > > + > > +- atmel,byte-access-type "write" or "select" (see Atmel datasheet). > > + "select" if not present. > > + > > +- atmel,read-mode "nrd" or "ncs". > > + "ncs" is not present. > > + > > +- atmel,write-mode "nwe" or "ncs". > > + "ncs" is not present. > > + > > +- atmel,exnw-mode "disabled", "frozen" or "ready". > > + "disabled" if not present. > > + > > +- atmel,page-mode enable page mode if present. The provided value > > + defines the page size (supported values: 4, 8, > > + 16 and 32). > > + > > +Optional device timings expressed in nanoseconds (if the property is not > > +present 0 is assumed): > > IMO If no timing information is provided, it's probably better not to > change it. It may have been configured by the bootloader or romboot. > It may not be the perfect timings but at least it could work, whereas > filling up with 0 is most probably going to break the access: it's a > kind of very agressive timing optimization Yes, probably. I'll make all those timings mandatory in the next version. > > > + > > +- atmel,ncs-rd-setup-ns > > +- atmel,nrd-setup-ns > > +- atmel,ncs-wr-setup-ns > > +- atmel,nwe-setup-ns > > +- atmel,ncs-rd-pulse-ns > > +- atmel,nrd-pulse-ns > > +- atmel,ncs-wr-pulse-ns > > +- atmel,nwe-pulse-ns > > +- atmel,nwe-cycle-ns > > +- atmel,nrd-cycle-ns > > +- atmel,tdf-ns > > One thought about the configuration in 'ns' unit: Some devices may > have requirements expressed in clock cycles (I'm thinking of FPGA > here). At a fixed frequency one can always convert manually from 'ns' > to 'clocks' but it's a bit tedious and prone to rounding errors. And > It 'll break when the EBI frequency is changed If you don't mind, I'd like to first get this version accepted, and we'll extend it with timings expressed in clock cycles afterward. BTW, could you describe a real use case where timings should be expressed in clock cycles? I mean, usually the devices have some timing constraints (tXX_min = Y ns), and I don't see why it would differ for FPGA interfaces, but I'm clearly not an FPGA expert. Thanks, Boris
Hi, On Thu, Apr 28, 2016 at 08:44:05AM +0200, Boris Brezillon wrote: > On Wed, 27 Apr 2016 16:07:38 +0100 > Mark Rutland <mark.rutland@arm.com> wrote: > > On Wed, Apr 27, 2016 at 04:35:54PM +0200, Boris Brezillon wrote: > > > + ebi: ebi@10000000 { > > > + compatible = "atmel,sama5d3-ebi", "simple-bus"; > > > + #address-cells = <2>; > > > + #size-cells = <1>; > > > + atmel,smc = <&hsmc>; > > > + atmel,matrix = <&matrix>; > > > + reg = <0x10000000 0x10000000 > > > + 0x40000000 0x30000000>; > > > + ranges = <0x0 0x0 0x10000000 0x10000000 > > > + 0x1 0x0 0x40000000 0x10000000 > > > + 0x2 0x0 0x50000000 0x10000000 > > > + 0x3 0x0 0x60000000 0x10000000>; > > > + clocks = <&mck>; > > > + > > > + pinctrl-names = "default"; > > > + pinctrl-0 = <&pinctrl_ebi_addr>; > > > + > > > + cs@0 { > > > + #address-cells = <2>; > > > + #size-cells = <1>; > > > + ranges; > > > + atmel,generic-dev; > > > + atmel,read-mode = "nrd"; > > > + atmel,write-mode = "nwe"; > > > + atmel,bus-width = <16>; > > > + atmel,ncs-rd-setup-ns = <0>; > > > + atmel,ncs-wr-setup-ns = <0>; > > > + atmel,nwe-setup-ns = <8>; > > > + atmel,nrd-setup-ns = <16>; > > > + atmel,ncs-rd-pulse-ns = <84>; > > > + atmel,ncs-wr-pulse-ns = <84>; > > > + atmel,nrd-pulse-ns = <76>; > > > + atmel,nwe-pulse-ns = <76>; > > > + atmel,nrd-cycle-ns = <107>; > > > + atmel,nwe-cycle-ns = <84>; > > > + atmel,tdf-ns = <16>; > > > + > > > + nor: flash@0,0 { > > > + compatible = "cfi-flash"; > > > + #address-cells = <1>; > > > + #size-cells = <1>; > > > + reg = <0x0 0x0 0x1000000>; > > > > It feels odd that in the node for chipselect N, sub-devices have to > > encode the chipselect number in their reg, when it's obvious from their > > container. It may make more sense for the cs node to have a non-empty > > reg (or somehow to make that translation/truncation implicit). > > Would you agree with the following representation? > > ebi: ebi@10000000 { > compatible = "atmel,sama5d3-ebi"; > #address-cells = <2>; > #size-cells = <1>; > atmel,smc = <&hsmc>; > atmel,matrix = <&matrix>; > reg = <0x10000000 0x10000000 > 0x40000000 0x30000000>; > ranges = <0x0 0x0 0x10000000 0x10000000 > 0x1 0x0 0x40000000 0x10000000 > 0x2 0x0 0x50000000 0x10000000 > 0x3 0x0 0x60000000 0x10000000>; > clocks = <&mck>; > > pinctrl-names = "default"; > pinctrl-0 = <&pinctrl_ebi_addr>; > > configs { > config-0 { > atmel,read-mode = "nrd"; > atmel,write-mode = "nwe"; > atmel,bus-width = <16>; > atmel,ncs-rd-setup-ns = <0>; > atmel,ncs-wr-setup-ns = <0>; > atmel,nwe-setup-ns = <8>; > atmel,nrd-setup-ns = <16>; > atmel,ncs-rd-pulse-ns = <84>; > atmel,ncs-wr-pulse-ns = <84>; > atmel,nrd-pulse-ns = <76>; > atmel,nwe-pulse-ns = <76>; > atmel,nrd-cycle-ns = <107>; > atmel,nwe-cycle-ns = <84>; > atmel,tdf-ns = <16>; > }; > }; > > nor: flash@0,0 { > compatible = "cfi-flash"; > #address-cells = <1>; > #size-cells = <1>; > reg = <0x0 0x0 0x1000000>; > bank-width = <2>; > }; > }; Something of that sort looks good to me, yes. Thanks, Mark.
2016-04-28 10:49 GMT+02:00 Boris Brezillon <boris.brezillon@free-electrons.com>: > Hi Jean-Jacques, > > On Thu, 28 Apr 2016 10:32:49 +0200 > Jean-Jacques Hiblot <jjhiblot@traphandler.com> wrote: > >> Hi Boris, >> >> i haven't seen this code in a while :) I'm glad you're working on it >> >> 2016-04-27 16:35 GMT+02:00 Boris Brezillon <boris.brezillon@free-electrons.com>: >> > The EBI (External Bus Interface) is used to access external peripherals >> > (NOR, SRAM, NAND, and other specific devices like ethernet controllers). >> > Each device is assigned a CS line and an address range and can have its >> > own configuration (timings, access mode, bus width, ...). >> > This driver provides a generic DT binding to configure a device according >> > to its requirements. >> > For specific device controllers (like the NAND one) the SMC timings >> > should be configured by the controller driver through the matrix and smc >> > syscon regmaps. >> > >> > Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> >> > --- >> > .../bindings/memory-controllers/atmel,ebi.txt | 146 +++++++++++++++++++++ >> > 1 file changed, 146 insertions(+) >> > create mode 100644 Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt >> > >> > diff --git a/Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt b/Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt >> > new file mode 100644 >> > index 0000000..0f332d2 >> > --- /dev/null >> > +++ b/Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt >> > @@ -0,0 +1,146 @@ >> > +* Device tree bindings for Atmel EBI >> > + >> > +The External Bus Interface (EBI) controller is a bus where you can connect >> > +asynchronous (NAND, NOR, SRAM, ....) and synchronous memories (SDR/DDR SDRAMs). >> > +The EBI provides a glue-less interface to asynchronous memories though the SMC >> > +(Static Memory Controller). >> > +Synchronous memories (and some asynchronous memories like NANDs) can be >> > +attached to specialized controllers which are responsible for configuring the >> > +bus appropriately according to the connected device. >> > +In the other hand, the bus interface can be automated for simple asynchronous >> > +devices. >> > + >> > +Required properties: >> > + >> > +- compatible: "atmel,at91sam9260-ebi" >> > + "atmel,at91sam9261-ebi" >> > + "atmel,at91sam9263-ebi0" >> > + "atmel,at91sam9263-ebi1" >> > + "atmel,at91sam9rl-ebi" >> > + "atmel,at91sam9g45-ebi" >> > + "atmel,at91sam9x5-ebi" >> > + "atmel,sama5d3-ebi" >> > + >> > +- reg: Contains offset/length value for EBI memory mapping. >> > + This property might contain several entries if the EBI >> > + memory range is not contiguous >> > + >> > +- #address-cells: Must be 2. >> > + The first cell encodes the CS. >> > + The second cell encode the offset into the CS memory >> > + range. >> > + >> > +- #size-cells: Must be set to 1. >> > + >> > +- ranges: Encodes CS to memory region association. >> > + >> > +- clocks: Clock feeding the EBI controller. >> > + See clock-bindings.txt >> > + >> > +Child chip-select (cs) nodes contain the memory devices nodes connected to >> > +such as NOR (e.g. cfi-flash) and NAND. >> > +There might be board specific devices like FPGAs. >> > +You'll define you device requirements in these child nodes. >> > + >> > +Required child cs node properties: >> > + >> > +- #address-cells: Must be 2. >> > + >> > +- #size-cells: Must be 1. >> > + >> > +- ranges: Empty property indicating that child nodes can inherit >> > + memory layout. >> > + >> > +Optional child cs node properties: >> > +- atmel,bus-width: width of the asynchronous device's data bus >> > + 8, 16 or 32. >> > + 8 if not present. >> > + >> > +- atmel,byte-access-type "write" or "select" (see Atmel datasheet). >> > + "select" if not present. >> > + >> > +- atmel,read-mode "nrd" or "ncs". >> > + "ncs" is not present. >> > + >> > +- atmel,write-mode "nwe" or "ncs". >> > + "ncs" is not present. >> > + >> > +- atmel,exnw-mode "disabled", "frozen" or "ready". >> > + "disabled" if not present. >> > + >> > +- atmel,page-mode enable page mode if present. The provided value >> > + defines the page size (supported values: 4, 8, >> > + 16 and 32). >> > + >> > +Optional device timings expressed in nanoseconds (if the property is not >> > +present 0 is assumed): >> >> IMO If no timing information is provided, it's probably better not to >> change it. It may have been configured by the bootloader or romboot. >> It may not be the perfect timings but at least it could work, whereas >> filling up with 0 is most probably going to break the access: it's a >> kind of very agressive timing optimization > > Yes, probably. I'll make all those timings mandatory in the next > version. > >> >> > + >> > +- atmel,ncs-rd-setup-ns >> > +- atmel,nrd-setup-ns >> > +- atmel,ncs-wr-setup-ns >> > +- atmel,nwe-setup-ns >> > +- atmel,ncs-rd-pulse-ns >> > +- atmel,nrd-pulse-ns >> > +- atmel,ncs-wr-pulse-ns >> > +- atmel,nwe-pulse-ns >> > +- atmel,nwe-cycle-ns >> > +- atmel,nrd-cycle-ns >> > +- atmel,tdf-ns >> >> One thought about the configuration in 'ns' unit: Some devices may >> have requirements expressed in clock cycles (I'm thinking of FPGA >> here). At a fixed frequency one can always convert manually from 'ns' >> to 'clocks' but it's a bit tedious and prone to rounding errors. And >> It 'll break when the EBI frequency is changed > > If you don't mind, I'd like to first get this version accepted, and > we'll extend it with timings expressed in clock cycles afterward. > > BTW, could you describe a real use case where timings should be > expressed in clock cycles? I mean, usually the devices have some timing > constraints (tXX_min = Y ns), and I don't see why it would differ for > FPGA interfaces, but I'm clearly not an FPGA expert. I'm not either, I only toyed with FPGA. That's just what experienced FPGA designer told me. I guess that it boils down to: FPGA are more suited for a synchronous design than an asynchronous one. JJ > > Thanks, > > Boris > > -- > Boris Brezillon, Free Electrons > Embedded Linux and Kernel engineering > http://free-electrons.com > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On Thu, 28 Apr 2016 14:18:25 +0200 Jean-Jacques Hiblot <jjhiblot@traphandler.com> wrote: > >> > + > >> > +- atmel,ncs-rd-setup-ns > >> > +- atmel,nrd-setup-ns > >> > +- atmel,ncs-wr-setup-ns > >> > +- atmel,nwe-setup-ns > >> > +- atmel,ncs-rd-pulse-ns > >> > +- atmel,nrd-pulse-ns > >> > +- atmel,ncs-wr-pulse-ns > >> > +- atmel,nwe-pulse-ns > >> > +- atmel,nwe-cycle-ns > >> > +- atmel,nrd-cycle-ns > >> > +- atmel,tdf-ns > >> > >> One thought about the configuration in 'ns' unit: Some devices may > >> have requirements expressed in clock cycles (I'm thinking of FPGA > >> here). At a fixed frequency one can always convert manually from 'ns' > >> to 'clocks' but it's a bit tedious and prone to rounding errors. And > >> It 'll break when the EBI frequency is changed > > > > If you don't mind, I'd like to first get this version accepted, and > > we'll extend it with timings expressed in clock cycles afterward. > > > > BTW, could you describe a real use case where timings should be > > expressed in clock cycles? I mean, usually the devices have some timing > > constraints (tXX_min = Y ns), and I don't see why it would differ for > > FPGA interfaces, but I'm clearly not an FPGA expert. > > I'm not either, I only toyed with FPGA. That's just what experienced > FPGA designer told me. > I guess that it boils down to: FPGA are more suited for a synchronous > design than an asynchronous one. The thing is, all the timings are based on the master clock, and, AFAICS, this clk signal is not exposed, so you're basing your clk-cycle based timings on something that can change depending on how the bootstrap/bootloader decided to configure the master clk. One option would be to define one of the timing as the reference, define this one in nanosecond, and define the other ones as multiple of the reference timing. But I'm not sure it's easier to do that than defining all the timings directly in nanoseconds.
2016-04-28 14:46 GMT+02:00 Boris Brezillon <boris.brezillon@free-electrons.com>: > On Thu, 28 Apr 2016 14:18:25 +0200 > Jean-Jacques Hiblot <jjhiblot@traphandler.com> wrote: >> >> > + >> >> > +- atmel,ncs-rd-setup-ns >> >> > +- atmel,nrd-setup-ns >> >> > +- atmel,ncs-wr-setup-ns >> >> > +- atmel,nwe-setup-ns >> >> > +- atmel,ncs-rd-pulse-ns >> >> > +- atmel,nrd-pulse-ns >> >> > +- atmel,ncs-wr-pulse-ns >> >> > +- atmel,nwe-pulse-ns >> >> > +- atmel,nwe-cycle-ns >> >> > +- atmel,nrd-cycle-ns >> >> > +- atmel,tdf-ns >> >> >> >> One thought about the configuration in 'ns' unit: Some devices may >> >> have requirements expressed in clock cycles (I'm thinking of FPGA >> >> here). At a fixed frequency one can always convert manually from 'ns' >> >> to 'clocks' but it's a bit tedious and prone to rounding errors. And >> >> It 'll break when the EBI frequency is changed >> > >> > If you don't mind, I'd like to first get this version accepted, and >> > we'll extend it with timings expressed in clock cycles afterward. >> > >> > BTW, could you describe a real use case where timings should be >> > expressed in clock cycles? I mean, usually the devices have some timing >> > constraints (tXX_min = Y ns), and I don't see why it would differ for >> > FPGA interfaces, but I'm clearly not an FPGA expert. >> >> I'm not either, I only toyed with FPGA. That's just what experienced >> FPGA designer told me. >> I guess that it boils down to: FPGA are more suited for a synchronous >> design than an asynchronous one. > > The thing is, all the timings are based on the master clock, and, > AFAICS, this clk signal is not exposed, so you're basing your clk-cycle while EBI itself is asynchronous, the clk can be exposed through one of the PCK. I've seen this in real projects. > based timings on something that can change depending on how the > bootstrap/bootloader decided to configure the master clk. > > One option would be to define one of the timing as the reference, > define this one in nanosecond, and define the other ones as multiple of > the reference timing. But I'm not sure it's easier to do that than > defining all the timings directly in nanoseconds. > > -- > Boris Brezillon, Free Electrons > Embedded Linux and Kernel engineering > http://free-electrons.com > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On Thu, 28 Apr 2016 14:54:39 +0200 Jean-Jacques Hiblot <jjhiblot@traphandler.com> wrote: > 2016-04-28 14:46 GMT+02:00 Boris Brezillon <boris.brezillon@free-electrons.com>: > > On Thu, 28 Apr 2016 14:18:25 +0200 > > Jean-Jacques Hiblot <jjhiblot@traphandler.com> wrote: > >> >> > + > >> >> > +- atmel,ncs-rd-setup-ns > >> >> > +- atmel,nrd-setup-ns > >> >> > +- atmel,ncs-wr-setup-ns > >> >> > +- atmel,nwe-setup-ns > >> >> > +- atmel,ncs-rd-pulse-ns > >> >> > +- atmel,nrd-pulse-ns > >> >> > +- atmel,ncs-wr-pulse-ns > >> >> > +- atmel,nwe-pulse-ns > >> >> > +- atmel,nwe-cycle-ns > >> >> > +- atmel,nrd-cycle-ns > >> >> > +- atmel,tdf-ns > >> >> > >> >> One thought about the configuration in 'ns' unit: Some devices may > >> >> have requirements expressed in clock cycles (I'm thinking of FPGA > >> >> here). At a fixed frequency one can always convert manually from 'ns' > >> >> to 'clocks' but it's a bit tedious and prone to rounding errors. And > >> >> It 'll break when the EBI frequency is changed > >> > > >> > If you don't mind, I'd like to first get this version accepted, and > >> > we'll extend it with timings expressed in clock cycles afterward. > >> > > >> > BTW, could you describe a real use case where timings should be > >> > expressed in clock cycles? I mean, usually the devices have some timing > >> > constraints (tXX_min = Y ns), and I don't see why it would differ for > >> > FPGA interfaces, but I'm clearly not an FPGA expert. > >> > >> I'm not either, I only toyed with FPGA. That's just what experienced > >> FPGA designer told me. > >> I guess that it boils down to: FPGA are more suited for a synchronous > >> design than an asynchronous one. > > > > The thing is, all the timings are based on the master clock, and, > > AFAICS, this clk signal is not exposed, so you're basing your clk-cycle > while EBI itself is asynchronous, the clk can be exposed through one > of the PCK. I've seen this in real projects. Okay, then it makes sense. But if you need such a complex thing it would probably be better to create a new driver and let this driver adapt the timings dynamically (I plan to expose an few fonctions for the NAND controller, so it would be possible to create an FPGA driver referencing the PCK clk and adapting the EBI timings).
diff --git a/Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt b/Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt new file mode 100644 index 0000000..0f332d2 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt @@ -0,0 +1,146 @@ +* Device tree bindings for Atmel EBI + +The External Bus Interface (EBI) controller is a bus where you can connect +asynchronous (NAND, NOR, SRAM, ....) and synchronous memories (SDR/DDR SDRAMs). +The EBI provides a glue-less interface to asynchronous memories though the SMC +(Static Memory Controller). +Synchronous memories (and some asynchronous memories like NANDs) can be +attached to specialized controllers which are responsible for configuring the +bus appropriately according to the connected device. +In the other hand, the bus interface can be automated for simple asynchronous +devices. + +Required properties: + +- compatible: "atmel,at91sam9260-ebi" + "atmel,at91sam9261-ebi" + "atmel,at91sam9263-ebi0" + "atmel,at91sam9263-ebi1" + "atmel,at91sam9rl-ebi" + "atmel,at91sam9g45-ebi" + "atmel,at91sam9x5-ebi" + "atmel,sama5d3-ebi" + +- reg: Contains offset/length value for EBI memory mapping. + This property might contain several entries if the EBI + memory range is not contiguous + +- #address-cells: Must be 2. + The first cell encodes the CS. + The second cell encode the offset into the CS memory + range. + +- #size-cells: Must be set to 1. + +- ranges: Encodes CS to memory region association. + +- clocks: Clock feeding the EBI controller. + See clock-bindings.txt + +Child chip-select (cs) nodes contain the memory devices nodes connected to +such as NOR (e.g. cfi-flash) and NAND. +There might be board specific devices like FPGAs. +You'll define you device requirements in these child nodes. + +Required child cs node properties: + +- #address-cells: Must be 2. + +- #size-cells: Must be 1. + +- ranges: Empty property indicating that child nodes can inherit + memory layout. + +Optional child cs node properties: +- atmel,bus-width: width of the asynchronous device's data bus + 8, 16 or 32. + 8 if not present. + +- atmel,byte-access-type "write" or "select" (see Atmel datasheet). + "select" if not present. + +- atmel,read-mode "nrd" or "ncs". + "ncs" is not present. + +- atmel,write-mode "nwe" or "ncs". + "ncs" is not present. + +- atmel,exnw-mode "disabled", "frozen" or "ready". + "disabled" if not present. + +- atmel,page-mode enable page mode if present. The provided value + defines the page size (supported values: 4, 8, + 16 and 32). + +Optional device timings expressed in nanoseconds (if the property is not +present 0 is assumed): + +- atmel,ncs-rd-setup-ns +- atmel,nrd-setup-ns +- atmel,ncs-wr-setup-ns +- atmel,nwe-setup-ns +- atmel,ncs-rd-pulse-ns +- atmel,nrd-pulse-ns +- atmel,ncs-wr-pulse-ns +- atmel,nwe-pulse-ns +- atmel,nwe-cycle-ns +- atmel,nrd-cycle-ns +- atmel,tdf-ns + +- atmel,tdf-mode: "normal" or "optimized". If set to "optimized" + the data float time is optimized depending on + the next device being accessed (next device + setup time is subtracted to the current device + data float time). + + + +Example: + + ebi: ebi@10000000 { + compatible = "atmel,sama5d3-ebi", "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + atmel,smc = <&hsmc>; + atmel,matrix = <&matrix>; + reg = <0x10000000 0x10000000 + 0x40000000 0x30000000>; + ranges = <0x0 0x0 0x10000000 0x10000000 + 0x1 0x0 0x40000000 0x10000000 + 0x2 0x0 0x50000000 0x10000000 + 0x3 0x0 0x60000000 0x10000000>; + clocks = <&mck>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ebi_addr>; + + cs@0 { + #address-cells = <2>; + #size-cells = <1>; + ranges; + atmel,generic-dev; + atmel,read-mode = "nrd"; + atmel,write-mode = "nwe"; + atmel,bus-width = <16>; + atmel,ncs-rd-setup-ns = <0>; + atmel,ncs-wr-setup-ns = <0>; + atmel,nwe-setup-ns = <8>; + atmel,nrd-setup-ns = <16>; + atmel,ncs-rd-pulse-ns = <84>; + atmel,ncs-wr-pulse-ns = <84>; + atmel,nrd-pulse-ns = <76>; + atmel,nwe-pulse-ns = <76>; + atmel,nrd-cycle-ns = <107>; + atmel,nwe-cycle-ns = <84>; + atmel,tdf-ns = <16>; + + nor: flash@0,0 { + compatible = "cfi-flash"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0 0x0 0x1000000>; + bank-width = <2>; + }; + }; + }; +
The EBI (External Bus Interface) is used to access external peripherals (NOR, SRAM, NAND, and other specific devices like ethernet controllers). Each device is assigned a CS line and an address range and can have its own configuration (timings, access mode, bus width, ...). This driver provides a generic DT binding to configure a device according to its requirements. For specific device controllers (like the NAND one) the SMC timings should be configured by the controller driver through the matrix and smc syscon regmaps. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> --- .../bindings/memory-controllers/atmel,ebi.txt | 146 +++++++++++++++++++++ 1 file changed, 146 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt