| Message ID | 1462273081-5814-10-git-send-email-architt@codeaurora.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, May 03, 2016 at 04:28:01PM +0530, Archit Taneja wrote: > The PLL in the DSI PHY block generates 2 clock outputs (Byte and Pixel > clocks) that are fed into the Multimedia Clock Controller (MMCC). The MMCC > uses these as source clocks for some of its RCGs to generate clocks that > finally feed to the DSI host controller. > > Use the assigned clocks DT bindings to set up the MMCC RCGs that feed to > the DSI host. Use the DSI PHY provided clocks to set up the parents > of these assigned clocks. > > Signed-off-by: Archit Taneja <architt@codeaurora.org> > --- > Documentation/devicetree/bindings/display/msm/dsi.txt | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt > index 0223f06..686f475 100644 > --- a/Documentation/devicetree/bindings/display/msm/dsi.txt > +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt > @@ -22,6 +22,10 @@ Required properties: > * "core_clk" > For DSIv2, we need an additional clock: > * "src_clk" > +- assigned-clocks: Parents of "byte_clk" and "pixel_clk" for the given platform. > + See [1] for more details. > +- assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided > + by a DSI PHY block. > - vdd-supply: phandle to vdd regulator device node > - vddio-supply: phandle to vdd-io regulator device node > - vdda-supply: phandle to vdda regulator device node > @@ -90,6 +94,8 @@ Required properties: > * "dsi_pll" > * "dsi_phy" > * "dsi_phy_regulator" > +- clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating > + 2 clocks: A byte clock (index 0), and a pixel clock (index 1). You can't really add new required properties unless they are for a new compatible string. Rob
On 5/4/2016 7:14 PM, Rob Herring wrote: > On Tue, May 03, 2016 at 04:28:01PM +0530, Archit Taneja wrote: >> The PLL in the DSI PHY block generates 2 clock outputs (Byte and Pixel >> clocks) that are fed into the Multimedia Clock Controller (MMCC). The MMCC >> uses these as source clocks for some of its RCGs to generate clocks that >> finally feed to the DSI host controller. >> >> Use the assigned clocks DT bindings to set up the MMCC RCGs that feed to >> the DSI host. Use the DSI PHY provided clocks to set up the parents >> of these assigned clocks. >> >> Signed-off-by: Archit Taneja <architt@codeaurora.org> >> --- >> Documentation/devicetree/bindings/display/msm/dsi.txt | 15 +++++++++++++++ >> 1 file changed, 15 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt >> index 0223f06..686f475 100644 >> --- a/Documentation/devicetree/bindings/display/msm/dsi.txt >> +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt >> @@ -22,6 +22,10 @@ Required properties: >> * "core_clk" >> For DSIv2, we need an additional clock: >> * "src_clk" >> +- assigned-clocks: Parents of "byte_clk" and "pixel_clk" for the given platform. >> + See [1] for more details. >> +- assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided >> + by a DSI PHY block. >> - vdd-supply: phandle to vdd regulator device node >> - vddio-supply: phandle to vdd-io regulator device node >> - vdda-supply: phandle to vdda regulator device node >> @@ -90,6 +94,8 @@ Required properties: >> * "dsi_pll" >> * "dsi_phy" >> * "dsi_phy_regulator" >> +- clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating >> + 2 clocks: A byte clock (index 0), and a pixel clock (index 1). > > You can't really add new required properties unless they are for a new > compatible string. Does this hold even when currently there isn't any device tree file in the kernel that has this DT node in it? I was trying to get all the properties in place before posting out patches that actually add the nodes into the platform files. Currently, they exist only DT files in downstream kernels. Thanks, Archit
On Wed, May 04, 2016 at 11:34:39PM +0530, Archit Taneja wrote: > > > On 5/4/2016 7:14 PM, Rob Herring wrote: > >On Tue, May 03, 2016 at 04:28:01PM +0530, Archit Taneja wrote: > >>The PLL in the DSI PHY block generates 2 clock outputs (Byte and Pixel > >>clocks) that are fed into the Multimedia Clock Controller (MMCC). The MMCC > >>uses these as source clocks for some of its RCGs to generate clocks that > >>finally feed to the DSI host controller. > >> > >>Use the assigned clocks DT bindings to set up the MMCC RCGs that feed to > >>the DSI host. Use the DSI PHY provided clocks to set up the parents > >>of these assigned clocks. > >> > >>Signed-off-by: Archit Taneja <architt@codeaurora.org> > >>--- > >> Documentation/devicetree/bindings/display/msm/dsi.txt | 15 +++++++++++++++ > >> 1 file changed, 15 insertions(+) > >> > >>diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt > >>index 0223f06..686f475 100644 > >>--- a/Documentation/devicetree/bindings/display/msm/dsi.txt > >>+++ b/Documentation/devicetree/bindings/display/msm/dsi.txt > >>@@ -22,6 +22,10 @@ Required properties: > >> * "core_clk" > >> For DSIv2, we need an additional clock: > >> * "src_clk" > >>+- assigned-clocks: Parents of "byte_clk" and "pixel_clk" for the given platform. > >>+ See [1] for more details. > >>+- assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided > >>+ by a DSI PHY block. > >> - vdd-supply: phandle to vdd regulator device node > >> - vddio-supply: phandle to vdd-io regulator device node > >> - vdda-supply: phandle to vdda regulator device node > >>@@ -90,6 +94,8 @@ Required properties: > >> * "dsi_pll" > >> * "dsi_phy" > >> * "dsi_phy_regulator" > >>+- clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating > >>+ 2 clocks: A byte clock (index 0), and a pixel clock (index 1). > > > >You can't really add new required properties unless they are for a new > >compatible string. > > Does this hold even when currently there isn't any device tree file in > the kernel that has this DT node in it? Generally it should, but in this case that is fine. Acked-by: Rob Herring <robh@kernel.org> > I was trying to get all the properties in place before posting out > patches that actually add the nodes into the platform files. Currently, > they exist only DT files in downstream kernels. "If it is not upstream, it doesn't exist." :) Rob
diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt index 0223f06..686f475 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi.txt +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt @@ -22,6 +22,10 @@ Required properties: * "core_clk" For DSIv2, we need an additional clock: * "src_clk" +- assigned-clocks: Parents of "byte_clk" and "pixel_clk" for the given platform. + See [1] for more details. +- assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided + by a DSI PHY block. - vdd-supply: phandle to vdd regulator device node - vddio-supply: phandle to vdd-io regulator device node - vdda-supply: phandle to vdda regulator device node @@ -90,6 +94,8 @@ Required properties: * "dsi_pll" * "dsi_phy" * "dsi_phy_regulator" +- clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating + 2 clocks: A byte clock (index 0), and a pixel clock (index 1). - qcom,dsi-phy-index: The ID of DSI PHY hardware instance. This should be 0 or 1, since we have 2 DSI PHYs at most for now. - power-domains: Should be <&mmcc MDSS_GDSC>. @@ -132,6 +138,14 @@ Example: <&mmcc MDSS_AHB_CLK>, <&mmcc MDSS_MDP_CLK>, <&mmcc MDSS_PCLK0_CLK>; + + assigned-clocks = + <&mmcc BYTE0_CLK_SRC>, + <&mmcc PCLK0_CLK_SRC>; + assigned-clock-parents = + <&dsi0_phy 0>, + <&dsi0_phy 1>; + vdda-supply = <&pma8084_l2>; vdd-supply = <&pma8084_l22>; vddio-supply = <&pma8084_l12>; @@ -195,6 +209,7 @@ Example: <0xfd922d80 0x7b>; clock-names = "iface_clk"; clocks = <&mmcc MDSS_AHB_CLK>; + #clock-cells = <1>; vddio-supply = <&pma8084_l12>; qcom,dsi-phy-regulator-ldo-mode;
The PLL in the DSI PHY block generates 2 clock outputs (Byte and Pixel clocks) that are fed into the Multimedia Clock Controller (MMCC). The MMCC uses these as source clocks for some of its RCGs to generate clocks that finally feed to the DSI host controller. Use the assigned clocks DT bindings to set up the MMCC RCGs that feed to the DSI host. Use the DSI PHY provided clocks to set up the parents of these assigned clocks. Signed-off-by: Archit Taneja <architt@codeaurora.org> --- Documentation/devicetree/bindings/display/msm/dsi.txt | 15 +++++++++++++++ 1 file changed, 15 insertions(+)