diff mbox

[v2,09/11] arm/dst: Add Aspeed ast2500 device tree

Message ID 1461225849-28074-10-git-send-email-joel@jms.id.au (mailing list archive)
State New, archived
Headers show

Commit Message

Joel Stanley April 21, 2016, 8:04 a.m. UTC 
This adds a common device tree for all fifth generation Aspeed systems,
and a board specific device tree for the ast2500 evaluation board.

Signed-off-by: Joel Stanley <joel@jms.id.au>
---
 arch/arm/boot/dts/Makefile               |   3 +-
 arch/arm/boot/dts/aspeed-ast2500-evb.dts |  21 +++++
 arch/arm/boot/dts/aspeed-g5.dtsi         | 156 +++++++++++++++++++++++++++++++
 3 files changed, 179 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/aspeed-ast2500-evb.dts
 create mode 100644 arch/arm/boot/dts/aspeed-g5.dtsi

Comments

Xo Wang May 5, 2016, 11:11 p.m. UTC | #1 
Joel Stanley <joel <at> jms.id.au> writes:
> +/ {
> +	model = "AST2500 EVB";
> +	compatible = "aspeed,ast2500";
> +
> +	chosen {
> +		stdout-path = &uart5;
> +		bootargs = "console=ttyS4,115200";
> +	};
> +
> +	memory {
> +		reg = < 0x80000000 0x10000000 >;

The AST2500 EVB has an SK Hynix H5AN4G6NMFR 4Gb part, so this should be 
0x20000000 for size.

> +			uart1: serial <at> 1e783000 {
> +				compatible = "ns16550a";
> +				reg = <0x1e783000 0x1000>;
> +				reg-shift = <2>;
> +				interrupts = <9>;
> +				clock-frequency = <1843200>;

The AST2500 datasheet 39.3.1 states the input clock to their 16550 IP is 
24 MHz. Their u-boot code also has #define CONFIG_SYS_NS16550_CLK 
24000000. I suspect we hit a path in the serial/8250 driver that doesn't 
change the divisor from what u-boot set, which is why this has worked.

Thanks for the porting work!

cheers
//xo
Joel Stanley May 6, 2016, 7:28 a.m. UTC | #2 
On Fri, May 6, 2016 at 8:41 AM, Xo Wang <xow@google.com> wrote:
> Joel Stanley <joel <at> jms.id.au> writes:
>> +/ {
>> +     model = "AST2500 EVB";
>> +     compatible = "aspeed,ast2500";
>> +
>> +     chosen {
>> +             stdout-path = &uart5;
>> +             bootargs = "console=ttyS4,115200";
>> +     };
>> +
>> +     memory {
>> +             reg = < 0x80000000 0x10000000 >;
>
> The AST2500 EVB has an SK Hynix H5AN4G6NMFR 4Gb part, so this should be
> 0x20000000 for size.

Well caught. I've got a different part on my v1.1 board, but it is also 4Gbit.

>
>> +                     uart1: serial <at> 1e783000 {
>> +                             compatible = "ns16550a";
>> +                             reg = <0x1e783000 0x1000>;
>> +                             reg-shift = <2>;
>> +                             interrupts = <9>;
>> +                             clock-frequency = <1843200>;
>
> The AST2500 datasheet 39.3.1 states the input clock to their 16550 IP is
> 24 MHz. Their u-boot code also has #define CONFIG_SYS_NS16550_CLK
> 24000000. I suspect we hit a path in the serial/8250 driver that doesn't
> change the divisor from what u-boot set, which is why this has worked.

You're correct, we are relying on uboot. There's also a tricky 'div13'
register in the SCU that we are setting in our board file for these
numbers to work out.

In V3 I've added a clk driver to take are of these details.

>
> Thanks for the porting work!

Thanks for the review. Did you manage to get these patches booting on
your board?

Cheers,

Joel
diff mbox

Patch

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index dee3a92cbd3c..98251828883f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -839,7 +839,8 @@  dtb-$(CONFIG_ARCH_MEDIATEK) += \
 	mt8127-moose.dtb \
 	mt8135-evbp1.dtb
 dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
-dtb-$(CONFIG_ARCH_ASPEED) += aspeed-bmc-opp-palmetto.dtb
+dtb-$(CONFIG_ARCH_ASPEED) += aspeed-bmc-opp-palmetto.dtb \
+	aspeed-ast2500-evb.dtb
 endif
 
 dtstree		:= $(srctree)/$(src)
diff --git a/arch/arm/boot/dts/aspeed-ast2500-evb.dts b/arch/arm/boot/dts/aspeed-ast2500-evb.dts
new file mode 100644
index 000000000000..24f2b60ed2fd
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-ast2500-evb.dts
@@ -0,0 +1,21 @@ 
+/dts-v1/;
+
+#include "aspeed-g5.dtsi"
+
+/ {
+	model = "AST2500 EVB";
+	compatible = "aspeed,ast2500";
+
+	chosen {
+		stdout-path = &uart5;
+		bootargs = "console=ttyS4,115200";
+	};
+
+	memory {
+		reg = < 0x80000000 0x10000000 >;
+	};
+};
+
+&uart5 {
+	status = "okay";
+};
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
new file mode 100644
index 000000000000..05a5f5bf458e
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -0,0 +1,156 @@ 
+#include "skeleton.dtsi"
+
+/ {
+	model = "Aspeed BMC";
+	compatible = "aspeed,ast2500";
+	#address-cells = <1>;
+	#size-cells = <1>;
+	interrupt-parent = <&vic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			compatible = "arm,arm1176jzf-s";
+			device_type = "cpu";
+			reg = <0>;
+		};
+	};
+
+	aliases {
+		serial0 = &uart1;
+		serial1 = &uart2;
+		serial2 = &uart3;
+		serial3 = &uart4;
+		serial4 = &uart5;
+		serial5 = &uart6;
+	};
+
+	ahb {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		vic: interrupt-controller@1e6c0080 {
+			compatible = "aspeed,ast2400-vic";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			valid-sources = <0xfefff7ff 0x0807ffff>;
+			reg = <0x1e6c0080 0x80>;
+		};
+
+		apb {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			clk_clkin: clk_clkin@1e6e2070 {
+				#clock-cells = <0>;
+				compatible = "aspeed,g5-clkin-clock";
+				reg = <0x1e6e2070 0x04>;
+			};
+
+			clk_hpll: clk_hpll@1e6e2024 {
+				#clock-cells = <0>;
+				compatible = "aspeed,g5-hpll-clock";
+				reg = <0x1e6e2024 0x4>;
+				clocks = <&clk_clkin>;
+			};
+
+			clk_ahb: clk_ahb@1e6e2070 {
+				#clock-cells = <0>;
+				compatible = "aspeed,g5-ahb-clock";
+				reg = <0x1e6e2070 0x4>;
+				clocks = <&clk_hpll>;
+			};
+
+			clk_apb: clk_apb@1e6e2008 {
+				#clock-cells = <0>;
+				compatible = "aspeed,g5-apb-clock";
+				reg = <0x1e6e2008 0x4>;
+				clocks = <&clk_hpll>;
+			};
+
+			sram@1e720000 {
+				compatible = "mmio-sram";
+				reg = <0x1e720000 0x9000>;	// 36K
+			};
+
+			timer: timer@1e782000 {
+				compatible = "aspeed,ast2400-timer";
+				reg = <0x1e782000 0x90>;
+				// The moxart_timer driver registers only one
+				// interrupt and assumes it's for timer 1
+				//interrupts = <16 17 18 35 36 37 38 39>;
+				interrupts = <16>;
+				clocks = <&clk_apb>;
+			};
+
+			uart1: serial@1e783000 {
+				compatible = "ns16550a";
+				reg = <0x1e783000 0x1000>;
+				reg-shift = <2>;
+				interrupts = <9>;
+				clock-frequency = <1843200>;
+				no-loopback-test;
+				status = "disabled";
+			};
+
+			uart2: serial@1e78d000 {
+				compatible = "ns16550a";
+				reg = <0x1e78d000 0x1000>;
+				reg-shift = <2>;
+				interrupts = <32>;
+				clock-frequency = <1843200>;
+				no-loopback-test;
+				status = "disabled";
+			};
+
+			uart3: serial@1e78e000 {
+				compatible = "ns16550a";
+				reg = <0x1e78e000 0x1000>;
+				reg-shift = <2>;
+				interrupts = <33>;
+				clock-frequency = <1843200>;
+				no-loopback-test;
+				status = "disabled";
+			};
+
+			uart4: serial@1e78f000 {
+				compatible = "ns16550a";
+				reg = <0x1e78f000 0x1000>;
+				reg-shift = <2>;
+				interrupts = <34>;
+				clock-frequency = <1843200>;
+				current-speed = <115200>;
+				no-loopback-test;
+				status = "disabled";
+			};
+
+			uart5: serial@1e784000 {
+				compatible = "ns16550a";
+				reg = <0x1e784000 0x1000>;
+				reg-shift = <2>;
+				interrupts = <10>;
+				clock-frequency = <1843200>;
+				current-speed = <38400>;
+				no-loopback-test;
+				status = "disabled";
+			};
+
+			uart6: serial@1e787000 {
+				compatible = "ns16550a";
+				reg = <0x1e787000 0x1000>;
+				reg-shift = <2>;
+				interrupts = <10>;
+				clock-frequency = <1843200>;
+				current-speed = <38400>;
+				no-loopback-test;
+				status = "disabled";
+			};
+		};
+	};
+};