[52/52] target-m68k: sr/ccr cleanup

Commit Message

Laurent Vivier May 4, 2016, 9:21 p.m. UTC

Signed-off-by: Laurent Vivier <[e-mail]>
---
 target-m68k/translate.c | 35 ++++++++++++++++++-----------------
 1 file changed, 18 insertions(+), 17 deletions(-)

Comments

Richard Henderson May 6, 2016, 10:02 p.m. UTC | #1

On 05/04/2016 11:21 AM, Laurent Vivier wrote:
> Signed-off-by: Laurent Vivier <[e-mail]>
> ---
>  target-m68k/translate.c | 35 ++++++++++++++++++-----------------
>  1 file changed, 18 insertions(+), 17 deletions(-)

Can this be merged with patch 14, which is also cleaning up these same functions?


r~

Patch

diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 2d92bdd..4f3e8ca 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -2239,29 +2239,29 @@  static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only)
     set_cc_op(s, CC_OP_FLAGS);
 }
 
-static void gen_set_sr(DisasContext *s, TCGv val, int ccr_only)
+static void gen_set_sr(CPUM68KState *env, DisasContext *s, uint16_t insn,
+                       int ccr_only)
 {
-    if (ccr_only) {
-        gen_helper_set_ccr(cpu_env, val);
+    if ((insn & 0x38) == 0) {
+        if (ccr_only) {
+            gen_helper_set_ccr(cpu_env, DREG(insn, 0));
+        } else {
+            gen_helper_set_sr(cpu_env, DREG(insn, 0));
+        }
+        set_cc_op(s, CC_OP_FLAGS);
+    } else if ((insn & 0x3f) == 0x3c) {
+        uint16_t val;
+        val = read_im16(env, s);
+        gen_set_sr_im(s, val, ccr_only);
     } else {
-        gen_helper_set_sr(cpu_env, val);
+        disas_undef(env, s, insn);
     }
-    set_cc_op(s, CC_OP_FLAGS);
-}
-
-static void gen_move_to_sr(CPUM68KState *env, DisasContext *s, uint16_t insn,
-                           int ccr_only)
-{
-    TCGv src;
-
-    SRC_EA(env, src, OS_WORD, 0, NULL);
-    gen_set_sr(s, src, ccr_only);
 }
 
 
 DISAS_INSN(move_to_ccr)
 {
-    gen_move_to_sr(env, s, insn, 1);
+    gen_set_sr(env, s, insn, 1);
 }
 
 DISAS_INSN(not)
@@ -3901,7 +3901,7 @@  DISAS_INSN(move_to_sr)
         gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
         return;
     }
-    gen_move_to_sr(env, s, insn, 0);
+    gen_set_sr(env, s, insn, 0);
     gen_lookup_tb(s);
 }
 
@@ -4652,8 +4652,9 @@  DISAS_INSN(macsr_to_ccr)
 {
     TCGv tmp = tcg_temp_new();
     tcg_gen_andi_i32(tmp, QREG_MACSR, 0xf);
-    gen_set_sr(s, tmp, 1);
+    gen_helper_set_sr(cpu_env, tmp);
     tcg_temp_free(tmp);
+    set_cc_op(s, CC_OP_FLAGS);
 }
 
 DISAS_INSN(to_mac)