| Message ID | 1463473149-5876-7-git-send-email-zhi.a.wang@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, May 17, 2016 at 04:19:06AM -0400, Zhi Wang wrote: > Previously the addressing mode bit in context descriptor is generated from > context PPGTT. As we allow context could be used without PPGTT, and we > still need to know the addressing mode during context submission, a flag > is introduced. > > And the addressing mode bit will be generated from this flag. > > v5: > > - Change USES_FULL_48BIT(dev) to USES_FULL_48BIT(dev_priv) (Tvrtko) > > Signed-off-by: Zhi Wang <zhi.a.wang@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h | 1 + > drivers/gpu/drm/i915/i915_gem_context.c | 2 ++ > drivers/gpu/drm/i915/intel_lrc.c | 9 +++++---- > 3 files changed, 8 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index cc83f2d..91f69e5 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -884,6 +884,7 @@ struct intel_context { > bool initialised; > } engine[I915_NUM_ENGINES]; > u32 ring_buffer_size; > + bool use_48bit_addressing_mode; A whole bool? You could put the desc.addressing_mode in there! -Chris
But the corresponding definition about desc.addressing_mode is in intel_lrc.c. And when we want to generate these bits in i915_gem_context.c we can't not reference them. Do you want me to move
define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
#define GEN8_CTX_ADDRESSING_MODE(ctx) \
(ctx->use_48bit_address_space_mode ? \
LEGACY_64B_CONTEXT :\
LEGACY_32B_CONTEXT)
to intel_lrc.h?
Thanks,
Zhi.
> -----Original Message-----
> From: Chris Wilson [mailto:chris@chris-wilson.co.uk]
> Sent: Friday, May 20, 2016 3:04 PM
> To: Wang, Zhi A <zhi.a.wang@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; tvrtko.ursulin@linux.intel.com;
> joonas.lahtinen@linux.intel.com; Tian, Kevin <kevin.tian@intel.com>; Lv,
> Zhiyuan <zhiyuan.lv@intel.com>
> Subject: Re: [PATCH 6/9] drm/i915: Generate addressing mode bit from flag in
> context.
>
> On Tue, May 17, 2016 at 04:19:06AM -0400, Zhi Wang wrote:
> > Previously the addressing mode bit in context descriptor is generated
> > from context PPGTT. As we allow context could be used without PPGTT,
> > and we still need to know the addressing mode during context
> > submission, a flag is introduced.
> >
> > And the addressing mode bit will be generated from this flag.
> >
> > v5:
> >
> > - Change USES_FULL_48BIT(dev) to USES_FULL_48BIT(dev_priv) (Tvrtko)
> >
> > Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > drivers/gpu/drm/i915/i915_gem_context.c | 2 ++
> > drivers/gpu/drm/i915/intel_lrc.c | 9 +++++----
> > 3 files changed, 8 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h index cc83f2d..91f69e5 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -884,6 +884,7 @@ struct intel_context {
> > bool initialised;
> > } engine[I915_NUM_ENGINES];
> > u32 ring_buffer_size;
> > + bool use_48bit_addressing_mode;
>
> A whole bool? You could put the desc.addressing_mode in there!
> -Chris
>
> --
> Chris Wilson, Intel Open Source Technology Centre
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index cc83f2d..91f69e5 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -884,6 +884,7 @@ struct intel_context { bool initialised; } engine[I915_NUM_ENGINES]; u32 ring_buffer_size; + bool use_48bit_addressing_mode; struct list_head link; }; diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 2aedd18..057e2fe 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -339,6 +339,8 @@ i915_gem_create_context(struct drm_device *dev, ctx->ppgtt = ppgtt; } + ctx->use_48bit_addressing_mode = USES_FULL_48BIT_PPGTT(dev_priv); + trace_i915_context_create(ctx); return ctx; diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index d52c806..d97623f 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -214,7 +214,8 @@ enum { LEGACY_64B_CONTEXT }; #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3 -#define GEN8_CTX_ADDRESSING_MODE(dev) (USES_FULL_48BIT_PPGTT(dev) ?\ +#define GEN8_CTX_ADDRESSING_MODE(ctx) \ + (ctx->use_48bit_addressing_mode ? \ LEGACY_64B_CONTEXT :\ LEGACY_32B_CONTEXT) enum { @@ -281,8 +282,6 @@ logical_ring_init_platform_invariants(struct intel_engine_cs *engine) (engine->id == VCS || engine->id == VCS2); engine->ctx_desc_template = GEN8_CTX_VALID; - engine->ctx_desc_template |= GEN8_CTX_ADDRESSING_MODE(dev_priv) << - GEN8_CTX_ADDRESSING_MODE_SHIFT; if (IS_GEN8(dev_priv)) engine->ctx_desc_template |= GEN8_CTX_L3LLC_COHERENT; engine->ctx_desc_template |= GEN8_CTX_PRIVILEGE; @@ -325,8 +324,10 @@ intel_lr_context_descriptor_update(struct intel_context *ctx, BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (1<<GEN8_CTX_ID_WIDTH)); desc = engine->ctx_desc_template; /* bits 0-11 */ + desc |= GEN8_CTX_ADDRESSING_MODE(ctx) << /* bits 3-4 */ + GEN8_CTX_ADDRESSING_MODE_SHIFT; desc |= ctx->engine[engine->id].lrc_vma->node.start + /* bits 12-31 */ - LRC_PPHWSP_PN * PAGE_SIZE; + LRC_PPHWSP_PN * PAGE_SIZE; desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT; /* bits 32-52 */ ctx->engine[engine->id].lrc_desc = desc;
Previously the addressing mode bit in context descriptor is generated from context PPGTT. As we allow context could be used without PPGTT, and we still need to know the addressing mode during context submission, a flag is introduced. And the addressing mode bit will be generated from this flag. v5: - Change USES_FULL_48BIT(dev) to USES_FULL_48BIT(dev_priv) (Tvrtko) Signed-off-by: Zhi Wang <zhi.a.wang@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_gem_context.c | 2 ++ drivers/gpu/drm/i915/intel_lrc.c | 9 +++++---- 3 files changed, 8 insertions(+), 4 deletions(-)