| Message ID | 20160524171856.1000-2-bobby.prani@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 24 May 2016 at 18:18, Pranith Kumar <bobby.prani@gmail.com> wrote: > This commit introduces the TCGOpcode for fence instruction. > > Signed-off-by: Pranith Kumar <bobby.prani@gmail.com> > --- > tcg/i386/tcg-target.inc.c | 4 ++++ > tcg/tcg-opc.h | 2 ++ > tcg/tcg.c | 2 ++ > 3 files changed, 8 insertions(+) Since this is a new TCG op, can we have it documented in tcg/README, please? This should describe the semantics of the operation in enough detail that: * a new TCG backend can implement it correctly * a TCG frontend knows when it needs to use the op thanks -- PMM
On Tue, May 24, 2016 at 1:32 PM, Peter Maydell <peter.maydell@linaro.org> wrote: > > Since this is a new TCG op, can we have it documented > in tcg/README, please? This should describe the semantics of > the operation in enough detail that: > * a new TCG backend can implement it correctly > * a TCG frontend knows when it needs to use the op > Sure, I will add this information. Thanks!
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 8fd37f4..238fa10 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -2114,6 +2114,8 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; + case INDEX_op_fence: + break; case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ @@ -2179,6 +2181,8 @@ static const TCGTargetOpDef x86_op_defs[] = { { INDEX_op_add2_i32, { "r", "r", "0", "1", "ri", "ri" } }, { INDEX_op_sub2_i32, { "r", "r", "0", "1", "ri", "ri" } }, + { INDEX_op_fence, { } }, + #if TCG_TARGET_REG_BITS == 32 { INDEX_op_brcond2_i32, { "r", "r", "ri", "ri" } }, { INDEX_op_setcond2_i32, { "r", "r", "r", "ri", "ri" } }, diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h index 6d0410c..4696cf1 100644 --- a/tcg/tcg-opc.h +++ b/tcg/tcg-opc.h @@ -42,6 +42,8 @@ DEF(br, 0, 0, 1, TCG_OPF_BB_END) # define IMPL64 TCG_OPF_64BIT #endif +DEF(fence, 0, 0, 0, 0) + DEF(mov_i32, 1, 1, 0, TCG_OPF_NOT_PRESENT) DEF(movi_i32, 1, 0, 1, TCG_OPF_NOT_PRESENT) DEF(setcond_i32, 1, 2, 1, 0) diff --git a/tcg/tcg.c b/tcg/tcg.c index b46bf1a..b5a22ba 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -2443,6 +2443,8 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) tcg_reg_alloc_call(s, op->callo, op->calli, args, dead_args, sync_args); break; + case INDEX_op_fence: + break; default: /* Sanity check that we've not introduced any unhandled opcodes. */ if (def->flags & TCG_OPF_NOT_PRESENT) {
This commit introduces the TCGOpcode for fence instruction. Signed-off-by: Pranith Kumar <bobby.prani@gmail.com> --- tcg/i386/tcg-target.inc.c | 4 ++++ tcg/tcg-opc.h | 2 ++ tcg/tcg.c | 2 ++ 3 files changed, 8 insertions(+)