[v3,1/3] arm64: dts: r8a7796: Add Renesas R8A7796 SoC support

Commit Message

Dirk Behme May 25, 2016, 7:32 a.m. UTC

On 25.05.2016 07:10, Dirk Behme wrote:
> Hi Simon,
>
> On 25.05.2016 02:48, Simon Horman wrote:
>> Hi Dirk,
>>
>> On Tue, May 24, 2016 at 07:30:17AM +0200, Dirk Behme wrote:
>>> Hi Simon,
>>
>> [...]
>>
>>> With Renesas R-Car3 we will get a whole family of SoCs. I.e. different
>>> computing power (e.g. different number of Cores) with more or less
>>> similar
>>> peripherals.
>>>
>>> I would think that we want to reflect this in the device tree, too.
>>> Therefore I think what we want is a hierarchy of device trees. Similar
>>> what's done with other SoC families (compare e.g. i.MX6).
>>>
>>> E.g. we want an initial rcar3.dtsi, which contains all common parts
>>> of all
>>> R-Car3 SoCs. E.g. one CA57 core, the SCIF where its common etc.
>>>
>>> Then you will have the r8a779x.dtsi which includes the rcar3.dtsi and
>>> extends it for SoC specific parts. Which then will be included by the
>>> board
>>> device trees, as already done, now.
>>>
>>> Or in other words: As soon as you have similar parts in the
>>> r8a779x.dtsi's,
>>> it's time to think about moving the parts one hierarchy level up into
>>> the
>>> rcar3.dtsi. Else you will end up in a maintenance hell once you have to
>>> change/fix anything.
>>
>> Thanks for raising this issue.
>>
>> I agree entirely that we should work towards a situation where
>> maintenance
>> is as easy as it can be. However, due to the per-SoC binding scheme that
>> we are using for IP related to Renesas SoCs I suspect that very few DT
>> nodes
>> can be shared between SoCs verbatim.
>
>
> Could you kindly share an example for this? Looking into the H3 and the
> M3-W manual, it looks to me that ~90% (?) of the peripherals are the same.
>
>
>> Probably some sort of scheme can be cooked up using preprocessor macros.
>> And probably there are other ways to resolve this problem. But I would
>> prefer if we worked towards resolving this maintenance problem in
>> parallel
>> with rather than as a dependency of merging r8a7796 support into
>> mainline.
>
>
> I'd propose to do it correct from the beginning.
>
> Doing it later would either be more work or forgotten, and never be
> done, then.
>
> For a starting point, I'd propose to put the r8a7795.dtsi and
> r8a7796.dtsi into a graphical diff tool and move all common parts to a
> rcar3.dtsi (I'd be happy to discuss the name, though)


To give an example what I'm talking about kindly have a look to the 
attached (draft) patch.

Best regards

Dirk

P.S.: This also results in the question why we need similar 
r8a7795-cpg-mssr.h and r8a7796-cpg-mssr.h with just different "numbers" 
for the same clocks. Can't we use the same numbers on all SoCs, with 
just having wholes in the list where the clocks don't exist on a SoC? I 
haven't looked into the manual if these numbers are given by the 
hardware, though.
From 08078bf12780176ab116fe5f39a378f5ee374ae3 Mon Sep 17 00:00:00 2001
From: Dirk Behme <[e-mail]>
Date: Wed, 25 May 2016 09:23:58 +0200
Subject: [PATCH] arm64: dts: Renesas R-Car3: Introduce common rcar3.dtsi

The R-Car3 SoC family will contain several similar SoCs, sharing
several peripherals.

Introduce a common rcar3.dtsi containing the common parts of all
R-Car3 family SoCs.

Signed-off-by: Dirk Behme <[e-mail]>
---
 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 109 ++----------------------------
 arch/arm64/boot/dts/renesas/r8a7796.dtsi | 109 ++----------------------------
 arch/arm64/boot/dts/renesas/rcar3.dtsi   | 112 +++++++++++++++++++++++++++++++
 3 files changed, 125 insertions(+), 205 deletions(-)
 create mode 100644 arch/arm64/boot/dts/renesas/rcar3.dtsi

Comments

Geert Uytterhoeven May 26, 2016, 7:03 a.m. UTC | #1

Hi Dirk,

On Wed, May 25, 2016 at 9:32 AM, Dirk Behme <[e-mail]> wrote:
> P.S.: This also results in the question why we need similar
> r8a7795-cpg-mssr.h and r8a7796-cpg-mssr.h with just different "numbers" for
> the same clocks. Can't we use the same numbers on all SoCs, with just having
> wholes in the list where the clocks don't exist on a SoC? I haven't looked

The CPG and MSSR block are the IP blocks that differ most among SoCs of the
same family. Some clocks are present on H3 only, others on M3-W only.

Having a shared driver core, but different defines, is a compromise between
reusability and avoiding mistakes in DTSes (e.g. pointing to a nonexisting
clock due to copy and paste from another SoC).

> into the manual if these numbers are given by the hardware, though.

The actual numbers don't map to numbers in the datasheet, just to an unordered
list in a table. The list of number is considered part of the DT bindings, and
thus append-only (to be considered in case the datasheet is updated).

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [e-mail]

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Dirk Behme May 26, 2016, 7:32 a.m. UTC | #2

On 26.05.2016 09:03, Geert Uytterhoeven wrote:
> Hi Dirk,
>
> On Wed, May 25, 2016 at 9:32 AM, Dirk Behme <[e-mail]> wrote:
>> P.S.: This also results in the question why we need similar
>> r8a7795-cpg-mssr.h and r8a7796-cpg-mssr.h with just different "numbers" for
>> the same clocks. Can't we use the same numbers on all SoCs, with just having
>> wholes in the list where the clocks don't exist on a SoC? I haven't looked
>
> The CPG and MSSR block are the IP blocks that differ most among SoCs of the
> same family. Some clocks are present on H3 only, others on M3-W only.


Yes, this is my understanding as well. Is the H3 a superset? And the 
M3-W drops some clocks? Or are there really clocks which are on M3-W 
only and not on H3?


> Having a shared driver core, but different defines, is a compromise between
> reusability and avoiding mistakes in DTSes (e.g. pointing to a nonexisting
> clock due to copy and paste from another SoC).


Sounds like this is a nice additional argument to don't do all this copy 
& paste and have a common rcar3.dtsi, instead :)


>> into the manual if these numbers are given by the hardware, though.
>
> The actual numbers don't map to numbers in the datasheet, just to an unordered
> list in a table. The list of number is considered part of the DT bindings, and
> thus append-only (to be considered in case the datasheet is updated).


Ok, then there should be the option to find a clever way to define the 
clocks common on all SoCs only once. And the clocks which are different 
somehow on top, then.

To take the example from

http://article.gmane.org/gmane.linux.kernel.renesas-soc/4013

this

&scif2 {
	clocks = <&cpg CPG_MOD 310>,
		 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
		 <&scif_clk>;
};

&scif2 {
	clocks = <&cpg CPG_MOD 310>,
		 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
		 <&scif_clk>;
};

should be done better.

Best regards

Dirk

Geert Uytterhoeven May 26, 2016, 8:05 a.m. UTC | #3

Hi Dirk,

On Thu, May 26, 2016 at 9:32 AM, Dirk Behme <[e-mail]> wrote:
> On 26.05.2016 09:03, Geert Uytterhoeven wrote:
>> On Wed, May 25, 2016 at 9:32 AM, Dirk Behme <[e-mail]>
>> wrote:
>>> P.S.: This also results in the question why we need similar
>>> r8a7795-cpg-mssr.h and r8a7796-cpg-mssr.h with just different "numbers"
>>> for
>>> the same clocks. Can't we use the same numbers on all SoCs, with just
>>> having
>>> wholes in the list where the clocks don't exist on a SoC? I haven't
>>> looked
>>
>> The CPG and MSSR block are the IP blocks that differ most among SoCs of
>> the
>> same family. Some clocks are present on H3 only, others on M3-W only.
>
> Yes, this is my understanding as well. Is the H3 a superset? And the M3-W
> drops some clocks? Or are there really clocks which are on M3-W only and not
> on H3?

H3 is not a superset.
M3-W e.g. has more S0Dx clocks (for x = 2, 3, 6, 8, 12).

> this
>
> &scif2 {
>         clocks = <&cpg CPG_MOD 310>,
>                  <&cpg CPG_CORE R8A7795_CLK_S3D1>,
>                  <&scif_clk>;
> };
>
> &scif2 {
>         clocks = <&cpg CPG_MOD 310>,
>                  <&cpg CPG_CORE R8A7796_CLK_S3D1>,
>                  <&scif_clk>;
> };
>
> should be done better.

That's a bad example, as both SoCs use S3D1 ;-)

Now look at e.g. i2c:
  - On H3, the parent of the i2c module clock is S3D2,
  - On M3-W, the parent of the i2c module clock is S3D2 for i2c0/1/2,
    and S0D6 for i2c3/4/5/6.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [e-mail]

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Dirk Behme May 26, 2016, 8:11 a.m. UTC | #4

Hi Geert,

On 26.05.2016 10:05, Geert Uytterhoeven wrote:
> Hi Dirk,
>
> On Thu, May 26, 2016 at 9:32 AM, Dirk Behme <[e-mail]> wrote:
>> On 26.05.2016 09:03, Geert Uytterhoeven wrote:
>>> On Wed, May 25, 2016 at 9:32 AM, Dirk Behme <[e-mail]>
>>> wrote:
>>>> P.S.: This also results in the question why we need similar
>>>> r8a7795-cpg-mssr.h and r8a7796-cpg-mssr.h with just different "numbers"
>>>> for
>>>> the same clocks. Can't we use the same numbers on all SoCs, with just
>>>> having
>>>> wholes in the list where the clocks don't exist on a SoC? I haven't
>>>> looked
>>>
>>> The CPG and MSSR block are the IP blocks that differ most among SoCs of
>>> the
>>> same family. Some clocks are present on H3 only, others on M3-W only.
>>
>> Yes, this is my understanding as well. Is the H3 a superset? And the M3-W
>> drops some clocks? Or are there really clocks which are on M3-W only and not
>> on H3?
>
> H3 is not a superset.
> M3-W e.g. has more S0Dx clocks (for x = 2, 3, 6, 8, 12).


Ok, thanks!


>> this
>>
>> &scif2 {
>>         clocks = <&cpg CPG_MOD 310>,
>>                  <&cpg CPG_CORE R8A7795_CLK_S3D1>,
>>                  <&scif_clk>;
>> };
>>
>> &scif2 {
>>         clocks = <&cpg CPG_MOD 310>,
>>                  <&cpg CPG_CORE R8A7796_CLK_S3D1>,
>>                  <&scif_clk>;
>> };
>>
>> should be done better.
>
> That's a bad example, as both SoCs use S3D1 ;-)


Then, I'd propose to find a clever way to put the common parts into a 
rcar-gen3.dtsi and ...


> Now look at e.g. i2c:
>   - On H3, the parent of the i2c module clock is S3D2,
>   - On M3-W, the parent of the i2c module clock is S3D2 for i2c0/1/2,
>     and S0D6 for i2c3/4/5/6.


... to keep the differences in the r8a7795.dtsi, r8a7796.dtsi etc.


Best regards

Dirk

Patch

diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index a7315eb..0737ed2 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -10,11 +10,10 @@ 
 
 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "rcar3.dtsi"
 
 / {
 	compatible = "renesas,r8a7795";
-	#address-cells = <2>;
-	#size-cells = <2>;
 
 	aliases {
 		i2c0 = &i2c0;
@@ -26,23 +25,7 @@ 
 		i2c6 = &i2c6;
 	};
 
-	psci {
-		compatible = "arm,psci-0.2";
-		method = "smc";
-	};
-
 	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		a57_0: cpu@0 {
-			compatible = "arm,cortex-a57", "arm,armv8";
-			reg = <0x0>;
-			device_type = "cpu";
-			next-level-cache = <&L2_CA57>;
-			enable-method = "psci";
-		};
-
 		a57_1: cpu@1 {
 			compatible = "arm,cortex-a57","arm,armv8";
 			reg = <0x1>;
@@ -66,32 +49,12 @@ 
 		};
 	};
 
-	L2_CA57: cache-controller@0 {
-		compatible = "cache";
-		cache-unified;
-		cache-level = <2>;
-	};
-
 	L2_CA53: cache-controller@1 {
 		compatible = "cache";
 		cache-unified;
 		cache-level = <2>;
 	};
 
-	extal_clk: extal {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		/* This value must be overridden by the board */
-		clock-frequency = <0>;
-	};
-
-	extalr_clk: extalr {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		/* This value must be overridden by the board */
-		clock-frequency = <0>;
-	};
-
 	/*
 	 * The external audio clocks are configured as 0 Hz fixed frequency
 	 * clocks by default.
@@ -115,35 +78,7 @@ 
 		clock-frequency = <0>;
 	};
 
-	/* External SCIF clock - to be overridden by boards that provide it */
-	scif_clk: scif {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <0>;
-		status = "disabled";
-	};
-
 	soc {
-		compatible = "simple-bus";
-		interrupt-parent = <&gic>;
-
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
-
-		gic: interrupt-controller@0xf1010000 {
-			compatible = "arm,gic-400";
-			#interrupt-cells = <3>;
-			#address-cells = <0>;
-			interrupt-controller;
-			reg = <0x0 0xf1010000 0 0x1000>,
-			      <0x0 0xf1020000 0 0x2000>,
-			      <0x0 0xf1040000 0 0x20000>,
-			      <0x0 0xf1060000 0 0x2000>;
-			interrupts = <GIC_PPI 9
-					(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
-		};
-
 		gpio0: gpio@e6050000 {
 			compatible = "renesas,gpio-r8a7795",
 				     "renesas,gpio-rcar";
@@ -268,27 +203,6 @@ 
 					     <&a57_3>;
 		};
 
-		timer {
-			compatible = "arm,armv8-timer";
-			interrupts = <GIC_PPI 13
-					(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-				     <GIC_PPI 14
-					(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-				     <GIC_PPI 11
-					(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-				     <GIC_PPI 10
-					(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
-		};
-
-		cpg: clock-controller@e6150000 {
-			compatible = "renesas,r8a7795-cpg-mssr";
-			reg = <0 0xe6150000 0 0x1000>;
-			clocks = <&extal_clk>, <&extalr_clk>;
-			clock-names = "extal", "extalr";
-			#clock-cells = <2>;
-			#power-domain-cells = <0>;
-		};
-
 		audma0: dma-controller@ec700000 {
 			compatible = "renesas,rcar-dmac";
 			reg = <0 0xec700000 0 0x10000>;
@@ -625,21 +539,6 @@ 
 			status = "disabled";
 		};
 
-		scif2: serial@e6e88000 {
-			compatible = "renesas,scif-r8a7795",
-				     "renesas,rcar-gen3-scif", "renesas,scif";
-			reg = <0 0xe6e88000 0 64>;
-			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cpg CPG_MOD 310>,
-				 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
-				 <&scif_clk>;
-			clock-names = "fck", "brg_int", "scif_clk";
-			dmas = <&dmac1 0x13>, <&dmac1 0x12>;
-			dma-names = "tx", "rx";
-			power-domains = <&cpg>;
-			status = "disabled";
-		};
-
 		scif3: serial@e6c50000 {
 			compatible = "renesas,scif-r8a7795",
 				     "renesas,rcar-gen3-scif", "renesas,scif";
@@ -1120,3 +1019,9 @@ 
 		};
 	};
 };
+
+&scif2 {
+	clocks = <&cpg CPG_MOD 310>,
+		 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
+		 <&scif_clk>;
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index 178debf..3e480d9 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -10,111 +10,14 @@ 
 
 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "rcar3.dtsi"
 
 / {
 	compatible = "renesas,r8a7796";
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	psci {
-		compatible = "arm,psci-0.2";
-		method = "smc";
-	};
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		/* 1 core only at this point */
-		a57_0: cpu@0 {
-			compatible = "arm,cortex-a57", "arm,armv8";
-			reg = <0x0>;
-			device_type = "cpu";
-			next-level-cache = <&L2_CA57>;
-			enable-method = "psci";
-		};
-
-		L2_CA57: cache-controller@0 {
-			compatible = "cache";
-			reg = <0>;
-			cache-unified;
-			cache-level = <2>;
-		};
-	};
-
-	extal_clk: extal {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		/* This value must be overridden by the board */
-		clock-frequency = <0>;
-	};
-
-	extalr_clk: extalr {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		/* This value must be overridden by the board */
-		clock-frequency = <0>;
-	};
-
-	/* External SCIF clock - to be overridden by boards that provide it */
-	scif_clk: scif {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <0>;
-	};
-
-	soc {
-		compatible = "simple-bus";
-		interrupt-parent = <&gic>;
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
-
-		gic: interrupt-controller@f1010000 {
-			compatible = "arm,gic-400";
-			#interrupt-cells = <3>;
-			#address-cells = <0>;
-			interrupt-controller;
-			reg = <0x0 0xf1010000 0 0x1000>,
-			      <0x0 0xf1020000 0 0x20000>,
-			      <0x0 0xf1040000 0 0x20000>,
-			      <0x0 0xf1060000 0 0x20000>;
-			interrupts = <GIC_PPI 9
-					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
-		};
-
-		timer {
-			compatible = "arm,armv8-timer";
-			interrupts = <GIC_PPI 13
-					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
-				     <GIC_PPI 14
-					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
-				     <GIC_PPI 11
-					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
-				     <GIC_PPI 10
-					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
-		};
-
-		cpg: clock-controller@e6150000 {
-			compatible = "renesas,r8a7796-cpg-mssr";
-			reg = <0 0xe6150000 0 0x1000>;
-			clocks = <&extal_clk>, <&extalr_clk>;
-			clock-names = "extal", "extalr";
-			#clock-cells = <2>;
-			#power-domain-cells = <0>;
-		};
+};
 
-		scif2: serial@e6e88000 {
-			compatible = "renesas,scif-r8a7796",
-				     "renesas,rcar-gen3-scif", "renesas,scif";
-			reg = <0 0xe6e88000 0 64>;
-			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cpg CPG_MOD 310>,
-				 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
-				 <&scif_clk>;
-			clock-names = "fck", "brg_int", "scif_clk";
-			power-domains = <&cpg>;
-			status = "disabled";
-		};
-	};
+&scif2 {
+	clocks = <&cpg CPG_MOD 310>,
+		 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
+		 <&scif_clk>;
 };
diff --git a/arch/arm64/boot/dts/renesas/rcar3.dtsi b/arch/arm64/boot/dts/renesas/rcar3.dtsi
new file mode 100644
index 0000000..c02c8e4
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/rcar3.dtsi
@@ -0,0 +1,112 @@ 
+/*
+ * Device Tree Source for the R-Car3 SoC family
+ *
+ * Copyright (C) 2015-2016 Renesas Electronics Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		a57_0: cpu@0 {
+			compatible = "arm,cortex-a57", "arm,armv8";
+			reg = <0x0>;
+			device_type = "cpu";
+			next-level-cache = <&L2_CA57>;
+			enable-method = "psci";
+		};
+	};
+
+	L2_CA57: cache-controller@0 {
+		compatible = "cache";
+		cache-unified;
+		cache-level = <2>;
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	extal_clk: extal {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+	};
+
+	extalr_clk: extalr {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+	};
+
+	/* External SCIF clock - to be overridden by boards that provide it */
+	scif_clk: scif {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <0>;
+		status = "disabled";
+	};
+
+	soc {
+		compatible = "simple-bus";
+		interrupt-parent = <&gic>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		gic: interrupt-controller@f1010000 {
+			compatible = "arm,gic-400";
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+			interrupt-controller;
+			reg = <0x0 0xf1010000 0 0x1000>,
+			      <0x0 0xf1020000 0 0x20000>,
+			      <0x0 0xf1040000 0 0x20000>,
+			      <0x0 0xf1060000 0 0x20000>;
+			interrupts = <GIC_PPI 9
+					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+		};
+
+		timer {
+			compatible = "arm,armv8-timer";
+			interrupts = <GIC_PPI 13
+					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+				     <GIC_PPI 14
+					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+				     <GIC_PPI 11
+					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+				     <GIC_PPI 10
+					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+		};
+
+		cpg: clock-controller@e6150000 {
+			compatible = "renesas,r8a7795-cpg-mssr", "renesas,r8a7796-cpg-mssr";
+			reg = <0 0xe6150000 0 0x1000>;
+			clocks = <&extal_clk>, <&extalr_clk>;
+			clock-names = "extal", "extalr";
+			#clock-cells = <2>;
+			#power-domain-cells = <0>;
+		};
+
+		scif2: serial@e6e88000 {
+			compatible = "renesas,scif-r8a7795", "renesas,scif-r8a7796",
+				     "renesas,rcar-gen3-scif", "renesas,scif";
+			reg = <0 0xe6e88000 0 64>;
+			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+	};
+};