| Message ID | 1464601951-25318-1-git-send-email-sagar.a.kamble@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Mon, May 30, 2016 at 03:22:31PM +0530, Sagar Arun Kamble wrote: > On Loading, GuC sets PM interrupts routing (bit 31) and unmasks ARAT > expired interrupt (bit 9). Host turbo also updates this register > in RPS flows. This patch ensures bit 31 and bit 9 setup by GuC persists. > ARAT timer interrupt is needed in GuC for various features. It also > facilitates halting GuC and hence achieving RC6. PM interrupt routing > will not impact RPS interrupt reception by host as GuC will redirect > them. > This patch fixes igt test pm_rc6_residency. Tested with SKL GuC v6.1 > and BXT GuC v5.1 and v8.7. i915_irq/intel_pm do not want to be mucking around inside intel_guc. Move the mask to dev_priv->rps, have it initialised during early irq setup and modify the mask when guc loads (presumably also triggering a resanitize just in case). -Chris
Warnings are not related to the patch. Kindly push this patch. Have filed bug for IVB warnings: https://bugs.freedesktop.org/show_bug.cgi?id=96293 For SKL warnings there is already a bug: https://bugs.freedesktop.org/show_bug.cgi?id=95632 Thanks Sagar On 5/31/2016 5:08 PM, Patchwork wrote: > == Series Details == > > Series: series starting with [v4,1/1] drm/i915: Update GEN6_PMINTRMSK setup with GuC enabled (rev5) > URL : https://patchwork.freedesktop.org/series/7972/ > State : warning > > == Summary == > > Series 7972v5 Series without cover letter > http://patchwork.freedesktop.org/api/1.0/series/7972/revisions/5/mbox > > Test gem_busy: > Subgroup basic-parallel-bsd: > pass -> DMESG-WARN (ro-ivb2-i7-3770) > Test gem_close_race: > Subgroup basic-process: > dmesg-warn -> PASS (ro-skl-i7-6700hq) > Test gem_cs_tlb: > Subgroup basic-default: > pass -> DMESG-WARN (ro-skl-i7-6700hq) > Test gem_ctx_exec: > Subgroup basic: > pass -> DMESG-WARN (ro-ivb2-i7-3770) > Test gem_exec_basic: > Subgroup readonly-render: > dmesg-warn -> PASS (ro-ivb2-i7-3770) > Test gem_exec_flush: > Subgroup basic-wb-pro-default: > pass -> DMESG-WARN (ro-skl-i7-6700hq) > Test gem_exec_store: > Subgroup basic-blt: > dmesg-warn -> PASS (ro-ivb2-i7-3770) > Subgroup basic-default: > dmesg-warn -> PASS (ro-ivb2-i7-3770) > Test gem_exec_suspend: > Subgroup basic: > pass -> DMESG-WARN (ro-ivb2-i7-3770) > Test gem_storedw_loop: > Subgroup basic-bsd: > dmesg-warn -> PASS (ro-skl-i7-6700hq) > Test kms_addfb_basic: > Subgroup addfb25-framebuffer-vs-set-tiling: > dmesg-warn -> PASS (ro-skl-i7-6700hq) > Subgroup addfb25-x-tiled: > dmesg-warn -> PASS (ro-skl-i7-6700hq) > Subgroup bad-pitch-1024: > dmesg-warn -> PASS (ro-skl-i7-6700hq) > Subgroup bad-pitch-63: > dmesg-warn -> PASS (ro-skl-i7-6700hq) > Subgroup bad-pitch-65536: > pass -> DMESG-WARN (ro-skl-i7-6700hq) > Subgroup bad-pitch-999: > pass -> DMESG-WARN (ro-skl-i7-6700hq) > Subgroup too-high: > dmesg-warn -> PASS (ro-skl-i7-6700hq) > Subgroup too-wide: > dmesg-warn -> PASS (ro-skl-i7-6700hq) > Test kms_flip: > Subgroup basic-flip-vs-wf_vblank: > dmesg-warn -> PASS (ro-skl-i7-6700hq) > Test kms_force_connector_basic: > Subgroup force-connector-state: > pass -> DMESG-WARN (ro-ivb2-i7-3770) > Test kms_psr_sink_crc: > Subgroup psr_basic: > dmesg-warn -> PASS (ro-skl-i7-6700hq) > > fi-bdw-i7-5557u total:102 pass:93 dwarn:0 dfail:0 fail:0 skip:8 > fi-bsw-n3050 total:209 pass:167 dwarn:0 dfail:0 fail:2 skip:40 > fi-byt-n2820 total:209 pass:168 dwarn:0 dfail:0 fail:3 skip:38 > fi-hsw-i7-4770k total:209 pass:190 dwarn:0 dfail:0 fail:0 skip:19 > fi-hsw-i7-4770r total:209 pass:186 dwarn:0 dfail:0 fail:0 skip:23 > fi-skl-i7-6700k total:209 pass:184 dwarn:0 dfail:0 fail:0 skip:25 > fi-snb-i7-2600 total:209 pass:170 dwarn:0 dfail:0 fail:0 skip:39 > ro-bdw-i5-5250u total:102 pass:93 dwarn:0 dfail:0 fail:0 skip:8 > ro-bdw-i7-5600u total:102 pass:75 dwarn:0 dfail:0 fail:0 skip:26 > ro-bsw-n3050 total:209 pass:168 dwarn:0 dfail:0 fail:2 skip:39 > ro-byt-n2820 total:209 pass:169 dwarn:0 dfail:0 fail:3 skip:37 > ro-hsw-i3-4010u total:209 pass:186 dwarn:0 dfail:0 fail:0 skip:23 > ro-hsw-i7-4770r total:102 pass:82 dwarn:0 dfail:0 fail:0 skip:19 > ro-ilk-i7-620lm total:1 pass:0 dwarn:0 dfail:0 fail:0 skip:0 > ro-ilk1-i5-650 total:204 pass:146 dwarn:0 dfail:0 fail:1 skip:57 > ro-ivb-i7-3770 total:52 pass:37 dwarn:0 dfail:0 fail:0 skip:14 > ro-ivb2-i7-3770 total:102 pass:44 dwarn:35 dfail:0 fail:0 skip:22 > ro-skl-i7-6700hq total:204 pass:177 dwarn:6 dfail:0 fail:0 skip:21 > ro-snb-i7-2620M total:102 pass:72 dwarn:0 dfail:0 fail:0 skip:29 > ro-bdw-i7-5557U failed to connect after reboot > ro-ivb-i7-3770 failed to connect after reboot > > Results at /archive/results/CI_IGT_test/RO_Patchwork_1057/ > > 031f2bb drm-intel-nightly: 2016y-05m-30d-17h-51m-33s UTC integration manifest > db75f2f drm/i915: Update GEN6_PMINTRMSK setup with GuC enabled >
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c index 169242a..4749588 100644 --- a/drivers/gpu/drm/i915/i915_guc_submission.c +++ b/drivers/gpu/drm/i915/i915_guc_submission.c @@ -941,6 +941,14 @@ void i915_guc_submission_disable(struct drm_device *dev) guc->execbuf_client = NULL; } +void i915_guc_get_pm_state(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_guc *guc = &dev_priv->guc; + + guc->pm_intr_mask = I915_READ(GEN6_PMINTRMSK); +} + void i915_guc_submission_fini(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index f0d9414..25c0b192 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -364,6 +364,8 @@ void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv) u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask) { + struct intel_guc *guc = &dev_priv->guc; + /* * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer * if GEN6_PM_UP_EI_EXPIRED is masked. @@ -373,8 +375,16 @@ u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask) if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv)) mask &= ~GEN6_PM_RP_UP_EI_EXPIRED; - if (INTEL_INFO(dev_priv)->gen >= 8) - mask &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP; + /* + * If PM interrupts are routed to GuC, Set mask for ARAT Expired + * interrupt based on mask set by GuC. + */ + if (INTEL_INFO(dev_priv)->gen >= 8) { + if (guc->pm_intr_mask & GEN8_PMINTR_REDIRECT_TO_NON_DISP) + mask &= guc->pm_intr_mask | ~GEN8_ARAT_EXPIRED_INT_MASK; + else + mask &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP; + } return mask; } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 86fbf72..98c20d7 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7030,7 +7030,8 @@ enum skl_disp_power_wells { #define VLV_RCEDATA _MMIO(0xA0BC) #define GEN6_RC6pp_THRESHOLD _MMIO(0xA0C0) #define GEN6_PMINTRMSK _MMIO(0xA168) -#define GEN8_PMINTR_REDIRECT_TO_NON_DISP (1<<31) +#define GEN8_PMINTR_REDIRECT_TO_NON_DISP (1<<31) +#define GEN8_ARAT_EXPIRED_INT_MASK (1<<9) #define VLV_PWRDWNUPCTL _MMIO(0xA294) #define GEN9_MEDIA_PG_IDLE_HYSTERESIS _MMIO(0xA0C4) #define GEN9_RENDER_PG_IDLE_HYSTERESIS _MMIO(0xA0C8) diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h index 9d79c4c..65904ab 100644 --- a/drivers/gpu/drm/i915/intel_guc.h +++ b/drivers/gpu/drm/i915/intel_guc.h @@ -135,6 +135,8 @@ struct intel_guc { uint64_t submissions[GUC_MAX_ENGINES_NUM]; uint32_t last_seqno[GUC_MAX_ENGINES_NUM]; + + uint32_t pm_intr_mask; }; /* intel_guc_loader.c */ @@ -151,6 +153,7 @@ int i915_guc_submission_enable(struct drm_device *dev); int i915_guc_submit(struct i915_guc_client *client, struct drm_i915_gem_request *rq); void i915_guc_submission_disable(struct drm_device *dev); +void i915_guc_get_pm_state(struct drm_device *dev); void i915_guc_submission_fini(struct drm_device *dev); int i915_guc_wq_check_space(struct i915_guc_client *client); diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c index 23345e1..33c6046 100644 --- a/drivers/gpu/drm/i915/intel_guc_loader.c +++ b/drivers/gpu/drm/i915/intel_guc_loader.c @@ -476,6 +476,8 @@ int intel_guc_ucode_load(struct drm_device *dev) /* The execbuf_client will be recreated. Release it first. */ i915_guc_submission_disable(dev); + i915_guc_get_pm_state(dev); + err = i915_guc_submission_enable(dev); if (err) goto fail; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index adb6463..c5e2311 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4708,6 +4708,9 @@ void gen6_rps_busy(struct drm_i915_private *dev_priv) void gen6_rps_idle(struct drm_i915_private *dev_priv) { + struct intel_guc *guc = &dev_priv->guc; + u32 mask = 0xffffffff; + mutex_lock(&dev_priv->rps.hw_lock); if (dev_priv->rps.enabled) { if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) @@ -4715,7 +4718,18 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv) else gen6_set_rps(dev_priv, dev_priv->rps.idle_freq); dev_priv->rps.last_adj = 0; - I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); + + /* + * If PM interrupts are routed to GuC, Set mask for ARAT Expired + * interrupt based on mask set by GuC. + */ + if (INTEL_INFO(dev_priv)->gen >= 8) { + if (guc->pm_intr_mask & GEN8_PMINTR_REDIRECT_TO_NON_DISP) + mask &= guc->pm_intr_mask | ~GEN8_ARAT_EXPIRED_INT_MASK; + else + mask &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP; + } + I915_WRITE(GEN6_PMINTRMSK, mask); } mutex_unlock(&dev_priv->rps.hw_lock);
On Loading, GuC sets PM interrupts routing (bit 31) and unmasks ARAT expired interrupt (bit 9). Host turbo also updates this register in RPS flows. This patch ensures bit 31 and bit 9 setup by GuC persists. ARAT timer interrupt is needed in GuC for various features. It also facilitates halting GuC and hence achieving RC6. PM interrupt routing will not impact RPS interrupt reception by host as GuC will redirect them. This patch fixes igt test pm_rc6_residency. Tested with SKL GuC v6.1 and BXT GuC v5.1 and v8.7. Cc: Chris Harris <chris.harris@intel.com> Cc: Zhe Wang <zhe1.wang@intel.com> Cc: Deepak S <deepak.s@intel.com> Cc: Satyanantha, Rama Gopal M <rama.gopal.m.satyanantha@intel.com> Cc: Akash Goel <akash.goel@intel.com> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> --- drivers/gpu/drm/i915/i915_guc_submission.c | 8 ++++++++ drivers/gpu/drm/i915/i915_irq.c | 14 ++++++++++++-- drivers/gpu/drm/i915/i915_reg.h | 3 ++- drivers/gpu/drm/i915/intel_guc.h | 3 +++ drivers/gpu/drm/i915/intel_guc_loader.c | 2 ++ drivers/gpu/drm/i915/intel_pm.c | 16 +++++++++++++++- 6 files changed, 42 insertions(+), 4 deletions(-)