| Message ID | 1464618758-20965-2-git-send-email-absahu@codeaurora.org (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Delegated to: | Stephen Boyd |
| Headers | show |
On 05/30, Abhishek Sahu wrote: > Modified the fixed clock rate initialization in the IPQ4019 clock > probe function with correct values. > > Also some of the fixed clocks entries were not added in the current > driver file so added the same. > > Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> This was a temporary solution until the PLL recalc code could be written. When is the real clk driver coming so we can get rid of these fixed rate clks being registered in this driver?
The PLLs on IPQ4019 cannot be reconfigured by design. The recommendation is to program these PLLS only once. Since, the Bootloaders configure the PLLs and clocks already. we did not support the recalc rate and marked them as fixed clocks. On 6/2/2016 3:48 AM, Stephen Boyd wrote: > This was a temporary solution until the PLL recalc code could be > written. When is the real clk driver coming so we can get rid of > these fixed rate clks being registered in this driver? -- To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 06/02, Banavathi, Pradeep wrote: > The PLLs on IPQ4019 cannot be reconfigured by design. The > recommendation is to program these PLLS only once. Since, the > Bootloaders configure the PLLs and clocks already. we did not > support the recalc rate and marked them as fixed clocks. > (Please don't top post) That doesn't matter. We recalculate PLL rates on all other qcom SoCs by reading the hardware even though an overwhelming majority of them are fixed by the bootloader.
On Thu, Jun 02, 2016 at 11:35:40AM -0700, Stephen Boyd wrote: > On 06/02, Banavathi, Pradeep wrote: > > The PLLs on IPQ4019 cannot be reconfigured by design. The > > recommendation is to program these PLLS only once. Since, the > > Bootloaders configure the PLLs and clocks already. we did not > > support the recalc rate and marked them as fixed clocks. > > > > (Please don't top post) > > That doesn't matter. We recalculate PLL rates on all other qcom > SoCs by reading the hardware even though an overwhelming majority > of them are fixed by the bootloader. > We will check for this. Already we added the APSS CPU PLL divider in clock framework in next 3 patches of this patchset. Could you please review the same so that we can follow the similar thing for other PLL and dividers. > -- > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, > a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c index 3cd1af0..db24cb8 100644 --- a/drivers/clk/qcom/gcc-ipq4019.c +++ b/drivers/clk/qcom/gcc-ipq4019.c @@ -80,7 +80,7 @@ static struct parent_map gcc_xo_sdcc1_500_map[] = { static const char * const gcc_xo_sdcc1_500[] = { "xo", - "ddrpll", + "ddrpllsdcc", "fepll500", }; @@ -1317,13 +1317,15 @@ static int gcc_ipq4019_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; - clk_register_fixed_rate(dev, "fepll125", "xo", 0, 200000000); - clk_register_fixed_rate(dev, "fepll125dly", "xo", 0, 200000000); - clk_register_fixed_rate(dev, "fepllwcss2g", "xo", 0, 200000000); - clk_register_fixed_rate(dev, "fepllwcss5g", "xo", 0, 200000000); + clk_register_fixed_rate(dev, "fepll125", "xo", 0, 125000000); + clk_register_fixed_rate(dev, "fepll125dly", "xo", 0, 125000000); + clk_register_fixed_rate(dev, "fepllwcss2g", "xo", 0, 250000000); + clk_register_fixed_rate(dev, "fepllwcss5g", "xo", 0, 250000000); clk_register_fixed_rate(dev, "fepll200", "xo", 0, 200000000); - clk_register_fixed_rate(dev, "fepll500", "xo", 0, 200000000); + clk_register_fixed_rate(dev, "fepll500", "xo", 0, 500000000); clk_register_fixed_rate(dev, "ddrpllapss", "xo", 0, 666000000); + clk_register_fixed_rate(dev, "ddrpllsdcc", "xo", 0, 193000000); + clk_register_fixed_rate(dev, "pcnoc_clk_src", "xo", 0, 100000000); return qcom_cc_probe(pdev, &gcc_ipq4019_desc); }
Modified the fixed clock rate initialization in the IPQ4019 clock probe function with correct values. Also some of the fixed clocks entries were not added in the current driver file so added the same. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> --- drivers/clk/qcom/gcc-ipq4019.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-)