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[1/7] dt-bindings: Update QorIQ TMU thermal bindings

Message ID 1464937059-19349-1-git-send-email-hongtao.jia@nxp.com (mailing list archive)
State Not Applicable, archived
Headers show

Commit Message

Jia Hongtao June 3, 2016, 6:57 a.m. UTC
For different types of SoC the sensor id and endianness may vary.
"#thermal-sensor-cells" is used to provide sensor id information.
"little-endian" property is to tell the endianness of TMU.

Signed-off-by: Jia Hongtao <hongtao.jia@nxp.com>
---
 .../devicetree/bindings/thermal/qoriq-thermal.txt     | 19 +++++++++++++------
 1 file changed, 13 insertions(+), 6 deletions(-)

Comments

Rob Herring June 6, 2016, 1:47 p.m. UTC | #1
On Fri, Jun 03, 2016 at 02:57:33PM +0800, Jia Hongtao wrote:
> For different types of SoC the sensor id and endianness may vary.
> "#thermal-sensor-cells" is used to provide sensor id information.
> "little-endian" property is to tell the endianness of TMU.
> 
> Signed-off-by: Jia Hongtao <hongtao.jia@nxp.com>
> ---
>  .../devicetree/bindings/thermal/qoriq-thermal.txt     | 19 +++++++++++++------
>  1 file changed, 13 insertions(+), 6 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
> index 66223d5..8eeef80 100644
> --- a/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
> +++ b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
> @@ -1,22 +1,28 @@
>  * Thermal Monitoring Unit (TMU) on Freescale QorIQ SoCs
>  
>  Required properties:
> -- compatible : Must include "fsl,qoriq-tmu". The version of the device is
> +- compatible: Must include "fsl,qoriq-tmu". The version of the device is

Please split functional changes from formatting changes. This one seems 
pretty pointless.

>  	determined by the TMU IP Block Revision Register (IPBRR0) at
>  	offset 0x0BF8.
> -	Table of correspondences between IPBRR0 values and example  chips:
> +	Table of correspondences between IPBRR0 values and example chips:
>  		Value           Device
>  		----------      -----
>  		0x01900102      T1040
> -- reg : Address range of TMU registers.
> -- interrupts : Contains the interrupt for TMU.
> -- fsl,tmu-range : The values to be programmed into TTRnCR, as specified by
> +- reg: Address range of TMU registers.
> +- interrupts: Contains the interrupt for TMU.
> +- fsl,tmu-range: The values to be programmed into TTRnCR, as specified by
>  	the SoC reference manual. The first cell is TTR0CR, the second is
>  	TTR1CR, etc.
> -- fsl,tmu-calibration : A list of cell pairs containing temperature
> +- fsl,tmu-calibration: A list of cell pairs containing temperature
>  	calibration data, as specified by the SoC reference manual.
>  	The first cell of each pair is the value to be written to TTCFGR,
>  	and the second is the value to be written to TSCFGR.
> +- #thermal-sensor-cells: Must be 1. The sensor specifier is the monitoring
> +	site ID, and represents the "n" in TRITSRn and TRATSRn.
> +
> +Optional property:
> +- little-endian: If present, the TMU registers are little endian.  If absent,
> +	the default is big endian.
>  
>  Example:
>  
> @@ -60,4 +66,5 @@ tmu@f0000 {
>  
>  			       0x00030000 0x00000012
>  			       0x00030001 0x0000001d>;
> +	#thermal-sensor-cells = <1>;
>  };
> -- 
> 2.1.0.27.g96db324
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
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diff mbox

Patch

diff --git a/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
index 66223d5..8eeef80 100644
--- a/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
@@ -1,22 +1,28 @@ 
 * Thermal Monitoring Unit (TMU) on Freescale QorIQ SoCs
 
 Required properties:
-- compatible : Must include "fsl,qoriq-tmu". The version of the device is
+- compatible: Must include "fsl,qoriq-tmu". The version of the device is
 	determined by the TMU IP Block Revision Register (IPBRR0) at
 	offset 0x0BF8.
-	Table of correspondences between IPBRR0 values and example  chips:
+	Table of correspondences between IPBRR0 values and example chips:
 		Value           Device
 		----------      -----
 		0x01900102      T1040
-- reg : Address range of TMU registers.
-- interrupts : Contains the interrupt for TMU.
-- fsl,tmu-range : The values to be programmed into TTRnCR, as specified by
+- reg: Address range of TMU registers.
+- interrupts: Contains the interrupt for TMU.
+- fsl,tmu-range: The values to be programmed into TTRnCR, as specified by
 	the SoC reference manual. The first cell is TTR0CR, the second is
 	TTR1CR, etc.
-- fsl,tmu-calibration : A list of cell pairs containing temperature
+- fsl,tmu-calibration: A list of cell pairs containing temperature
 	calibration data, as specified by the SoC reference manual.
 	The first cell of each pair is the value to be written to TTCFGR,
 	and the second is the value to be written to TSCFGR.
+- #thermal-sensor-cells: Must be 1. The sensor specifier is the monitoring
+	site ID, and represents the "n" in TRITSRn and TRATSRn.
+
+Optional property:
+- little-endian: If present, the TMU registers are little endian.  If absent,
+	the default is big endian.
 
 Example:
 
@@ -60,4 +66,5 @@  tmu@f0000 {
 
 			       0x00030000 0x00000012
 			       0x00030001 0x0000001d>;
+	#thermal-sensor-cells = <1>;
 };