| Message ID | 1464947790-22991-4-git-send-email-clabbe.montjoie@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Jun 03, 2016 at 11:56:28AM +0200, LABBE Corentin wrote: > This patch adds documentation for Device-Tree bindings for the > Allwinner sun8i-emac driver. > > Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com> > --- > .../bindings/net/allwinner,sun8i-emac.txt | 64 ++++++++++++++++++++++ > 1 file changed, 64 insertions(+) > create mode 100644 Documentation/devicetree/bindings/net/allwinner,sun8i-emac.txt > > diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-emac.txt b/Documentation/devicetree/bindings/net/allwinner,sun8i-emac.txt > new file mode 100644 > index 0000000..cf71a71 > --- /dev/null > +++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-emac.txt > @@ -0,0 +1,64 @@ > +* Allwinner sun8i EMAC ethernet controller > + > +Required properties: > +- compatible: "allwinner,sun8i-a83t-emac", "allwinner,sun8i-h3-emac", > + or "allwinner,sun50i-a64-emac" > +- reg: address and length of the register sets for the device. > +- reg-names: should be "emac" and "syscon", matching the register sets Is syscon shared with other devices? Your example only has 1 reg address. > +- interrupts: interrupt for the device > +- clocks: A phandle to the reference clock for this device > +- clock-names: should be "ahb" > +- resets: A phandle to the reset control for this device > +- reset-names: should be "ahb" > +- phy-mode: See ethernet.txt > +- phy or phy-handle: See ethernet.txt > +- #address-cells: shall be 1 > +- #size-cells: shall be 0 > + > +"allwinner,sun8i-h3-emac" also requires: > +- clocks: an extra phandle to the reference clock for the EPHY > +- clock-names: an extra "ephy" entry matching the clocks property > +- resets: an extra phandle to the reset control for the EPHY > +- resets-names: an extra "ephy" entry matching the resets property > + > +See ethernet.txt in the same directory for generic bindings for ethernet > +controllers. > + > +The device node referenced by "phy" or "phy-handle" should be a child node > +of this node. See phy.txt for the generic PHY bindings. > + > +Optional properties: > +- phy-supply: phandle to a regulator if the PHY needs one > +- phy-io-supply: phandle to a regulator if the PHY needs a another one for I/O. > + This is sometimes found with RGMII PHYs, which use a second > + regulator for the lower I/O voltage. These should go in the phy's node. > +- allwinner,tx-delay: The setting of the TX clock delay chain > +- allwinner,rx-delay: The setting of the RX clock delay chain > + > +The TX/RX clock delay chain settings are board specific. > + > +Optional properties for "allwinner,sun8i-h3-emac": > +- allwinner,use-internal-phy: Use the H3 SoC's internal E(thernet) PHY > +- allwinner,leds-active-low: EPHY LEDs are active low > + > +When the internal PHY is requested, the implementation shall configure the > +internal PHY to use the address specified in the child PHY node. > + > +Example: > + > +emac: ethernet@01c0b000 { > + compatible = "allwinner,sun8i-h3-emac"; > + reg = <0x01c0b000 0x1000>; > + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&bus_gates 17>, <&bus_gates 128>; > + clock-names = "ahb", "ephy"; > + resets = <&ahb_rst 17>, <&ahb_rst 66>; > + reset-names = "ahb", "ephy"; > + phy = <&phy1>; > + allwinner,use-internal-phy; > + allwinner,leds-active-low; > + > + phy1: ethernet-phy@1 { > + reg = <1>; > + }; > +}; > -- > 2.7.3 >
Le 06/06/2016 16:14, Rob Herring a écrit : > On Fri, Jun 03, 2016 at 11:56:28AM +0200, LABBE Corentin wrote: >> This patch adds documentation for Device-Tree bindings for the >> Allwinner sun8i-emac driver. >> >> Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com> >> --- >> .../bindings/net/allwinner,sun8i-emac.txt | 64 ++++++++++++++++++++++ >> 1 file changed, 64 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/net/allwinner,sun8i-emac.txt >> >> diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-emac.txt b/Documentation/devicetree/bindings/net/allwinner,sun8i-emac.txt >> new file mode 100644 >> index 0000000..cf71a71 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-emac.txt >> @@ -0,0 +1,64 @@ >> +* Allwinner sun8i EMAC ethernet controller >> + >> +Required properties: >> +- compatible: "allwinner,sun8i-a83t-emac", "allwinner,sun8i-h3-emac", >> + or "allwinner,sun50i-a64-emac" >> +- reg: address and length of the register sets for the device. >> +- reg-names: should be "emac" and "syscon", matching the register sets > > Is syscon shared with other devices? Your example only has 1 reg > address. > The example is bad, emac and syscon are two distinct regspaces. I will correct the example. >> +- interrupts: interrupt for the device >> +- clocks: A phandle to the reference clock for this device >> +- clock-names: should be "ahb" >> +- resets: A phandle to the reset control for this device >> +- reset-names: should be "ahb" >> +- phy-mode: See ethernet.txt >> +- phy or phy-handle: See ethernet.txt >> +- #address-cells: shall be 1 >> +- #size-cells: shall be 0 >> + >> +"allwinner,sun8i-h3-emac" also requires: >> +- clocks: an extra phandle to the reference clock for the EPHY >> +- clock-names: an extra "ephy" entry matching the clocks property >> +- resets: an extra phandle to the reset control for the EPHY >> +- resets-names: an extra "ephy" entry matching the resets property >> + >> +See ethernet.txt in the same directory for generic bindings for ethernet >> +controllers. >> + >> +The device node referenced by "phy" or "phy-handle" should be a child node >> +of this node. See phy.txt for the generic PHY bindings. >> + >> +Optional properties: >> +- phy-supply: phandle to a regulator if the PHY needs one >> +- phy-io-supply: phandle to a regulator if the PHY needs a another one for I/O. >> + This is sometimes found with RGMII PHYs, which use a second >> + regulator for the lower I/O voltage. > > These should go in the phy's node. > In fact, I forgot to remove them, since for the moment, the driver sent do not have any regulator support. Thanks
On Mon, Jun 06, 2016 at 08:10:54PM +0200, Corentin LABBE wrote: > Le 06/06/2016 16:14, Rob Herring a écrit : > > On Fri, Jun 03, 2016 at 11:56:28AM +0200, LABBE Corentin wrote: > >> This patch adds documentation for Device-Tree bindings for the > >> Allwinner sun8i-emac driver. > >> > >> Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com> > >> --- > >> .../bindings/net/allwinner,sun8i-emac.txt | 64 ++++++++++++++++++++++ > >> 1 file changed, 64 insertions(+) > >> create mode 100644 Documentation/devicetree/bindings/net/allwinner,sun8i-emac.txt > >> > >> diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-emac.txt b/Documentation/devicetree/bindings/net/allwinner,sun8i-emac.txt > >> new file mode 100644 > >> index 0000000..cf71a71 > >> --- /dev/null > >> +++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-emac.txt > >> @@ -0,0 +1,64 @@ > >> +* Allwinner sun8i EMAC ethernet controller > >> + > >> +Required properties: > >> +- compatible: "allwinner,sun8i-a83t-emac", "allwinner,sun8i-h3-emac", > >> + or "allwinner,sun50i-a64-emac" > >> +- reg: address and length of the register sets for the device. > >> +- reg-names: should be "emac" and "syscon", matching the register sets > > > > Is syscon shared with other devices? Your example only has 1 reg > > address. > > > > The example is bad, emac and syscon are two distinct regspaces. > I will correct the example. And the syscon registers are not shared with anything else? Typically, syscon registers would be a separate node not part of this blocks registers. The main thing is make sure you are not creating overlapping register addresses. Rob
Hi Rob, On Thu, Jun 9, 2016 at 3:11 AM, Rob Herring <robh@kernel.org> wrote: > On Mon, Jun 06, 2016 at 08:10:54PM +0200, Corentin LABBE wrote: >> Le 06/06/2016 16:14, Rob Herring a écrit : >> > On Fri, Jun 03, 2016 at 11:56:28AM +0200, LABBE Corentin wrote: >> >> This patch adds documentation for Device-Tree bindings for the >> >> Allwinner sun8i-emac driver. >> >> >> >> Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com> >> >> --- >> >> .../bindings/net/allwinner,sun8i-emac.txt | 64 ++++++++++++++++++++++ >> >> 1 file changed, 64 insertions(+) >> >> create mode 100644 Documentation/devicetree/bindings/net/allwinner,sun8i-emac.txt >> >> >> >> diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-emac.txt b/Documentation/devicetree/bindings/net/allwinner,sun8i-emac.txt >> >> new file mode 100644 >> >> index 0000000..cf71a71 >> >> --- /dev/null >> >> +++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-emac.txt >> >> @@ -0,0 +1,64 @@ >> >> +* Allwinner sun8i EMAC ethernet controller >> >> + >> >> +Required properties: >> >> +- compatible: "allwinner,sun8i-a83t-emac", "allwinner,sun8i-h3-emac", >> >> + or "allwinner,sun50i-a64-emac" >> >> +- reg: address and length of the register sets for the device. >> >> +- reg-names: should be "emac" and "syscon", matching the register sets >> > >> > Is syscon shared with other devices? Your example only has 1 reg >> > address. >> > >> >> The example is bad, emac and syscon are two distinct regspaces. >> I will correct the example. > > And the syscon registers are not shared with anything else? Typically, > syscon registers would be a separate node not part of this blocks > registers. The main thing is make sure you are not creating overlapping > register addresses. These syscon registers are in a separate address range, like a glue layer over the underlying EMAC hardware. There are only 2 registers defined in that address range, and this particular one is used only for EMAC related controls. The other register is not used anywhere in the kernel. It's a readonly register that gives the SoC revision. IIRC there was some work to add per-platform functions to support this, but we haven't the need to use it yet. Hope this clears things up. Regards ChenYu
diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-emac.txt b/Documentation/devicetree/bindings/net/allwinner,sun8i-emac.txt new file mode 100644 index 0000000..cf71a71 --- /dev/null +++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-emac.txt @@ -0,0 +1,64 @@ +* Allwinner sun8i EMAC ethernet controller + +Required properties: +- compatible: "allwinner,sun8i-a83t-emac", "allwinner,sun8i-h3-emac", + or "allwinner,sun50i-a64-emac" +- reg: address and length of the register sets for the device. +- reg-names: should be "emac" and "syscon", matching the register sets +- interrupts: interrupt for the device +- clocks: A phandle to the reference clock for this device +- clock-names: should be "ahb" +- resets: A phandle to the reset control for this device +- reset-names: should be "ahb" +- phy-mode: See ethernet.txt +- phy or phy-handle: See ethernet.txt +- #address-cells: shall be 1 +- #size-cells: shall be 0 + +"allwinner,sun8i-h3-emac" also requires: +- clocks: an extra phandle to the reference clock for the EPHY +- clock-names: an extra "ephy" entry matching the clocks property +- resets: an extra phandle to the reset control for the EPHY +- resets-names: an extra "ephy" entry matching the resets property + +See ethernet.txt in the same directory for generic bindings for ethernet +controllers. + +The device node referenced by "phy" or "phy-handle" should be a child node +of this node. See phy.txt for the generic PHY bindings. + +Optional properties: +- phy-supply: phandle to a regulator if the PHY needs one +- phy-io-supply: phandle to a regulator if the PHY needs a another one for I/O. + This is sometimes found with RGMII PHYs, which use a second + regulator for the lower I/O voltage. +- allwinner,tx-delay: The setting of the TX clock delay chain +- allwinner,rx-delay: The setting of the RX clock delay chain + +The TX/RX clock delay chain settings are board specific. + +Optional properties for "allwinner,sun8i-h3-emac": +- allwinner,use-internal-phy: Use the H3 SoC's internal E(thernet) PHY +- allwinner,leds-active-low: EPHY LEDs are active low + +When the internal PHY is requested, the implementation shall configure the +internal PHY to use the address specified in the child PHY node. + +Example: + +emac: ethernet@01c0b000 { + compatible = "allwinner,sun8i-h3-emac"; + reg = <0x01c0b000 0x1000>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bus_gates 17>, <&bus_gates 128>; + clock-names = "ahb", "ephy"; + resets = <&ahb_rst 17>, <&ahb_rst 66>; + reset-names = "ahb", "ephy"; + phy = <&phy1>; + allwinner,use-internal-phy; + allwinner,leds-active-low; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +};
This patch adds documentation for Device-Tree bindings for the Allwinner sun8i-emac driver. Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com> --- .../bindings/net/allwinner,sun8i-emac.txt | 64 ++++++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/allwinner,sun8i-emac.txt