[v5,2/4] i386: publish advised value of MSR_IA32_FEATURE_CONTROL via fw_cfg

Commit Message

Haozhong Zhang June 22, 2016, 6:56 a.m. UTC

It's a prerequisite that certain bits of MSR_IA32_FEATURE_CONTROL should
be set before some features (e.g. VMX and LMCE) can be used, which is
usually done by the firmware. This patch adds a fw_cfg file
"etc/msr_feature_control" which contains the advised value of
MSR_IA32_FEATURE_CONTROL and can be used by guest firmware (e.g. SeaBIOS).

Suggested-by: Paolo Bonzini <[e-mail]>
Signed-off-by: Haozhong Zhang <[e-mail]>
Reviewed-by: Paolo Bonzini <[e-mail]>
---
 hw/i386/pc.c      | 29 +++++++++++++++++++++++++++++
 target-i386/cpu.h |  4 ++++
 2 files changed, 33 insertions(+)

Comments

Paolo Bonzini June 22, 2016, 5:08 p.m. UTC | #1

On 22/06/2016 08:56, Haozhong Zhang wrote:
> +
> +    val = g_malloc(sizeof(*val));
> +    *val = feature_control_bits | FEATURE_CONTROL_LOCKED;

As noticed by Laszlo, you need to use cpu_to_le64 here.  The maintainer
can fix it, I think.

Paolo

> +    fw_cfg_add_file(pcms->fw_cfg, "etc/msr_feature_control", val, sizeof(*val));
> +}

Haozhong Zhang June 23, 2016, 6:08 a.m. UTC | #2

On 06/22/16 19:08, Paolo Bonzini wrote:
> 
> 
> On 22/06/2016 08:56, Haozhong Zhang wrote:
> > +
> > +    val = g_malloc(sizeof(*val));
> > +    *val = feature_control_bits | FEATURE_CONTROL_LOCKED;
> 
> As noticed by Laszlo, you need to use cpu_to_le64 here.  The maintainer
> can fix it, I think.
> 

Thanks for indicating this! I'll resend this one.

Haozhong

Patch

diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 7198ed5..2a945fd 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1147,6 +1147,34 @@  void pc_cpus_init(PCMachineState *pcms)
     smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]);
 }
 
+static void pc_build_feature_control_file(PCMachineState *pcms)
+{
+    X86CPU *cpu = X86_CPU(pcms->possible_cpus->cpus[0].cpu);
+    CPUX86State *env = &cpu->env;
+    uint32_t unused, ecx, edx;
+    uint64_t feature_control_bits = 0;
+    uint64_t *val;
+
+    cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx);
+    if (ecx & CPUID_EXT_VMX) {
+        feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
+    }
+
+    if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) ==
+        (CPUID_EXT2_MCE | CPUID_EXT2_MCA) &&
+        (env->mcg_cap & MCG_LMCE_P)) {
+        feature_control_bits |= FEATURE_CONTROL_LMCE;
+    }
+
+    if (!feature_control_bits) {
+        return;
+    }
+
+    val = g_malloc(sizeof(*val));
+    *val = feature_control_bits | FEATURE_CONTROL_LOCKED;
+    fw_cfg_add_file(pcms->fw_cfg, "etc/msr_feature_control", val, sizeof(*val));
+}
+
 static
 void pc_machine_done(Notifier *notifier, void *data)
 {
@@ -1174,6 +1202,7 @@  void pc_machine_done(Notifier *notifier, void *data)
     acpi_setup();
     if (pcms->fw_cfg) {
         pc_build_smbios(pcms->fw_cfg);
+        pc_build_feature_control_file(pcms);
     }
 }
 
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index cda3ea1..11291b6 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -332,6 +332,10 @@ 
 #define MSR_TSC_ADJUST                  0x0000003b
 #define MSR_IA32_TSCDEADLINE            0x6e0
 
+#define FEATURE_CONTROL_LOCKED                    (1<<0)
+#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
+#define FEATURE_CONTROL_LMCE                      (1<<20)
+
 #define MSR_P6_PERFCTR0                 0xc1
 
 #define MSR_IA32_SMBASE                 0x9e