| Message ID | 1467305430-25660-4-git-send-email-kieran@bingham.xyz (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Thu, Jun 30, 2016 at 05:50:30PM +0100, Kieran Bingham wrote: > The FDP1 is a de-interlacing module which converts interlaced video to > progressive video. It is also capable of performing pixel format conversion > between YCbCr/YUV formats and RGB formats. > > Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > Signed-off-by: Kieran Bingham <kieran@bingham.xyz> > --- > Changes since v1: > - title fixed > - Interrupts property documented > - version specific compatibles removed as we have a hw version register > - label removed from device node example > * (fdp1 is not referenced by other nodes) > > .../devicetree/bindings/media/renesas,fdp1.txt | 33 ++++++++++++++++++++++ > 1 file changed, 33 insertions(+) > create mode 100644 Documentation/devicetree/bindings/media/renesas,fdp1.txt Acked-by: Rob Herring <robh@kernel.org> -- To unsubscribe from this list: send the line "unsubscribe linux-media" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/Documentation/devicetree/bindings/media/renesas,fdp1.txt b/Documentation/devicetree/bindings/media/renesas,fdp1.txt new file mode 100644 index 000000000000..e6abd2a17e66 --- /dev/null +++ b/Documentation/devicetree/bindings/media/renesas,fdp1.txt @@ -0,0 +1,33 @@ +Renesas R-Car Fine Display Processor (FDP1) +------------------------------------------- + +The FDP1 is a de-interlacing module which converts interlaced video to +progressive video. It is capable of performing pixel format conversion between +YCbCr/YUV formats and RGB formats. Only YCbCr/YUV formats are supported as +an input to the module. + + - compatible: Must be the following + + - "renesas,fdp1" for generic compatible + + - reg: the register base and size for the device registers + - interrupts : interrupt specifier for the FDP1 instance + - clocks: reference to the functional clock + - renesas,fcp: reference to the FCPF connected to the FDP1 + +Optional properties: + - power-domains : power-domain property defined with a power domain specifier + to respective power domain. + + +Device node example +------------------- + + fdp1@fe940000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe940000 0 0x2400>; + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 119>; + power-domains = <&sysc R8A7795_PD_A3VP>; + renesas,fcp = <&fcpf0>; + };