| Message ID | 1467270911-10971-2-git-send-email-andi.shyti@samsung.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 06/30/2016 09:15 AM, Andi Shyti wrote: > The CLK_IGNORE_UNUSED flag has to be avoided whenever possible. In general I would rather disagree. > Use the CLK_IS_CRITICAL flag instead for critical SPI1 clocks, > which enables the clock line during boot time. > > Suggested-by: Tomasz Figa <tomasz.figa@gmail.com> > Signed-off-by: Andi Shyti <andi.shyti@samsung.com> > --- > drivers/clk/samsung/clk-exynos5433.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c > index c3a5318..1f7c4951 100644 > --- a/drivers/clk/samsung/clk-exynos5433.c > +++ b/drivers/clk/samsung/clk-exynos5433.c > @@ -1662,7 +1662,7 @@ static struct samsung_gate_clock peric_gate_clks[] __initdata = { > @@ -1677,7 +1677,7 @@ static struct samsung_gate_clock peric_gate_clks[] __initdata = { > GATE(CLK_SCLK_SPI2, "sclk_spi2", "sclk_spi2_peric", ENABLE_SCLK_PERIC, > 5, CLK_SET_RATE_PARENT, 0), > GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC, > - 4, CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), > + 4, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), As Tomasz pointed out, this should be addressed in the driver/dts, we shouldn't be patching board configurations into a per-SoC driver. Other boards may want to keep this clock disabled. What is an exact problem here, are you perhaps testing suspend to RAM? I tested my sound support patches on top of v4.7-rc1 and everything seemed to work well, I didn't notice any issues with the audio codec which was the only slave on the SPI 1 bus. Doesn't it help when you specify CLK_SCLK_SPI1 as the second clock ("spi_busclk0") of the spi_1 bus controller instead of CLK_SCLK_SPI0_PERIC? CLK_SCLK_SPI0_PERIC seem to be parent of CLK_SCLK_SPI1 so the enable state would be propagated.
Hi Sylwester, > > GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC, > > - 4, CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), > > + 4, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), > > As Tomasz pointed out, this should be addressed in the driver/dts, > we shouldn't be patching board configurations into a per-SoC driver. > Other boards may want to keep this clock disabled. The single clock lines are not configured in the exynos5433 dts, but in the drivers/clk/samsung/clk-exynos5433.c file and it's the only place where we can set the flags. > What is an exact problem here, are you perhaps testing suspend to RAM? > I tested my sound support patches on top of v4.7-rc1 and everything > seemed to work well, I didn't notice any issues with the audio codec > which was the only slave on the SPI 1 bus. Yes, because the audio codec is on SPI1 and its bus line (spi_busclk0) is CLK_SCLK_SPI1_PERIC while the CLK_SCLK_SPI1 is set as CLK_IGNORE_UNUSED. > Doesn't it help when you specify CLK_SCLK_SPI1 as the second clock > ("spi_busclk0") of the spi_1 bus controller instead of > CLK_SCLK_SPI0_PERIC? CLK_SCLK_SPI0_PERIC seem to be parent of > CLK_SCLK_SPI1 so the enable state would be propagated. nope! :( For some reasons, if you set in the DTS as spi_busclk0 the CLK_SCLK_SPI1 from cmu_peric you get a synchronus abort in the s3c64xx_spi_config (the first read performed on the device). Andi
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index c3a5318..1f7c4951 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -1662,7 +1662,7 @@ static struct samsung_gate_clock peric_gate_clks[] __initdata = { ENABLE_SCLK_PERIC, 13, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_IOCLK_SPI1, "sclk_ioclk_spi1", "ioclk_spi1_clk_in", ENABLE_SCLK_PERIC, 12, - CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_IOCLK_SPI0, "sclk_ioclk_spi0", "ioclk_spi0_clk_in", ENABLE_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_IOCLK_I2S1_BCLK, "sclk_ioclk_i2s1_bclk", @@ -1677,7 +1677,7 @@ static struct samsung_gate_clock peric_gate_clks[] __initdata = { GATE(CLK_SCLK_SPI2, "sclk_spi2", "sclk_spi2_peric", ENABLE_SCLK_PERIC, 5, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC, - 4, CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), + 4, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_UART2, "sclk_uart2", "sclk_uart2_peric",
The CLK_IGNORE_UNUSED flag has to be avoided whenever possible. Use the CLK_IS_CRITICAL flag instead for critical SPI1 clocks, which enables the clock line during boot time. Suggested-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Andi Shyti <andi.shyti@samsung.com> --- drivers/clk/samsung/clk-exynos5433.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)