| Message ID | 20160712193645.9098-7-atull@opensource.altera.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, Jul 12, 2016 at 3:36 PM, Alan Tull <atull@opensource.altera.com> wrote: > Supports Altera SOCFPGA bridges: > * fpga2sdram > * fpga2hps > * hps2fpga > * lwhps2fpga > > Allows enabling/disabling the bridges through the FPGA > Bridge Framework API functions. > > The fpga2sdram driver only supports enabling and disabling > of the ports that been configured early on. This is due to > a hardware limitation where the read, write, and command > ports on the fpga2sdram bridge can only be reconfigured > while there are no transactions to the sdram, i.e. when > running out of OCRAM before the kernel boots. > > Device tree property 'init-val' configures the driver to > enable or disable the bridge during probe. If the property > does not exist, the driver will leave the bridge in its > current state. > > Signed-off-by: Alan Tull <atull@opensource.altera.com> > Signed-off-by: Matthew Gerlach <mgerlach@altera.com> > Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> > --- > v2: Use resets instead of directly writing reset registers > v12: Bump version to align with simple-fpga-bus version > Get rid of the sysfs interface > fpga2sdram: get configuration stored in handoff register > v13: Remove unneeded WARN_ON > Change property from init-val to bridge-enable > Checkpatch cleanup > Fix email address > v14: use module_platform_driver > remove unused struct field and some #defines > don't really need exclamation points on error msgs > *const* struct fpga_bridge_ops > v15: No change in this patch for v15 of this patch set > v16: No change in this patch for v16 of this patch set > v17: No change to this patch for v17 of this patch set > v18: Eliminate need to specify reset names since only one reset > --- > drivers/fpga/Kconfig | 7 ++ > drivers/fpga/Makefile | 1 + > drivers/fpga/altera-fpga2sdram.c | 174 ++++++++++++++++++++++++++++++++ > drivers/fpga/altera-hps2fpga.c | 213 +++++++++++++++++++++++++++++++++++++++ > 4 files changed, 395 insertions(+) > create mode 100644 drivers/fpga/altera-fpga2sdram.c > create mode 100644 drivers/fpga/altera-hps2fpga.c > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig > index ec81e21..b346166 100644 > --- a/drivers/fpga/Kconfig > +++ b/drivers/fpga/Kconfig > @@ -39,6 +39,13 @@ config FPGA_BRIDGE > Say Y here if you want to support bridges connected between host > processors and FPGAs or between FPGAs. > > +config SOCFPGA_FPGA_BRIDGE > + bool "Altera SoCFPGA FPGA Bridges" > + depends on ARCH_SOCFPGA && FPGA_BRIDGE > + help > + Say Y to enable drivers for FPGA bridges for Altera SOCFPGA > + devices. > + > endif # FPGA > > endmenu > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile > index 8d746c3..e658436 100644 > --- a/drivers/fpga/Makefile > +++ b/drivers/fpga/Makefile > @@ -11,6 +11,7 @@ obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o > > # FPGA Bridge Drivers > obj-$(CONFIG_FPGA_BRIDGE) += fpga-bridge.o > +obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE) += altera-hps2fpga.o altera-fpga2sdram.o > > # High Level Interfaces > obj-$(CONFIG_FPGA_REGION) += fpga-region.o > diff --git a/drivers/fpga/altera-fpga2sdram.c b/drivers/fpga/altera-fpga2sdram.c > new file mode 100644 > index 0000000..91f4a40 > --- /dev/null > +++ b/drivers/fpga/altera-fpga2sdram.c > @@ -0,0 +1,174 @@ > +/* > + * FPGA to SDRAM Bridge Driver for Altera SoCFPGA Devices > + * > + * Copyright (C) 2013-2015 Altera Corporation, All Rights Reserved. > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms and conditions of the GNU General Public License, > + * version 2, as published by the Free Software Foundation. > + * > + * This program is distributed in the hope it will be useful, but WITHOUT > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for > + * more details. > + * > + * You should have received a copy of the GNU General Public License along with > + * this program. If not, see <http://www.gnu.org/licenses/>. > + */ > + > +/* > + * This driver manages a bridge between an FPGA and the SDRAM used by the ARM > + * host processor system (HPS). > + * > + * The bridge contains 4 read ports, 4 write ports, and 6 command ports. > + * Reconfiguring these ports requires that no SDRAM transactions occur during > + * reconfiguration. The code reconfiguring the ports cannot run out of SDRAM > + * nor can the FPGA access the SDRAM during reconfiguration. This driver does > + * not support reconfiguring the ports. The ports are configured by code > + * running out of on chip ram before Linux is started and the configuration > + * is passed in a handoff register in the system manager. > + * > + * This driver supports enabling and disabling of the configured ports, which > + * allows for safe reprogramming of the FPGA, assuming that the new FPGA image > + * uses the same port configuration. Bridges must be disabled before > + * reprogramming the FPGA and re-enabled after the FPGA has been programmed. > + */ > + > +#include <linux/fpga/fpga-bridge.h> > +#include <linux/kernel.h> > +#include <linux/mfd/syscon.h> > +#include <linux/module.h Please don't use module.h in drivers controlled by a bool Kconfig setting. THanks, Paul.
On Thu, 14 Jul 2016, Paul Gortmaker wrote: > On Tue, Jul 12, 2016 at 3:36 PM, Alan Tull <atull@opensource.altera.com> wrote: > > Supports Altera SOCFPGA bridges: > > * fpga2sdram > > * fpga2hps > > * hps2fpga > > * lwhps2fpga > > > > Allows enabling/disabling the bridges through the FPGA > > Bridge Framework API functions. > > > > The fpga2sdram driver only supports enabling and disabling > > of the ports that been configured early on. This is due to > > a hardware limitation where the read, write, and command > > ports on the fpga2sdram bridge can only be reconfigured > > while there are no transactions to the sdram, i.e. when > > running out of OCRAM before the kernel boots. > > > > Device tree property 'init-val' configures the driver to > > enable or disable the bridge during probe. If the property > > does not exist, the driver will leave the bridge in its > > current state. > > > > Signed-off-by: Alan Tull <atull@opensource.altera.com> > > Signed-off-by: Matthew Gerlach <mgerlach@altera.com> > > Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> > > --- > > v2: Use resets instead of directly writing reset registers > > v12: Bump version to align with simple-fpga-bus version > > Get rid of the sysfs interface > > fpga2sdram: get configuration stored in handoff register > > v13: Remove unneeded WARN_ON > > Change property from init-val to bridge-enable > > Checkpatch cleanup > > Fix email address > > v14: use module_platform_driver > > remove unused struct field and some #defines > > don't really need exclamation points on error msgs > > *const* struct fpga_bridge_ops > > v15: No change in this patch for v15 of this patch set > > v16: No change in this patch for v16 of this patch set > > v17: No change to this patch for v17 of this patch set > > v18: Eliminate need to specify reset names since only one reset > > --- > > drivers/fpga/Kconfig | 7 ++ > > drivers/fpga/Makefile | 1 + > > drivers/fpga/altera-fpga2sdram.c | 174 ++++++++++++++++++++++++++++++++ > > drivers/fpga/altera-hps2fpga.c | 213 +++++++++++++++++++++++++++++++++++++++ > > 4 files changed, 395 insertions(+) > > create mode 100644 drivers/fpga/altera-fpga2sdram.c > > create mode 100644 drivers/fpga/altera-hps2fpga.c > > > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig > > index ec81e21..b346166 100644 > > --- a/drivers/fpga/Kconfig > > +++ b/drivers/fpga/Kconfig > > @@ -39,6 +39,13 @@ config FPGA_BRIDGE > > Say Y here if you want to support bridges connected between host > > processors and FPGAs or between FPGAs. > > > > +config SOCFPGA_FPGA_BRIDGE > > + bool "Altera SoCFPGA FPGA Bridges" > > + depends on ARCH_SOCFPGA && FPGA_BRIDGE > > + help > > + Say Y to enable drivers for FPGA bridges for Altera SOCFPGA > > + devices. > > + > > endif # FPGA > > > > endmenu > > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile > > index 8d746c3..e658436 100644 > > --- a/drivers/fpga/Makefile > > +++ b/drivers/fpga/Makefile > > @@ -11,6 +11,7 @@ obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o > > > > # FPGA Bridge Drivers > > obj-$(CONFIG_FPGA_BRIDGE) += fpga-bridge.o > > +obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE) += altera-hps2fpga.o altera-fpga2sdram.o > > > > # High Level Interfaces > > obj-$(CONFIG_FPGA_REGION) += fpga-region.o > > diff --git a/drivers/fpga/altera-fpga2sdram.c b/drivers/fpga/altera-fpga2sdram.c > > new file mode 100644 > > index 0000000..91f4a40 > > --- /dev/null > > +++ b/drivers/fpga/altera-fpga2sdram.c > > @@ -0,0 +1,174 @@ > > +/* > > + * FPGA to SDRAM Bridge Driver for Altera SoCFPGA Devices > > + * > > + * Copyright (C) 2013-2015 Altera Corporation, All Rights Reserved. > > + * > > + * This program is free software; you can redistribute it and/or modify it > > + * under the terms and conditions of the GNU General Public License, > > + * version 2, as published by the Free Software Foundation. > > + * > > + * This program is distributed in the hope it will be useful, but WITHOUT > > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for > > + * more details. > > + * > > + * You should have received a copy of the GNU General Public License along with > > + * this program. If not, see <http://www.gnu.org/licenses/>. > > + */ > > + > > +/* > > + * This driver manages a bridge between an FPGA and the SDRAM used by the ARM > > + * host processor system (HPS). > > + * > > + * The bridge contains 4 read ports, 4 write ports, and 6 command ports. > > + * Reconfiguring these ports requires that no SDRAM transactions occur during > > + * reconfiguration. The code reconfiguring the ports cannot run out of SDRAM > > + * nor can the FPGA access the SDRAM during reconfiguration. This driver does > > + * not support reconfiguring the ports. The ports are configured by code > > + * running out of on chip ram before Linux is started and the configuration > > + * is passed in a handoff register in the system manager. > > + * > > + * This driver supports enabling and disabling of the configured ports, which > > + * allows for safe reprogramming of the FPGA, assuming that the new FPGA image > > + * uses the same port configuration. Bridges must be disabled before > > + * reprogramming the FPGA and re-enabled after the FPGA has been programmed. > > + */ > > + > > +#include <linux/fpga/fpga-bridge.h> > > +#include <linux/kernel.h> > > +#include <linux/mfd/syscon.h> > > +#include <linux/module.h > > Please don't use module.h in drivers controlled by a bool > Kconfig setting. > > THanks, > Paul. > Thanks for the feedback. Can you provide an example of what you would consider to be proper usage in the kernel? Alan
Hi Alan, On Mon, Aug 8, 2016 at 12:18 PM, atull <atull@opensource.altera.com> wrote: >> Please don't use module.h in drivers controlled by a bool >> Kconfig setting. >> >> THanks, >> Paul. >> > > Thanks for the feedback. Can you provide an example of what you > would consider to be proper usage in the kernel? I think Paul is suggesting to use static int __init alt_fpga_bridge_init(void) { platform_driver_register(&alt_fpga_bridge_driver); } device_initcall(alt_fpga_bridge_init); or better: builtin_platform_driver(&alt_fpga_bridge_driver); Like for example in: drivers/cpuidle/cpuidle-mvebu-v7.c Cheers, Moritz
[Re: [PATCH v18 6/6] ARM: socfpga: fpga bridge driver support] On 08/08/2016 (Mon 13:44) Moritz Fischer wrote: > Hi Alan, > > On Mon, Aug 8, 2016 at 12:18 PM, atull <atull@opensource.altera.com> wrote: > > >> Please don't use module.h in drivers controlled by a bool > >> Kconfig setting. > >> > >> THanks, > >> Paul. > >> > > > > Thanks for the feedback. Can you provide an example of what you > > would consider to be proper usage in the kernel? > > > I think Paul is suggesting to use > > static int __init alt_fpga_bridge_init(void) > { > platform_driver_register(&alt_fpga_bridge_driver); > } > > device_initcall(alt_fpga_bridge_init); > > or better: > > builtin_platform_driver(&alt_fpga_bridge_driver); > > Like for example in: drivers/cpuidle/cpuidle-mvebu-v7.c Yes, pretty much that -- if you have a bool Kconfig, you should be using builtin registration functions, and have no need for module.h or anything MODULE_<xyz> or any module_init/module_exit calls. An empty file containing nothing but #include <linux/module.h> will cause cpp to emit about 750k of goop, so we really should only be using it for drivers that are genuinely modular; i.e. tristate Kconfig. Thanks, Paul. -- > > Cheers, > > Moritz
On Tue, 9 Aug 2016, Paul Gortmaker wrote: > [Re: [PATCH v18 6/6] ARM: socfpga: fpga bridge driver support] On 08/08/2016 (Mon 13:44) Moritz Fischer wrote: > > > Hi Alan, > > > > On Mon, Aug 8, 2016 at 12:18 PM, atull <atull@opensource.altera.com> wrote: > > > > >> Please don't use module.h in drivers controlled by a bool > > >> Kconfig setting. > > >> > > >> THanks, > > >> Paul. > > >> > > > > > > Thanks for the feedback. Can you provide an example of what you > > > would consider to be proper usage in the kernel? > > > > > > I think Paul is suggesting to use > > > > static int __init alt_fpga_bridge_init(void) > > { > > platform_driver_register(&alt_fpga_bridge_driver); > > } > > > > device_initcall(alt_fpga_bridge_init); > > > > or better: > > > > builtin_platform_driver(&alt_fpga_bridge_driver); > > > > Like for example in: drivers/cpuidle/cpuidle-mvebu-v7.c > > Yes, pretty much that -- if you have a bool Kconfig, you should be using > builtin registration functions, and have no need for module.h or > anything MODULE_<xyz> or any module_init/module_exit calls. > > An empty file containing nothing but #include <linux/module.h> will > cause cpp to emit about 750k of goop, so we really should only be using > it for drivers that are genuinely modular; i.e. tristate Kconfig. > > Thanks, > Paul. > -- > > > > > Cheers, > > > > Moritz > Thanks for the feedback and explanations! I've retested my stuff with it all built as modules (mgr, bridged, and fpga-region) and it all works that way as well as built in. So I'll fix up the Kconfig as tristates for everybody. Also I'll add some dependencies as FPGA_REGION should be dependent on FPGA_BRIDGE. Alan
Hi! Alan Tull writes: > Supports Altera SOCFPGA bridges: > * fpga2sdram > * fpga2hps > * hps2fpga > * lwhps2fpga > > Allows enabling/disabling the bridges through the FPGA > Bridge Framework API functions. > > The fpga2sdram driver only supports enabling and disabling > of the ports that been configured early on. This is due to > a hardware limitation where the read, write, and command > ports on the fpga2sdram bridge can only be reconfigured > while there are no transactions to the sdram, i.e. when > running out of OCRAM before the kernel boots. > > Device tree property 'init-val' configures the driver to > enable or disable the bridge during probe. If the property > does not exist, the driver will leave the bridge in its > current state. > > Signed-off-by: Alan Tull <atull@opensource.altera.com> > Signed-off-by: Matthew Gerlach <mgerlach@altera.com> > Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> (...) > +static inline int _alt_fpga2sdram_enable_set(struct alt_fpga2sdram_data *priv, > + bool enable) > +{ > + return regmap_update_bits(priv->sdrctl, ALT_SDR_CTL_FPGAPORTRST_OFST, > + priv->mask, enable ? priv->mask : 0); > +} (...) > + /* Get f2s bridge configuration saved in handoff register */ > + regmap_read(sysmgr, SYSMGR_ISWGRP_HANDOFF3, &priv->mask); > + Could you maybe add some documentation about this implicit information shared between a bootloader and this driver? I understand why you do this, but there must be a better way than depending on something some bootloader wrote in some undocumented register, no? The documentation just says: "These registers are used to store handoff infomation between the preloader and the OS. These 8 registers can be used to store any information. The contents of these registers have no impact on the state of the HPS hardware" If it is already agreed upon, that a bridge-enable property is okay, why not add a port-enable property, too? Regards, Steffen Trumtrar
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index ec81e21..b346166 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -39,6 +39,13 @@ config FPGA_BRIDGE Say Y here if you want to support bridges connected between host processors and FPGAs or between FPGAs. +config SOCFPGA_FPGA_BRIDGE + bool "Altera SoCFPGA FPGA Bridges" + depends on ARCH_SOCFPGA && FPGA_BRIDGE + help + Say Y to enable drivers for FPGA bridges for Altera SOCFPGA + devices. + endif # FPGA endmenu diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index 8d746c3..e658436 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o # FPGA Bridge Drivers obj-$(CONFIG_FPGA_BRIDGE) += fpga-bridge.o +obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE) += altera-hps2fpga.o altera-fpga2sdram.o # High Level Interfaces obj-$(CONFIG_FPGA_REGION) += fpga-region.o diff --git a/drivers/fpga/altera-fpga2sdram.c b/drivers/fpga/altera-fpga2sdram.c new file mode 100644 index 0000000..91f4a40 --- /dev/null +++ b/drivers/fpga/altera-fpga2sdram.c @@ -0,0 +1,174 @@ +/* + * FPGA to SDRAM Bridge Driver for Altera SoCFPGA Devices + * + * Copyright (C) 2013-2015 Altera Corporation, All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/* + * This driver manages a bridge between an FPGA and the SDRAM used by the ARM + * host processor system (HPS). + * + * The bridge contains 4 read ports, 4 write ports, and 6 command ports. + * Reconfiguring these ports requires that no SDRAM transactions occur during + * reconfiguration. The code reconfiguring the ports cannot run out of SDRAM + * nor can the FPGA access the SDRAM during reconfiguration. This driver does + * not support reconfiguring the ports. The ports are configured by code + * running out of on chip ram before Linux is started and the configuration + * is passed in a handoff register in the system manager. + * + * This driver supports enabling and disabling of the configured ports, which + * allows for safe reprogramming of the FPGA, assuming that the new FPGA image + * uses the same port configuration. Bridges must be disabled before + * reprogramming the FPGA and re-enabled after the FPGA has been programmed. + */ + +#include <linux/fpga/fpga-bridge.h> +#include <linux/kernel.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/of_platform.h> +#include <linux/regmap.h> + +#define ALT_SDR_CTL_FPGAPORTRST_OFST 0x80 +#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_MSK 0x00003fff +#define ALT_SDR_CTL_FPGAPORTRST_RD_SHIFT 0 +#define ALT_SDR_CTL_FPGAPORTRST_WR_SHIFT 4 +#define ALT_SDR_CTL_FPGAPORTRST_CTRL_SHIFT 8 + +#define SYSMGR_ISWGRP_HANDOFF3 (0x8C) +#define ISWGRP_HANDOFF_FPGA2SDR SYSMGR_ISWGRP_HANDOFF3 + +#define F2S_BRIDGE_NAME "fpga2sdram" + +struct alt_fpga2sdram_data { + struct device *dev; + struct regmap *sdrctl; + int mask; +}; + +static int alt_fpga2sdram_enable_show(struct fpga_bridge *bridge) +{ + struct alt_fpga2sdram_data *priv = bridge->priv; + int value; + + regmap_read(priv->sdrctl, ALT_SDR_CTL_FPGAPORTRST_OFST, &value); + + return (value & priv->mask) == priv->mask; +} + +static inline int _alt_fpga2sdram_enable_set(struct alt_fpga2sdram_data *priv, + bool enable) +{ + return regmap_update_bits(priv->sdrctl, ALT_SDR_CTL_FPGAPORTRST_OFST, + priv->mask, enable ? priv->mask : 0); +} + +static int alt_fpga2sdram_enable_set(struct fpga_bridge *bridge, bool enable) +{ + return _alt_fpga2sdram_enable_set(bridge->priv, enable); +} + +struct prop_map { + char *prop_name; + u32 *prop_value; + u32 prop_max; +}; + +static const struct fpga_bridge_ops altera_fpga2sdram_br_ops = { + .enable_set = alt_fpga2sdram_enable_set, + .enable_show = alt_fpga2sdram_enable_show, +}; + +static const struct of_device_id altera_fpga_of_match[] = { + { .compatible = "altr,socfpga-fpga2sdram-bridge" }, + {}, +}; + +static int alt_fpga_bridge_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct alt_fpga2sdram_data *priv; + u32 enable; + struct regmap *sysmgr; + int ret = 0; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = dev; + + priv->sdrctl = syscon_regmap_lookup_by_compatible("altr,sdr-ctl"); + if (IS_ERR(priv->sdrctl)) { + dev_err(dev, "regmap for altr,sdr-ctl lookup failed.\n"); + return PTR_ERR(priv->sdrctl); + } + + sysmgr = syscon_regmap_lookup_by_compatible("altr,sys-mgr"); + if (IS_ERR(priv->sdrctl)) { + dev_err(dev, "regmap for altr,sys-mgr lookup failed.\n"); + return PTR_ERR(sysmgr); + } + + /* Get f2s bridge configuration saved in handoff register */ + regmap_read(sysmgr, SYSMGR_ISWGRP_HANDOFF3, &priv->mask); + + ret = fpga_bridge_register(dev, F2S_BRIDGE_NAME, + &altera_fpga2sdram_br_ops, priv); + if (ret) + return ret; + + dev_info(dev, "driver initialized with handoff %08x\n", priv->mask); + + if (!of_property_read_u32(dev->of_node, "bridge-enable", &enable)) { + if (enable > 1) { + dev_warn(dev, "invalid bridge-enable %u > 1\n", enable); + } else { + dev_info(dev, "%s bridge\n", + (enable ? "enabling" : "disabling")); + ret = _alt_fpga2sdram_enable_set(priv, enable); + if (ret) { + fpga_bridge_unregister(&pdev->dev); + return ret; + } + } + } + + return ret; +} + +static int alt_fpga_bridge_remove(struct platform_device *pdev) +{ + fpga_bridge_unregister(&pdev->dev); + + return 0; +} + +MODULE_DEVICE_TABLE(of, altera_fpga_of_match); + +static struct platform_driver altera_fpga_driver = { + .probe = alt_fpga_bridge_probe, + .remove = alt_fpga_bridge_remove, + .driver = { + .name = "altera_fpga2sdram_bridge", + .of_match_table = of_match_ptr(altera_fpga_of_match), + }, +}; + +module_platform_driver(altera_fpga_driver); + +MODULE_DESCRIPTION("Altera SoCFPGA FPGA to SDRAM Bridge"); +MODULE_AUTHOR("Alan Tull <atull@opensource.altera.com>"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/fpga/altera-hps2fpga.c b/drivers/fpga/altera-hps2fpga.c new file mode 100644 index 0000000..4466022 --- /dev/null +++ b/drivers/fpga/altera-hps2fpga.c @@ -0,0 +1,213 @@ +/* + * FPGA to/from HPS Bridge Driver for Altera SoCFPGA Devices + * + * Copyright (C) 2013-2015 Altera Corporation, All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/* + * This driver manages bridges on a Altera SOCFPGA between the ARM host + * processor system (HPS) and the embedded FPGA. + * + * This driver supports enabling and disabling of the configured ports, which + * allows for safe reprogramming of the FPGA, assuming that the new FPGA image + * uses the same port configuration. Bridges must be disabled before + * reprogramming the FPGA and re-enabled after the FPGA has been programmed. + */ + +#include <linux/clk.h> +#include <linux/fpga/fpga-bridge.h> +#include <linux/kernel.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/of_platform.h> +#include <linux/regmap.h> +#include <linux/reset.h> + +#define ALT_L3_REMAP_OFST 0x0 +#define ALT_L3_REMAP_MPUZERO_MSK 0x00000001 +#define ALT_L3_REMAP_H2F_MSK 0x00000008 +#define ALT_L3_REMAP_LWH2F_MSK 0x00000010 + +#define HPS2FPGA_BRIDGE_NAME "hps2fpga" +#define LWHPS2FPGA_BRIDGE_NAME "lwhps2fpga" +#define FPGA2HPS_BRIDGE_NAME "fpga2hps" + +struct altera_hps2fpga_data { + const char *name; + struct reset_control *bridge_reset; + struct regmap *l3reg; + /* The L3 REMAP register is write only, so keep a cached value. */ + unsigned int l3_remap_value; + unsigned int remap_mask; + struct clk *clk; +}; + +static int alt_hps2fpga_enable_show(struct fpga_bridge *bridge) +{ + struct altera_hps2fpga_data *priv = bridge->priv; + + return reset_control_status(priv->bridge_reset); +} + +static int _alt_hps2fpga_enable_set(struct altera_hps2fpga_data *priv, + bool enable) +{ + int ret; + + /* bring bridge out of reset */ + if (enable) + ret = reset_control_deassert(priv->bridge_reset); + else + ret = reset_control_assert(priv->bridge_reset); + if (ret) + return ret; + + /* Allow bridge to be visible to L3 masters or not */ + if (priv->remap_mask) { + priv->l3_remap_value |= ALT_L3_REMAP_MPUZERO_MSK; + + if (enable) + priv->l3_remap_value |= priv->remap_mask; + else + priv->l3_remap_value &= ~priv->remap_mask; + + ret = regmap_write(priv->l3reg, ALT_L3_REMAP_OFST, + priv->l3_remap_value); + } + + return ret; +} + +static int alt_hps2fpga_enable_set(struct fpga_bridge *bridge, bool enable) +{ + return _alt_hps2fpga_enable_set(bridge->priv, enable); +} + +static const struct fpga_bridge_ops altera_hps2fpga_br_ops = { + .enable_set = alt_hps2fpga_enable_set, + .enable_show = alt_hps2fpga_enable_show, +}; + +static struct altera_hps2fpga_data hps2fpga_data = { + .name = HPS2FPGA_BRIDGE_NAME, + .remap_mask = ALT_L3_REMAP_H2F_MSK, +}; + +static struct altera_hps2fpga_data lwhps2fpga_data = { + .name = LWHPS2FPGA_BRIDGE_NAME, + .remap_mask = ALT_L3_REMAP_LWH2F_MSK, +}; + +static struct altera_hps2fpga_data fpga2hps_data = { + .name = FPGA2HPS_BRIDGE_NAME, +}; + +static const struct of_device_id altera_fpga_of_match[] = { + { .compatible = "altr,socfpga-hps2fpga-bridge", + .data = &hps2fpga_data }, + { .compatible = "altr,socfpga-lwhps2fpga-bridge", + .data = &lwhps2fpga_data }, + { .compatible = "altr,socfpga-fpga2hps-bridge", + .data = &fpga2hps_data }, + {}, +}; + +static int alt_fpga_bridge_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct altera_hps2fpga_data *priv; + const struct of_device_id *of_id; + u32 enable; + int ret; + + of_id = of_match_device(altera_fpga_of_match, dev); + priv = (struct altera_hps2fpga_data *)of_id->data; + + priv->bridge_reset = of_reset_control_get_by_index(dev->of_node, 0); + if (IS_ERR(priv->bridge_reset)) { + dev_err(dev, "Could not get %s reset control\n", priv->name); + return PTR_ERR(priv->bridge_reset); + } + + priv->l3reg = syscon_regmap_lookup_by_compatible("altr,l3regs"); + if (IS_ERR(priv->l3reg)) { + dev_err(dev, "regmap for altr,l3regs lookup failed\n"); + return PTR_ERR(priv->l3reg); + } + + priv->clk = of_clk_get(dev->of_node, 0); + if (IS_ERR(priv->clk)) { + dev_err(dev, "no clock specified\n"); + return PTR_ERR(priv->clk); + } + + ret = clk_prepare_enable(priv->clk); + if (ret) { + dev_err(dev, "could not enable clock\n"); + return -EBUSY; + } + + ret = fpga_bridge_register(dev, priv->name, &altera_hps2fpga_br_ops, + priv); + if (ret) + return ret; + + if (!of_property_read_u32(dev->of_node, "bridge-enable", &enable)) { + if (enable > 1) { + dev_warn(dev, "invalid bridge-enable %u > 1\n", enable); + } else { + dev_info(dev, "%s bridge\n", + (enable ? "enabling" : "disabling")); + + ret = _alt_hps2fpga_enable_set(priv, enable); + if (ret) { + fpga_bridge_unregister(&pdev->dev); + return ret; + } + } + } + + return ret; +} + +static int alt_fpga_bridge_remove(struct platform_device *pdev) +{ + struct fpga_bridge *bridge = platform_get_drvdata(pdev); + struct altera_hps2fpga_data *priv = bridge->priv; + + fpga_bridge_unregister(&pdev->dev); + + clk_disable_unprepare(priv->clk); + clk_put(priv->clk); + + return 0; +} + +MODULE_DEVICE_TABLE(of, altera_fpga_of_match); + +static struct platform_driver alt_fpga_bridge_driver = { + .probe = alt_fpga_bridge_probe, + .remove = alt_fpga_bridge_remove, + .driver = { + .name = "altera_hps2fpga_bridge", + .of_match_table = of_match_ptr(altera_fpga_of_match), + }, +}; + +module_platform_driver(alt_fpga_bridge_driver); + +MODULE_DESCRIPTION("Altera SoCFPGA HPS to FPGA Bridge"); +MODULE_AUTHOR("Alan Tull <atull@opensource.altera.com>"); +MODULE_LICENSE("GPL v2");