| Message ID | 1469757314-116169-2-git-send-email-apronin@chromium.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Thu, Jul 28, 2016 at 06:55:13PM -0700, Andrey Pronin wrote: > Add TPM2.0 PTP FIFO compatible SPI interface for chips with Cr50 > firmware. Since this is now a trivial device, does it still need a dedicated file? Jason ------------------------------------------------------------------------------
On Fri, Jul 29, 2016 at 11:27:52AM -0600, Jason Gunthorpe wrote: > On Thu, Jul 28, 2016 at 06:55:13PM -0700, Andrey Pronin wrote: > > Add TPM2.0 PTP FIFO compatible SPI interface for chips with Cr50 > > firmware. > > Since this is now a trivial device, does it still need a dedicated > file? There is no trivial devices file for SPI, only I2C. We could add one, but this is fine as is for me. Acked-by: Rob Herring <robh@kernel.org> ------------------------------------------------------------------------------
On Thu, Jul 28, 2016 at 06:55:13PM -0700, Andrey Pronin wrote: > Add TPM2.0 PTP FIFO compatible SPI interface for chips with Cr50 > firmware. > > Signed-off-by: Andrey Pronin <apronin@chromium.org> Acked-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com> /Jarkko > --- > .../devicetree/bindings/security/tpm/cr50_spi.txt | 21 +++++++++++++++++++++ > 1 file changed, 21 insertions(+) > create mode 100644 Documentation/devicetree/bindings/security/tpm/cr50_spi.txt > > diff --git a/Documentation/devicetree/bindings/security/tpm/cr50_spi.txt b/Documentation/devicetree/bindings/security/tpm/cr50_spi.txt > new file mode 100644 > index 0000000..2fbebd3 > --- /dev/null > +++ b/Documentation/devicetree/bindings/security/tpm/cr50_spi.txt > @@ -0,0 +1,21 @@ > +* H1 Secure Microcontroller with Cr50 Firmware on SPI Bus. > + > +H1 Secure Microcontroller running Cr50 firmware provides several > +functions, including TPM-like functionality. It communicates over > +SPI using the FIFO protocol described in the PTP Spec, section 6. > + > +Required properties: > +- compatible: Should be "google,cr50". > +- spi-max-frequency: Maximum SPI frequency. > + > +Example: > + > +&spi0 { > + status = "okay"; > + > + cr50@0 { > + compatible = "google,cr50"; > + reg = <0>; > + spi-max-frequency = <800000>; > + }; > +}; > -- > 2.6.6 > ------------------------------------------------------------------------------ What NetFlow Analyzer can do for you? Monitors network bandwidth and traffic patterns at an interface-level. Reveals which users, apps, and protocols are consuming the most bandwidth. Provides multi-vendor support for NetFlow, J-Flow, sFlow and other flows. Make informed decisions using capacity planning reports. http://sdm.link/zohodev2dev
diff --git a/Documentation/devicetree/bindings/security/tpm/cr50_spi.txt b/Documentation/devicetree/bindings/security/tpm/cr50_spi.txt new file mode 100644 index 0000000..2fbebd3 --- /dev/null +++ b/Documentation/devicetree/bindings/security/tpm/cr50_spi.txt @@ -0,0 +1,21 @@ +* H1 Secure Microcontroller with Cr50 Firmware on SPI Bus. + +H1 Secure Microcontroller running Cr50 firmware provides several +functions, including TPM-like functionality. It communicates over +SPI using the FIFO protocol described in the PTP Spec, section 6. + +Required properties: +- compatible: Should be "google,cr50". +- spi-max-frequency: Maximum SPI frequency. + +Example: + +&spi0 { + status = "okay"; + + cr50@0 { + compatible = "google,cr50"; + reg = <0>; + spi-max-frequency = <800000>; + }; +};
Add TPM2.0 PTP FIFO compatible SPI interface for chips with Cr50 firmware. Signed-off-by: Andrey Pronin <apronin@chromium.org> --- .../devicetree/bindings/security/tpm/cr50_spi.txt | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 Documentation/devicetree/bindings/security/tpm/cr50_spi.txt