diff mbox

[11/11] cpufreq: intel_pstate: Use CPPC to get max performance

Message ID 1471559812-19967-12-git-send-email-srinivas.pandruvada@linux.intel.com (mailing list archive)
State Changes Requested, archived
Headers show

Commit Message

srinivas pandruvada Aug. 18, 2016, 10:36 p.m. UTC 
This change uses acpi cppc_lib interface to get CPPC performance limits.
Once CPPC limits of all online cores are read, first check if there is
difference in max performance. If there is a difference, then the
scheduler interface is called to update per cpu priority. After updating
priority of all current cpus, the itmt feature is enabled.

Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
---
 drivers/cpufreq/Kconfig.x86    |  1 +
 drivers/cpufreq/intel_pstate.c | 75 ++++++++++++++++++++++++++++++++++++++++--
 2 files changed, 73 insertions(+), 3 deletions(-)

Comments

kernel test robot Aug. 22, 2016, 11:59 a.m. UTC | #1 
Hi Srinivas,

[auto build test ERROR on pm/linux-next]
[also build test ERROR on v4.8-rc3 next-20160822]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
[Suggest to use git(>=2.9.0) format-patch --base=<commit> (or --base=auto for convenience) to record what (public, well-known) commit your patch series was built on]
[Check https://git-scm.com/docs/git-format-patch for more information]

url:    https://github.com/0day-ci/linux/commits/Srinivas-Pandruvada/Support-Intel-Turbo-Boost-Max-Technology-3-0/20160819-101955
base:   https://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git linux-next
config: i386-randconfig-h0-08210914 (attached as .config)
compiler: gcc-6 (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
        # save the attached .config to linux build tree
        make ARCH=i386 

All errors (new ones prefixed by >>):

   drivers/acpi/cppc_acpi.c: In function 'cpc_read':
>> drivers/acpi/cppc_acpi.c:731:11: error: implicit declaration of function 'readq_relaxed' [-Werror=implicit-function-declaration]
       *val = readq_relaxed(vaddr);
              ^~~~~~~~~~~~~
   drivers/acpi/cppc_acpi.c: In function 'cpc_write':
>> drivers/acpi/cppc_acpi.c:764:4: error: implicit declaration of function 'writeq_relaxed' [-Werror=implicit-function-declaration]
       writeq_relaxed(val, vaddr);
       ^~~~~~~~~~~~~~
   cc1: some warnings being treated as errors

vim +/readq_relaxed +731 drivers/acpi/cppc_acpi.c

beee23ae Prakash, Prashanth  2016-02-17  725  			*val = readw_relaxed(vaddr);
77e3d86f Prakash, Prashanth  2016-02-17  726  			break;
77e3d86f Prakash, Prashanth  2016-02-17  727  		case 32:
beee23ae Prakash, Prashanth  2016-02-17  728  			*val = readl_relaxed(vaddr);
77e3d86f Prakash, Prashanth  2016-02-17  729  			break;
77e3d86f Prakash, Prashanth  2016-02-17  730  		case 64:
beee23ae Prakash, Prashanth  2016-02-17 @731  			*val = readq_relaxed(vaddr);
77e3d86f Prakash, Prashanth  2016-02-17  732  			break;
77e3d86f Prakash, Prashanth  2016-02-17  733  		default:
77e3d86f Prakash, Prashanth  2016-02-17  734  			pr_debug("Error: Cannot read %u bit width from PCC\n",
77e3d86f Prakash, Prashanth  2016-02-17  735  				reg->bit_width);
77e3d86f Prakash, Prashanth  2016-02-17  736  			ret_val = -EFAULT;
77e3d86f Prakash, Prashanth  2016-02-17  737  		}
c39ec8bd Srinivas Pandruvada 2016-08-18  738  	} else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) {
c39ec8bd Srinivas Pandruvada 2016-08-18  739  		ret_val = cpc_read_ffh(cpunum, reg, val);
77e3d86f Prakash, Prashanth  2016-02-17  740  	} else
77e3d86f Prakash, Prashanth  2016-02-17  741  		ret_val = acpi_os_read_memory((acpi_physical_address)reg->address,
337aadff Ashwin Chaugule     2015-10-02  742  					val, reg->bit_width);
77e3d86f Prakash, Prashanth  2016-02-17  743  	return ret_val;
337aadff Ashwin Chaugule     2015-10-02  744  }
337aadff Ashwin Chaugule     2015-10-02  745  
c39ec8bd Srinivas Pandruvada 2016-08-18  746  static int cpc_write(int cpunum, struct cpc_reg *reg, u64 val)
337aadff Ashwin Chaugule     2015-10-02  747  {
77e3d86f Prakash, Prashanth  2016-02-17  748  	int ret_val = 0;
77e3d86f Prakash, Prashanth  2016-02-17  749  
77e3d86f Prakash, Prashanth  2016-02-17  750  	if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
77e3d86f Prakash, Prashanth  2016-02-17  751  		void __iomem *vaddr = GET_PCC_VADDR(reg->address);
337aadff Ashwin Chaugule     2015-10-02  752  
77e3d86f Prakash, Prashanth  2016-02-17  753  		switch (reg->bit_width) {
77e3d86f Prakash, Prashanth  2016-02-17  754  		case 8:
beee23ae Prakash, Prashanth  2016-02-17  755  			writeb_relaxed(val, vaddr);
77e3d86f Prakash, Prashanth  2016-02-17  756  			break;
77e3d86f Prakash, Prashanth  2016-02-17  757  		case 16:
beee23ae Prakash, Prashanth  2016-02-17  758  			writew_relaxed(val, vaddr);
77e3d86f Prakash, Prashanth  2016-02-17  759  			break;
77e3d86f Prakash, Prashanth  2016-02-17  760  		case 32:
beee23ae Prakash, Prashanth  2016-02-17  761  			writel_relaxed(val, vaddr);
77e3d86f Prakash, Prashanth  2016-02-17  762  			break;
77e3d86f Prakash, Prashanth  2016-02-17  763  		case 64:
beee23ae Prakash, Prashanth  2016-02-17 @764  			writeq_relaxed(val, vaddr);
77e3d86f Prakash, Prashanth  2016-02-17  765  			break;
77e3d86f Prakash, Prashanth  2016-02-17  766  		default:
77e3d86f Prakash, Prashanth  2016-02-17  767  			pr_debug("Error: Cannot write %u bit width to PCC\n",

:::::: The code at line 731 was first introduced by commit
:::::: beee23aebc6650609ef1547f6d813fa5065f74aa ACPI / CPPC: replace writeX/readX to PCC with relaxed version

:::::: TO: Prakash, Prashanth <pprakash@codeaurora.org>
:::::: CC: Rafael J. Wysocki <rafael.j.wysocki@intel.com>

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation
diff mbox

Patch

diff --git a/drivers/cpufreq/Kconfig.x86 b/drivers/cpufreq/Kconfig.x86
index adbd1de..6c4f747 100644
--- a/drivers/cpufreq/Kconfig.x86
+++ b/drivers/cpufreq/Kconfig.x86
@@ -6,6 +6,7 @@  config X86_INTEL_PSTATE
        bool "Intel P state control"
        depends on X86
        select ACPI_PROCESSOR if ACPI
+       select ACPI_CPPC_LIB if ACPI
        help
           This driver provides a P state for Intel core processors.
 	  The driver implements an internal governor and will become
diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c
index be9eade..c51b9c7 100644
--- a/drivers/cpufreq/intel_pstate.c
+++ b/drivers/cpufreq/intel_pstate.c
@@ -44,6 +44,7 @@ 
 
 #ifdef CONFIG_ACPI
 #include <acpi/processor.h>
+#include <acpi/cppc_acpi.h>
 #endif
 
 #define FRAC_BITS 8
@@ -193,6 +194,8 @@  struct _pid {
  * @sample:		Storage for storing last Sample data
  * @acpi_perf_data:	Stores ACPI perf information read from _PSS
  * @valid_pss_table:	Set to true for valid ACPI _PSS entries found
+ * @cppc_data:		Stores CPPC information for HWP capable CPUs
+ * @valid_cppc_table:	Set to true for valid CPPC entries are found
  *
  * This structure stores per CPU instance data for all CPUs.
  */
@@ -215,6 +218,8 @@  struct cpudata {
 #ifdef CONFIG_ACPI
 	struct acpi_processor_performance acpi_perf_data;
 	bool valid_pss_table;
+	struct cppc_cpudata *cppc_data;
+	bool valid_cppc_table;
 #endif
 };
 
@@ -361,6 +366,15 @@  static struct perf_limits *limits = &powersave_limits;
 #endif
 
 #ifdef CONFIG_ACPI
+static cpumask_t cppc_rd_cpu_mask;
+
+/* Call set_sched_itmt from a work function to be able to use hotplug locks */
+static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
+{
+	set_sched_itmt(true);
+}
+
+static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
 
 static bool intel_pstate_get_ppc_enable_status(void)
 {
@@ -377,14 +391,63 @@  static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
 	int ret;
 	int i;
 
-	if (hwp_active)
+	cpu = all_cpu_data[policy->cpu];
+
+	if (hwp_active) {
+		struct cppc_perf_caps *perf_caps;
+
+		cpu->cppc_data = kzalloc(sizeof(struct cppc_cpudata),
+					 GFP_KERNEL);
+		if (!cpu->cppc_data)
+			return;
+
+		perf_caps = &cpu->cppc_data->perf_caps;
+		ret = cppc_get_perf_caps(policy->cpu, perf_caps);
+		if (ret) {
+			kfree(cpu->cppc_data);
+			return;
+		}
+
+		cpu->valid_cppc_table = true;
+		pr_debug("cpu:%d H:0x%x N:0x%x R:0x%x L:0x%x\n", policy->cpu,
+			 perf_caps->highest_perf, perf_caps->nominal_perf,
+			 perf_caps->reference_perf, perf_caps->lowest_perf);
+
+		cpumask_set_cpu(policy->cpu, &cppc_rd_cpu_mask);
+		if (cpumask_subset(topology_core_cpumask(policy->cpu),
+				   &cppc_rd_cpu_mask)) {
+			int cpu_index;
+			int max_prio;
+			bool itmt_support = false;
+
+			cpu = all_cpu_data[0];
+			max_prio = cpu->cppc_data->perf_caps.highest_perf;
+			for_each_cpu(cpu_index, &cppc_rd_cpu_mask) {
+				cpu = all_cpu_data[cpu_index];
+				perf_caps = &cpu->cppc_data->perf_caps;
+				if (max_prio != perf_caps->highest_perf) {
+					itmt_support = true;
+					break;
+				}
+			}
+
+			if (!itmt_support)
+				return;
+
+			for_each_cpu(cpu_index, &cppc_rd_cpu_mask) {
+				cpu = all_cpu_data[cpu_index];
+				perf_caps = &cpu->cppc_data->perf_caps;
+				sched_set_itmt_core_prio(
+					perf_caps->highest_perf, cpu_index);
+			}
+			schedule_work(&sched_itmt_work);
+		}
 		return;
+	}
 
 	if (!intel_pstate_get_ppc_enable_status())
 		return;
 
-	cpu = all_cpu_data[policy->cpu];
-
 	ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
 						  policy->cpu);
 	if (ret)
@@ -444,6 +507,12 @@  static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
 	struct cpudata *cpu;
 
 	cpu = all_cpu_data[policy->cpu];
+
+	if (cpu->valid_cppc_table) {
+		cpumask_clear_cpu(policy->cpu, &cppc_rd_cpu_mask);
+		kfree(cpu->cppc_data);
+	}
+
 	if (!cpu->valid_pss_table)
 		return;