| Message ID | 20160830031358.19468-1-chris.brandt@renesas.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
On Mon, Aug 29, 2016 at 11:13:58PM -0400, Chris Brandt wrote: > Check the MD_CLK pin to determine the current clock mode in order to set > the pll clock parent correctly. > > Signed-off-by: Chris Brandt <chris.brandt@renesas.com> > --- > v2: > * Switched to reading MD_CLK pin to determine mode Thanks, I have queued this up.
On Tue, Aug 30, 2016 at 09:04:44AM +0200, Simon Horman wrote: > On Mon, Aug 29, 2016 at 11:13:58PM -0400, Chris Brandt wrote: > > Check the MD_CLK pin to determine the current clock mode in order to set > > the pll clock parent correctly. > > > > Signed-off-by: Chris Brandt <chris.brandt@renesas.com> > > --- > > v2: > > * Switched to reading MD_CLK pin to determine mode > > Thanks, I have queued this up. Sorry, I hit reply to the wrong message This patch is for Geert not me.
Hi Chris, On Tue, Aug 30, 2016 at 5:13 AM, Chris Brandt <chris.brandt@renesas.com> wrote: > Check the MD_CLK pin to determine the current clock mode in order to set > the pll clock parent correctly. > > Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Thanks for your patch! > --- > v2: > * Switched to reading MD_CLK pin to determine mode > --- > drivers/clk/renesas/clk-rz.c | 21 +++++++++++++++++---- > 1 file changed, 17 insertions(+), 4 deletions(-) > > diff --git a/drivers/clk/renesas/clk-rz.c b/drivers/clk/renesas/clk-rz.c > index f6312c6..2fc8aae 100644 > --- a/drivers/clk/renesas/clk-rz.c > +++ b/drivers/clk/renesas/clk-rz.c > @@ -25,6 +25,9 @@ struct rz_cpg { > #define CPG_FRQCR 0x10 > #define CPG_FRQCR2 0x14 > > +#define PPR0 0xFCFE3200 > +#define PIBC0 0xFCFE7000 > + > /* ----------------------------------------------------------------------------- > * Initialization > */ > @@ -37,10 +40,20 @@ rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *na > static const unsigned frqcr_tab[4] = { 3, 2, 0, 1 }; > > if (strcmp(name, "pll") == 0) { > - /* FIXME: cpg_mode should be read from GPIO. But no GPIO support yet */ > - unsigned cpg_mode = 0; /* hardcoded to EXTAL for now */ > - const char *parent_name = of_clk_get_parent_name(np, cpg_mode); > - > + unsigned int cpg_mode; > + const char *parent_name; > + void __iomem *ppr0, *pibc0; > + > + /* MD_CLK is on P0_2 */ > + ppr0 = ioremap_nocache(PPR0, 2); > + pibc0 = ioremap_nocache(PIBC0, 2); > + BUG_ON(!ppr0 || !pibc0); > + iowrite16(4, pibc0); /* Enable input buffer */ > + cpg_mode = ioread16(ppr0) & 4; > + iounmap(ppr0); > + iounmap(pibc0); > + > + parent_name = cpg_mode ? "usb_x1" : "extal"; If you would use "cpg_mode = (ioread16(ppr0) >> 2) & 1;", the value of cpg_mode would be in sync with Table 6.2. Then you can avoid relying on actual clock names in DT, and keep parent_name = of_clk_get_parent_name(np, cpg_mode); The bindings already dictate the parent clocks must match clock modes in the datasheet, i.e. Table 6.2. For easier maintenance, I would factor out reading the mode pins in a separate function. When a proper GPIO driver is added, the function can be removed, and its callsite updated. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Geert, Thank you for the good review! On Aug 30, 2016, Geert Uytterhoeven wrote: > If you would use "cpg_mode = (ioread16(ppr0) >> 2) & 1;", the value of cpg_mode would > be in sync with Table 6.2. Then you can avoid relying on actual clock names in DT, and > keep > > parent_name = of_clk_get_parent_name(np, cpg_mode); > > The bindings already dictate the parent clocks must match clock modes in the datasheet, > i.e. Table 6.2. Cool trick. I guess I don't get understand all the "DT Magic" yet. I'll update the patch and resend. > For easier maintenance, I would factor out reading the mode pins in a separate function. > When a proper GPIO driver is added, the function can be removed, and its callsite updated. OK. I see setup-rcar-gen2.c had a separate rcar_gen2_read_mode_pins() function. Inside of clk-rz.c I'll make a rz_cpg_read_mode_pin() function. Chris
diff --git a/drivers/clk/renesas/clk-rz.c b/drivers/clk/renesas/clk-rz.c index f6312c6..2fc8aae 100644 --- a/drivers/clk/renesas/clk-rz.c +++ b/drivers/clk/renesas/clk-rz.c @@ -25,6 +25,9 @@ struct rz_cpg { #define CPG_FRQCR 0x10 #define CPG_FRQCR2 0x14 +#define PPR0 0xFCFE3200 +#define PIBC0 0xFCFE7000 + /* ----------------------------------------------------------------------------- * Initialization */ @@ -37,10 +40,20 @@ rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *na static const unsigned frqcr_tab[4] = { 3, 2, 0, 1 }; if (strcmp(name, "pll") == 0) { - /* FIXME: cpg_mode should be read from GPIO. But no GPIO support yet */ - unsigned cpg_mode = 0; /* hardcoded to EXTAL for now */ - const char *parent_name = of_clk_get_parent_name(np, cpg_mode); - + unsigned int cpg_mode; + const char *parent_name; + void __iomem *ppr0, *pibc0; + + /* MD_CLK is on P0_2 */ + ppr0 = ioremap_nocache(PPR0, 2); + pibc0 = ioremap_nocache(PIBC0, 2); + BUG_ON(!ppr0 || !pibc0); + iowrite16(4, pibc0); /* Enable input buffer */ + cpg_mode = ioread16(ppr0) & 4; + iounmap(ppr0); + iounmap(pibc0); + + parent_name = cpg_mode ? "usb_x1" : "extal"; mult = cpg_mode ? (32 / 4) : 30; return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, 1);
Check the MD_CLK pin to determine the current clock mode in order to set the pll clock parent correctly. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> --- v2: * Switched to reading MD_CLK pin to determine mode --- drivers/clk/renesas/clk-rz.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-)