| Message ID | 20160901114617.19416-1-thierry.reding@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 1 September 2016 at 13:46, Thierry Reding <thierry.reding@gmail.com> wrote: > From: Thierry Reding <treding@nvidia.com> > > According to the TRM, the SD/MMC controller on Tegra124 supports 34-bit > addressing, but testing shows that this doesn't work. On a device which > has more than 2 GiB of RAM and LPAE enabled, buffer allocations can use > addresses above the 32-bit boundary. > > One way to work around this would be to enable IOMMU physical to virtual > address translations for the SD/MMC controllers, but that's not easy to > implement without breaking existing use-cases. It's also not obvious why > 34-bit addressing doesn't work as advertised. In order to fix this for > existing users, add the SDHCI_QUIRK2_BROKEN_64_BIT_DMA quirk for now. > > Reported-by: Paul Kocialkowski <contact@paulk.fr> > Acked-by: Stephen Warren <swarren@nvidia.com> > Acked-by: Arnd Bergmann <arnd@arndb.de> > Acked-by: Adrian Hunter <adrian.hunter@intel.com> > Signed-off-by: Thierry Reding <treding@nvidia.com> Thanks, applied for next! Kind regards Uffe > --- > Changes in v2: > - add comment with rationale for the quirk > - add various Acked-bys > > drivers/mmc/host/sdhci-tegra.c | 27 ++++++++++++++++++++++++++- > 1 file changed, 26 insertions(+), 1 deletion(-) > > diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c > index 1e93dc4e303e..20b6ff5b4af1 100644 > --- a/drivers/mmc/host/sdhci-tegra.c > +++ b/drivers/mmc/host/sdhci-tegra.c > @@ -391,6 +391,31 @@ static const struct sdhci_tegra_soc_data soc_data_tegra114 = { > .pdata = &sdhci_tegra114_pdata, > }; > > +static const struct sdhci_pltfm_data sdhci_tegra124_pdata = { > + .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | > + SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | > + SDHCI_QUIRK_SINGLE_POWER_WRITE | > + SDHCI_QUIRK_NO_HISPD_BIT | > + SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | > + SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, > + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | > + /* > + * The TRM states that the SD/MMC controller found on > + * Tegra124 can address 34 bits (the maximum supported by > + * the Tegra memory controller), but tests show that DMA > + * to or from above 4 GiB doesn't work. This is possibly > + * caused by missing programming, though it's not obvious > + * what sequence is required. Mark 64-bit DMA broken for > + * now to fix this for existing users (e.g. Nyan boards). > + */ > + SDHCI_QUIRK2_BROKEN_64_BIT_DMA, > + .ops = &tegra114_sdhci_ops, > +}; > + > +static const struct sdhci_tegra_soc_data soc_data_tegra124 = { > + .pdata = &sdhci_tegra124_pdata, > +}; > + > static const struct sdhci_pltfm_data sdhci_tegra210_pdata = { > .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | > SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | > @@ -408,7 +433,7 @@ static const struct sdhci_tegra_soc_data soc_data_tegra210 = { > > static const struct of_device_id sdhci_tegra_dt_match[] = { > { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 }, > - { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra114 }, > + { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 }, > { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 }, > { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 }, > { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 }, > -- > 2.9.3 > -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Le jeudi 01 septembre 2016 à 13:46 +0200, Thierry Reding a écrit : > From: Thierry Reding <treding@nvidia.com> > > According to the TRM, the SD/MMC controller on Tegra124 supports 34-bit > addressing, but testing shows that this doesn't work. On a device which > has more than 2 GiB of RAM and LPAE enabled, buffer allocations can use > addresses above the 32-bit boundary. > > One way to work around this would be to enable IOMMU physical to virtual > address translations for the SD/MMC controllers, but that's not easy to > implement without breaking existing use-cases. It's also not obvious why > 34-bit addressing doesn't work as advertised. In order to fix this for > existing users, add the SDHCI_QUIRK2_BROKEN_64_BIT_DMA quirk for now. I finally took time to test this and it sadly doesn't fix the issue I have on tegra124 with 4 GiB RAM and LPAE. dmesg when the issue happens (with the patch applied and some debug added) follows: sdhci: Secure Digital Host Controller Interface driver sdhci: Copyright(c) Pierre Ossman sdhci-pltfm: SDHCI platform and OF driver helper sdhci-tegra 700b0000.sdhci: allocated mmc-pwrseq sdhci-tegra 700b0400.sdhci: Got CD GPIO sdhci-tegra 700b0400.sdhci: Got WP GPIO mmc0: Unknown controller version (3). You may experience problems. random: fast init done sdhci_set_dma_mask(): broken 64bit dma sdhci_set_dma_mask(): use 32bit dma mmc0: Invalid maximum block size, assuming 512 bytes input: Elan Touchpad as /devices/soc0/7000c400.i2c/i2c-1/1-0015/input/input1 using ADMA usbcore: registered new interface driver usbhid usbhid: USB HID core driver tegra-mc 70019000.memory-controller: hdar: read @0x000000007c058000: EMEM address decode error (EMEM decode error) tegra30-i2s 70301100.i2s: DMA channels sourced from device 70300000.ahub max98090 0-0010: MAX98090 REVID=0x43 max98090 0-0010: use default 2.8v micbias tegra-snd-max98090 sound: HiFi <-> 70301100.i2s mapping ok input: GoogleNyanBig Headphones as /devices/soc0/sound/sound/card1/input2 input: GoogleNyanBig Mic Jack as /devices/soc0/sound/sound/card1/input3 tegra-mc 70019000.memory-controller: sdmmcrab: read @0x000000007c050200: EMEM address decode error (EMEM decode error) mmc0: ADMA error A usual dmesg without LPAE enabled follows: [ 13.593724] mmc0: Unknown controller version (3). You may experience problems. [ 13.600934] sdhci_set_dma_mask(): broken 64bit dma [ 13.605716] sdhci_set_dma_mask(): use 32bit dma [ 13.610262] mmc0: Invalid maximum block size, assuming 512 bytes [ 13.622382] input: Elan Touchpad as /devices/soc0/7000c400.i2c/i2c-1/1-0015/input/input1 [ 13.675562] mmc0: SDHCI controller on 700b0600.sdhci [700b0600.sdhci] using ADMA which shows the same other two errors about controller version and block size. > Reported-by: Paul Kocialkowski <contact@paulk.fr> > Acked-by: Stephen Warren <swarren@nvidia.com> > Acked-by: Arnd Bergmann <arnd@arndb.de> > Acked-by: Adrian Hunter <adrian.hunter@intel.com> > Signed-off-by: Thierry Reding <treding@nvidia.com> > --- > Changes in v2: > - add comment with rationale for the quirk > - add various Acked-bys > > drivers/mmc/host/sdhci-tegra.c | 27 ++++++++++++++++++++++++++- > 1 file changed, 26 insertions(+), 1 deletion(-) > > diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c > index 1e93dc4e303e..20b6ff5b4af1 100644 > --- a/drivers/mmc/host/sdhci-tegra.c > +++ b/drivers/mmc/host/sdhci-tegra.c > @@ -391,6 +391,31 @@ static const struct sdhci_tegra_soc_data > soc_data_tegra114 = { > .pdata = &sdhci_tegra114_pdata, > }; > > +static const struct sdhci_pltfm_data sdhci_tegra124_pdata = { > + .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | > + SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | > + SDHCI_QUIRK_SINGLE_POWER_WRITE | > + SDHCI_QUIRK_NO_HISPD_BIT | > + SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | > + SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, > + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | > + /* > + * The TRM states that the SD/MMC controller found on > + * Tegra124 can address 34 bits (the maximum supported by > + * the Tegra memory controller), but tests show that DMA > + * to or from above 4 GiB doesn't work. This is possibly > + * caused by missing programming, though it's not obvious > + * what sequence is required. Mark 64-bit DMA broken for > + * now to fix this for existing users (e.g. Nyan boards). > + */ > + SDHCI_QUIRK2_BROKEN_64_BIT_DMA, > + .ops = &tegra114_sdhci_ops, > +}; > + > +static const struct sdhci_tegra_soc_data soc_data_tegra124 = { > + .pdata = &sdhci_tegra124_pdata, > +}; > + > static const struct sdhci_pltfm_data sdhci_tegra210_pdata = { > .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | > SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | > @@ -408,7 +433,7 @@ static const struct sdhci_tegra_soc_data soc_data_tegra210 > = { > > static const struct of_device_id sdhci_tegra_dt_match[] = { > { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 > }, > - { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra114 > }, > + { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 > }, > { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 > }, > { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 }, > { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 },
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 1e93dc4e303e..20b6ff5b4af1 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -391,6 +391,31 @@ static const struct sdhci_tegra_soc_data soc_data_tegra114 = { .pdata = &sdhci_tegra114_pdata, }; +static const struct sdhci_pltfm_data sdhci_tegra124_pdata = { + .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | + SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | + SDHCI_QUIRK_SINGLE_POWER_WRITE | + SDHCI_QUIRK_NO_HISPD_BIT | + SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | + SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | + /* + * The TRM states that the SD/MMC controller found on + * Tegra124 can address 34 bits (the maximum supported by + * the Tegra memory controller), but tests show that DMA + * to or from above 4 GiB doesn't work. This is possibly + * caused by missing programming, though it's not obvious + * what sequence is required. Mark 64-bit DMA broken for + * now to fix this for existing users (e.g. Nyan boards). + */ + SDHCI_QUIRK2_BROKEN_64_BIT_DMA, + .ops = &tegra114_sdhci_ops, +}; + +static const struct sdhci_tegra_soc_data soc_data_tegra124 = { + .pdata = &sdhci_tegra124_pdata, +}; + static const struct sdhci_pltfm_data sdhci_tegra210_pdata = { .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | @@ -408,7 +433,7 @@ static const struct sdhci_tegra_soc_data soc_data_tegra210 = { static const struct of_device_id sdhci_tegra_dt_match[] = { { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 }, - { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra114 }, + { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 }, { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 }, { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 }, { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 },