[v2,2/2] cpufreq: ti: Add cpufreq driver to determine available OPPs at runtime

Message ID	20160901025328.376-3-d-gerlach@ti.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org> From: Dave Gerlach <d-gerlach@ti.com> To: <linux-arm-kernel@lists.infradead.org>, <linux-omap@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-pm@vger.kernel.org> Subject: [PATCH v2 2/2] cpufreq: ti: Add cpufreq driver to determine available OPPs at runtime Date: Wed, 31 Aug 2016 21:53:28 -0500 Message-ID: <20160901025328.376-3-d-gerlach@ti.com> In-Reply-To: <20160901025328.376-1-d-gerlach@ti.com> References: <20160901025328.376-1-d-gerlach@ti.com> MIME-Version: 1.0 Precedence: list Cc: Mark Rutland <mark.rutland@arm.com>, Nishanth Menon <nm@ti.com>, Dave Gerlach <d-gerlach@ti.com>, Tony Lindgren <tony@atomide.com>, Viresh Kumar <viresh.kumar@linaro.org>, Rob Herring <robh+dt@kernel.org> Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" <linux-arm-kernel-bounces@lists.infradead.org> Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org

diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm index d89b8afe23b6..0dea6849ac3e 100644 --- a/drivers/cpufreq/Kconfig.arm +++ b/drivers/cpufreq/Kconfig.arm @@ -234,6 +234,17 @@ config ARM_TEGRA124_CPUFREQ help This adds the CPUFreq driver support for Tegra124 SOCs. +config ARM_TI_CPUFREQ + tristate "Texas Instruments CPUFreq support" + depends on ARCH_OMAP2PLUS + help + This driver enables valid OPPs on the running platform based on + values contained within the SoC in use. Enable this in order to + use the cpufreq-dt driver on all Texas Instruments platforms that + provide dt based operating-points-v2 tables with opp-supported-hw + data provided. Required for cpufreq support on AM335x, AM437x, + DRA7x, and AM57x platforms. + config ARM_PXA2xx_CPUFREQ tristate "Intel PXA2xx CPUfreq driver" depends on PXA27x || PXA25x diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile index 0a9b6a093646..5b1b6ec0a9f0 100644 --- a/drivers/cpufreq/Makefile +++ b/drivers/cpufreq/Makefile @@ -77,6 +77,7 @@ obj-$(CONFIG_ARM_SPEAR_CPUFREQ) += spear-cpufreq.o obj-$(CONFIG_ARM_STI_CPUFREQ) += sti-cpufreq.o obj-$(CONFIG_ARM_TEGRA20_CPUFREQ) += tegra20-cpufreq.o obj-$(CONFIG_ARM_TEGRA124_CPUFREQ) += tegra124-cpufreq.o +obj-$(CONFIG_ARM_TI_CPUFREQ) += ti-cpufreq.o obj-$(CONFIG_ARM_VEXPRESS_SPC_CPUFREQ) += vexpress-spc-cpufreq.o obj-$(CONFIG_ACPI_CPPC_CPUFREQ) += cppc_cpufreq.o obj-$(CONFIG_MACH_MVEBU_V7) += mvebu-cpufreq.o diff --git a/drivers/cpufreq/ti-cpufreq.c b/drivers/cpufreq/ti-cpufreq.c new file mode 100644 index 000000000000..819aff3ba449 --- /dev/null +++ b/drivers/cpufreq/ti-cpufreq.c @@ -0,0 +1,308 @@ +/* + * TI CPUFreq/OPP hw-supported driver + * + * Copyright (C) 2016 Texas Instruments, Inc. + * Dave Gerlach <d-gerlach@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/cpu.h> +#include <linux/io.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_platform.h> +#include <linux/pm_opp.h> +#include <linux/regmap.h> + +#define REVISION_MASK 0xF +#define REVISION_SHIFT 28 + +#define AM33XX_800M_ARM_MPU_MAX_FREQ 0x1E2F +#define AM43XX_600M_ARM_MPU_MAX_FREQ 0xFFA + +#define DRA7_EFUSE_HAS_OD_MPU_OPP 11 +#define DRA7_EFUSE_HAS_HIGH_MPU_OPP 15 +#define DRA7_EFUSE_HAS_ALL_MPU_OPP 23 + +#define DRA7_EFUSE_NOM_MPU_OPP BIT(0) +#define DRA7_EFUSE_OD_MPU_OPP BIT(1) +#define DRA7_EFUSE_HIGH_MPU_OPP BIT(2) + +#define VERSION_COUNT 2 + +struct ti_cpufreq_data; + +struct ti_cpufreq_soc_data { + unsigned long (*efuse_xlate)(struct ti_cpufreq_data *opp_data, + unsigned long efuse); + unsigned long efuse_fallback; +}; + +struct ti_cpufreq_data { + struct device *cpu_dev; + struct device *opp_dev; + struct regmap *opp_efuse; + struct regmap *revision; + const struct ti_cpufreq_soc_data *soc_data; +}; + +static unsigned long amx3_efuse_xlate(struct ti_cpufreq_data *opp_data, + unsigned long efuse) +{ + if (!efuse) + efuse = opp_data->soc_data->efuse_fallback; + /* AM335x and AM437x use "OPP disable" bits, so invert */ + return ~efuse; +} + +static unsigned long dra7_efuse_xlate(struct ti_cpufreq_data *opp_data, + unsigned long efuse) +{ + unsigned long calculated_efuse = DRA7_EFUSE_NOM_MPU_OPP; + + /* + * The efuse on dra7 and am57 parts contains a specific + * value indicating the highest available OPP. + */ + + switch (efuse) { + case DRA7_EFUSE_HAS_ALL_MPU_OPP: + case DRA7_EFUSE_HAS_HIGH_MPU_OPP: + calculated_efuse |= DRA7_EFUSE_HIGH_MPU_OPP; + case DRA7_EFUSE_HAS_OD_MPU_OPP: + calculated_efuse |= DRA7_EFUSE_OD_MPU_OPP; + } + + return calculated_efuse; +} + +static struct ti_cpufreq_soc_data am3x_soc_data = { + .efuse_xlate = amx3_efuse_xlate, + .efuse_fallback = AM33XX_800M_ARM_MPU_MAX_FREQ, +}; + +static struct ti_cpufreq_soc_data am4x_soc_data = { + .efuse_xlate = amx3_efuse_xlate, + .efuse_fallback = AM43XX_600M_ARM_MPU_MAX_FREQ, +}; + +static struct ti_cpufreq_soc_data dra7_soc_data = { + .efuse_xlate = dra7_efuse_xlate, +}; + +/** + * ti_cpufreq_get_efuse() - Parse and return efuse value present on SoC + * @opp_data: pointer to ti_cpufreq_data context + * @efuse_value: Set to the value parsed from efuse + * + * Returns error code if efuse not read properly. + */ +static int ti_cpufreq_get_efuse(struct ti_cpufreq_data *opp_data, + u32 *efuse_value) +{ + struct device *dev = opp_data->cpu_dev; + struct device_node *np = dev->of_node; + unsigned int efuse_offset; + u32 efuse, efuse_mask, efuse_shift, vals[4]; + int ret; + + ret = of_property_read_u32_array(np, "ti,syscon-efuse", vals, 4); + if (ret) { + dev_err(dev, "ti,syscon-efuse cannot be read %s: %d\n", + np->full_name, ret); + return ret; + } + + efuse_offset = vals[1]; + efuse_mask = vals[2]; + efuse_shift = vals[3]; + + ret = regmap_read(opp_data->opp_efuse, efuse_offset, &efuse); + if (ret) { + dev_err(dev, + "Failed to read the efuse value from syscon: %d\n", + ret); + return ret; + } + + efuse = (efuse & efuse_mask) >> efuse_shift; + + *efuse_value = opp_data->soc_data->efuse_xlate(opp_data, efuse); + + return 0; +} + +/** + * ti_cpufreq_get_rev() - Parse and return rev value present on SoC + * @opp_data: pointer to ti_cpufreq_data context + * @revision_value: Set to the value parsed from revision register + * + * Returns error code if revision not read properly. + */ +static int ti_cpufreq_get_rev(struct ti_cpufreq_data *opp_data, + u32 *revision_value) +{ + struct device *dev = opp_data->cpu_dev; + struct device_node *np = dev->of_node; + unsigned int revision_offset; + u32 revision; + int ret; + + ret = of_property_read_u32_index(np, "ti,syscon-rev", + 1, &revision_offset); + if (ret) { + dev_err(dev, + "No revision offset provided %s [%d]\n", + np->full_name, ret); + return ret; + } + + ret = regmap_read(opp_data->revision, revision_offset, &revision); + if (ret) { + dev_err(dev, + "Failed to read the revision number from syscon: %d\n", + ret); + return ret; + } + + *revision_value = BIT((revision >> REVISION_SHIFT) & REVISION_MASK); + + return 0; +} + +static int ti_cpufreq_setup_syscon_registers(struct ti_cpufreq_data *opp_data) +{ + struct device *dev = opp_data->cpu_dev; + struct device_node *np = dev->of_node; + + opp_data->opp_efuse = syscon_regmap_lookup_by_phandle(np, + "ti,syscon-efuse"); + if (IS_ERR(opp_data->opp_efuse)) { + dev_err(dev, + "\"ti,syscon-efuse\" is missing, cannot use OPPv2 table.\n"); + return PTR_ERR(opp_data->opp_efuse); + } + + opp_data->revision = syscon_regmap_lookup_by_phandle(np, + "ti,syscon-rev"); + if (IS_ERR(opp_data->revision)) { + dev_err(dev, + "\"ti,syscon-rev\" is missing, cannot use OPPv2 table.\n"); + return PTR_ERR(opp_data->revision); + } + + return 0; +} + +static const struct of_device_id ti_cpufreq_of_match[] = { + { .compatible = "operating-points-v2-ti-am3352-cpu", + .data = &am3x_soc_data, }, + { .compatible = "operating-points-v2-ti-am4372-cpu", + .data = &am4x_soc_data, }, + { .compatible = "operating-points-v2-ti-dra7-cpu", + .data = &dra7_soc_data }, + {}, +}; +MODULE_DEVICE_TABLE(of, ti_cpufreq_of_match); + +static int ti_cpufreq_probe(struct platform_device *pdev) +{ + int ret; + u32 version[VERSION_COUNT]; + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + const struct of_device_id *match; + struct ti_cpufreq_data *opp_data; + + if (!np) + return -ENODEV; + + match = of_match_node(ti_cpufreq_of_match, np); + if (!match) + return -ENODEV; + + opp_data = devm_kzalloc(dev, sizeof(*opp_data), GFP_KERNEL); + if (!opp_data) + return -ENOMEM; + + opp_data->soc_data = match->data; + opp_data->opp_dev = dev; + + opp_data->cpu_dev = get_cpu_device(0); + if (!opp_data->cpu_dev) { + pr_err("%s: Failed to get device for CPU0\n", __func__); + return -ENODEV; + } + + if (!of_get_property(opp_data->cpu_dev->of_node, "operating-points-v2", + NULL)) { + dev_info(opp_data->cpu_dev, + "OPP-v2 not supported, cpufreq-dt will attempt to use legacy tables.\n"); + goto register_cpufreq_dt; + } + + ret = ti_cpufreq_setup_syscon_registers(opp_data); + if (ret) + return ret; + + /* + * OPPs determine whether or not they are supported based on + * two metrics: + * 0 - SoC Revision + * 1 - eFuse value + */ + ret = ti_cpufreq_get_rev(opp_data, &version[0]); + if (ret) + return ret; + + ret = ti_cpufreq_get_efuse(opp_data, &version[1]); + if (ret) + return ret; + + ret = dev_pm_opp_set_supported_hw(opp_data->cpu_dev, version, + VERSION_COUNT); + if (ret) { + dev_err(opp_data->cpu_dev, + "Failed to set supported hardware\n"); + return ret; + } + +register_cpufreq_dt: + dev_set_drvdata(dev, opp_data); + platform_device_register_simple("cpufreq-dt", -1, NULL, 0); + + return 0; +} + +static int ti_cpufreq_remove(struct platform_device *pdev) +{ + struct ti_cpufreq_data *opp_data = platform_get_drvdata(pdev); + + dev_pm_opp_put_supported_hw(opp_data->cpu_dev); + + return 0; +} + +static struct platform_driver ti_cpufreq_driver = { + .probe = ti_cpufreq_probe, + .remove = ti_cpufreq_remove, + .driver = { + .name = "ti_cpufreq", + .of_match_table = ti_cpufreq_of_match, + }, +}; + +module_platform_driver(ti_cpufreq_driver); + +MODULE_DESCRIPTION("TI CPUFreq/OPP hw-supported driver"); +MODULE_AUTHOR("Dave Gerlach <d-gerlach@ti.com>"); +MODULE_LICENSE("GPL v2");

[v2,2/2] cpufreq: ti: Add cpufreq driver to determine available OPPs at runtime

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