| Message ID | 1471430989-28161-10-git-send-email-mika.kahola@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, Aug 17, 2016 at 01:49:45PM +0300, Mika Kahola wrote: > Filter out a mode that exceeds the max pixel rate setting > for DP to VGA dongle. This is defined in DPCD register 0x81 > if detailed cap info i.e. info field is 4 bytes long and > it is available for DP downstream port. > > The register defines the pixel rate divided by 8 in MP/s. > > v2: DPCD read outs and computation moved to drm (Ville, Daniel) > v3: Sink pixel rate computation moved to drm_dp_max_sink_dotclock() > function (Daniel) > v4: Use of drm_dp_helper.c routines to compute max pixel clock (Ville) > v5: Use of intel_dp->downstream_ports to read out port capabilities. > Code restructuring (Ville) > v6: Move DP branch device check to drm_dp_helper.c (Daniel) > v7: Cleanup as suggested by Ville > > Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Jim Bride <jim.bride@linux.intel.com> > --- > drivers/gpu/drm/i915/intel_dp.c | 27 ++++++++++++++++++++++++++- > 1 file changed, 26 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index 91ffb79..25f459e 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -190,6 +190,29 @@ intel_dp_max_data_rate(int max_link_clock, int max_lanes) > return (max_link_clock * max_lanes * 8) / 10; > } > > +static int > +intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp) > +{ > + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); > + struct intel_encoder *encoder = &intel_dig_port->base; > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > + int max_dotclk = dev_priv->max_dotclk_freq; > + int ds_max_dotclk; > + > + int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; > + > + if (type != DP_DS_PORT_TYPE_VGA) > + return max_dotclk; > + > + ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd, > + intel_dp->downstream_ports); > + > + if (ds_max_dotclk != 0) > + max_dotclk = min(max_dotclk, ds_max_dotclk);; > + > + return max_dotclk; > +} > + > static enum drm_mode_status > intel_dp_mode_valid(struct drm_connector *connector, > struct drm_display_mode *mode) > @@ -199,7 +222,9 @@ intel_dp_mode_valid(struct drm_connector *connector, > struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; > int target_clock = mode->clock; > int max_rate, mode_rate, max_lanes, max_link_clock; > - int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; > + int max_dotclk; > + > + max_dotclk = intel_dp_downstream_max_dotclock(intel_dp); > > if (is_edp(intel_dp) && fixed_mode) { > if (mode->hdisplay > fixed_mode->hdisplay) > -- > 1.9.1
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 91ffb79..25f459e 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -190,6 +190,29 @@ intel_dp_max_data_rate(int max_link_clock, int max_lanes) return (max_link_clock * max_lanes * 8) / 10; } +static int +intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp) +{ + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); + struct intel_encoder *encoder = &intel_dig_port->base; + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + int max_dotclk = dev_priv->max_dotclk_freq; + int ds_max_dotclk; + + int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; + + if (type != DP_DS_PORT_TYPE_VGA) + return max_dotclk; + + ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd, + intel_dp->downstream_ports); + + if (ds_max_dotclk != 0) + max_dotclk = min(max_dotclk, ds_max_dotclk);; + + return max_dotclk; +} + static enum drm_mode_status intel_dp_mode_valid(struct drm_connector *connector, struct drm_display_mode *mode) @@ -199,7 +222,9 @@ intel_dp_mode_valid(struct drm_connector *connector, struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; int target_clock = mode->clock; int max_rate, mode_rate, max_lanes, max_link_clock; - int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; + int max_dotclk; + + max_dotclk = intel_dp_downstream_max_dotclock(intel_dp); if (is_edp(intel_dp) && fixed_mode) { if (mode->hdisplay > fixed_mode->hdisplay)
Filter out a mode that exceeds the max pixel rate setting for DP to VGA dongle. This is defined in DPCD register 0x81 if detailed cap info i.e. info field is 4 bytes long and it is available for DP downstream port. The register defines the pixel rate divided by 8 in MP/s. v2: DPCD read outs and computation moved to drm (Ville, Daniel) v3: Sink pixel rate computation moved to drm_dp_max_sink_dotclock() function (Daniel) v4: Use of drm_dp_helper.c routines to compute max pixel clock (Ville) v5: Use of intel_dp->downstream_ports to read out port capabilities. Code restructuring (Ville) v6: Move DP branch device check to drm_dp_helper.c (Daniel) v7: Cleanup as suggested by Ville Signed-off-by: Mika Kahola <mika.kahola@intel.com> --- drivers/gpu/drm/i915/intel_dp.c | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-)