| Message ID | 20160831081817.5191-6-maxime.ripard@free-electrons.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, Aug 31, 2016 at 4:18 PM, Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > From: Mylène Josserand <mylene.josserand@free-electrons.com> > > The GR8 is an SoC made by Nextthing loosely based on the sun5i family. > > Since it's not clear yet what we can factor out and merge with the A10s and > A13 support, let's keep it out of the sun5i.dtsi include tree. We will > figure out what can be shared when things settle down. > > Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> > --- > arch/arm/boot/dts/gr8.dtsi | 1080 ++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 1080 insertions(+) > create mode 100644 arch/arm/boot/dts/gr8.dtsi > > diff --git a/arch/arm/boot/dts/gr8.dtsi b/arch/arm/boot/dts/gr8.dtsi > new file mode 100644 > index 000000000000..d21cfa3f3c14 > --- /dev/null > +++ b/arch/arm/boot/dts/gr8.dtsi > @@ -0,0 +1,1080 @@ > +/* > + * Copyright 2016 Mylène Josserand > + * > + * Mylène Josserand <mylene.josserand@free-electrons.com> > + * > + * This file is dual-licensed: you can use it either under the terms > + * of the GPL or the X11 license, at your option. Note that this dual > + * licensing only applies to this file, and not this project as a > + * whole. > + * > + * a) This library is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of the > + * License, or (at your option) any later version. > + * > + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * Or, alternatively, > + * > + * b) Permission is hereby granted, free of charge, to any person > + * obtaining a copy of this software and associated documentation > + * files (the "Software"), to deal in the Software without > + * restriction, including without limitation the rights to use, > + * copy, modify, merge, publish, distribute, sublicense, and/or > + * sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following > + * conditions: > + * > + * The above copyright notice and this permission notice shall be > + * included in all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES > + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND > + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT > + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, > + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > + * OTHER DEALINGS IN THE SOFTWARE. > + */ > + > +#include "skeleton.dtsi" > + > +#include <dt-bindings/clock/sun4i-a10-pll2.h> > +#include <dt-bindings/dma/sun4i-a10.h> > +#include <dt-bindings/pinctrl/sun4i-a10.h> > + > +/ { > + interrupt-parent = <&intc>; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a8"; > + reg = <0x0>; > + clocks = <&cpu>; > + }; > + }; > + > + clocks { > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + /* > + * This is a dummy clock, to be used as placeholder on > + * other mux clocks when a specific parent clock is not > + * yet implemented. It should be dropped when the driver > + * is complete. > + */ > + dummy: dummy { > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + clock-frequency = <0>; > + }; > + > + osc24M: clk@01c20050 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-osc-clk"; > + reg = <0x01c20050 0x4>; > + clock-frequency = <24000000>; > + clock-output-names = "osc24M"; > + }; > + > + osc3M: osc3M_clk { > + compatible = "fixed-factor-clock"; > + #clock-cells = <0>; > + clock-div = <8>; > + clock-mult = <1>; > + clocks = <&osc24M>; > + clock-output-names = "osc3M"; > + }; > + > + osc32k: clk@0 { > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + clock-frequency = <32768>; > + clock-output-names = "osc32k"; > + }; > + > + pll1: clk@01c20000 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-pll1-clk"; > + reg = <0x01c20000 0x4>; > + clocks = <&osc24M>; > + clock-output-names = "pll1"; > + }; > + > + pll2: clk@01c20008 { > + #clock-cells = <1>; > + compatible = "allwinner,sun5i-a13-pll2-clk"; > + reg = <0x01c20008 0x8>; > + clocks = <&osc24M>; > + clock-output-names = "pll2-1x", "pll2-2x", > + "pll2-4x", "pll2-8x"; > + }; > + > + pll3: clk@01c20010 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-pll3-clk"; > + reg = <0x01c20010 0x4>; > + clocks = <&osc3M>; > + clock-output-names = "pll3"; > + }; > + > + pll3x2: pll3x2_clk { > + compatible = "fixed-factor-clock"; > + #clock-cells = <0>; > + clock-div = <1>; > + clock-mult = <2>; > + clocks = <&pll3>; > + clock-output-names = "pll3-2x"; > + }; > + > + pll4: clk@01c20018 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-pll1-clk"; > + reg = <0x01c20018 0x4>; > + clocks = <&osc24M>; > + clock-output-names = "pll4"; > + }; > + > + pll5: clk@01c20020 { > + #clock-cells = <1>; > + compatible = "allwinner,sun4i-a10-pll5-clk"; > + reg = <0x01c20020 0x4>; > + clocks = <&osc24M>; > + clock-output-names = "pll5_ddr", "pll5_other"; > + }; > + > + pll6: clk@01c20028 { > + #clock-cells = <1>; > + compatible = "allwinner,sun4i-a10-pll6-clk"; > + reg = <0x01c20028 0x4>; > + clocks = <&osc24M>; > + clock-output-names = "pll6_sata", "pll6_other", "pll6"; > + }; > + > + pll7: clk@01c20030 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-pll3-clk"; > + reg = <0x01c20030 0x4>; > + clocks = <&osc3M>; > + clock-output-names = "pll7"; > + }; > + > + pll7x2: pll7x2_clk { > + compatible = "fixed-factor-clock"; > + #clock-cells = <0>; > + clock-div = <1>; > + clock-mult = <2>; > + clocks = <&pll7>; > + clock-output-names = "pll7-2x"; > + }; > + > + /* dummy is 200M */ > + cpu: cpu@01c20054 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-cpu-clk"; > + reg = <0x01c20054 0x4>; > + clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; > + clock-output-names = "cpu"; > + }; > + > + axi: axi@01c20054 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-axi-clk"; > + reg = <0x01c20054 0x4>; > + clocks = <&cpu>; > + clock-output-names = "axi"; > + }; > + > + ahb: ahb@01c20054 { > + #clock-cells = <0>; > + compatible = "allwinner,sun5i-a13-ahb-clk"; > + reg = <0x01c20054 0x4>; > + clocks = <&axi>, <&cpu>, <&pll6 1>; > + clock-output-names = "ahb"; > + /* > + * Use PLL6 as parent, instead of CPU/AXI > + * which has rate changes due to cpufreq > + */ > + assigned-clocks = <&ahb>; > + assigned-clock-parents = <&pll6 1>; > + }; > + > + apb0: apb0@01c20054 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-apb0-clk"; > + reg = <0x01c20054 0x4>; > + clocks = <&ahb>; > + clock-output-names = "apb0"; > + }; > + > + apb1: clk@01c20058 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-apb1-clk"; > + reg = <0x01c20058 0x4>; > + clocks = <&osc24M>, <&pll6 1>, <&osc32k>; > + clock-output-names = "apb1"; > + }; > + > + axi_gates: clk@01c2005c { > + #clock-cells = <1>; > + compatible = "allwinner,sun4i-a10-axi-gates-clk"; > + reg = <0x01c2005c 0x4>; > + clocks = <&axi>; > + clock-indices = <0>; > + clock-output-names = "axi_dram"; > + }; > + > + ahb_gates: clk@01c20060 { > + #clock-cells = <1>; > + compatible = "allwinner,sun5i-a13-ahb-gates-clk"; > + reg = <0x01c20060 0x8>; > + clocks = <&ahb>; > + clock-indices = <0>, <1>, > + <2>, <5>, <6>, > + <7>, <8>, <9>, > + <10>, <13>, > + <14>, <20>, > + <21>, <22>, > + <28>, <32>, <34>, > + <36>, <40>, <44>, > + <46>, <51>, > + <52>; > + clock-output-names = "ahb_usbotg", "ahb_ehci", > + "ahb_ohci", "ahb_ss", "ahb_dma", > + "ahb_bist", "ahb_mmc0", "ahb_mmc1", > + "ahb_mmc2", "ahb_nand", > + "ahb_sdram", "ahb_spi0", > + "ahb_spi1", "ahb_spi2", > + "ahb_stimer", "ahb_ve", "ahb_tve", > + "ahb_lcd", "ahb_csi", "ahb_de_be", > + "ahb_de_fe", "ahb_iep", > + "ahb_mali400"; > + }; > + > + apb0_gates: clk@01c20068 { > + #clock-cells = <1>; > + compatible = "allwinner,sun5i-a13-apb0-gates-clk"; > + reg = <0x01c20068 0x4>; > + clocks = <&apb0>; > + clock-indices = <0>, <3>, > + <5>, <6>; > + clock-output-names = "apb0_codec", "apb0_i2s0", > + "apb0_pio", "apb0_ir"; > + }; I assume the ahb and apb0 gates would be different? In the cover letter you mentioned that ethernet is gone, but i2s was added? Otherwise, Acked-by: Chen-Yu Tsai <wens@csie.org> > + > + apb1_gates: clk@01c2006c { > + #clock-cells = <1>; > + compatible = "allwinner,sun5i-a13-apb1-gates-clk"; > + reg = <0x01c2006c 0x4>; > + clocks = <&apb1>; > + clock-indices = <0>, <1>, > + <2>, <17>, > + <18>; > + clock-output-names = "apb1_i2c0", "apb1_i2c1", > + "apb1_i2c2", "apb1_uart1", > + "apb1_uart2"; > + }; > + > + nand_clk: clk@01c20080 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-mod0-clk"; > + reg = <0x01c20080 0x4>; > + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; > + clock-output-names = "nand"; > + }; > + > + ms_clk: clk@01c20084 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-mod0-clk"; > + reg = <0x01c20084 0x4>; > + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; > + clock-output-names = "ms"; > + }; > + > + mmc0_clk: clk@01c20088 { > + #clock-cells = <1>; > + compatible = "allwinner,sun4i-a10-mmc-clk"; > + reg = <0x01c20088 0x4>; > + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; > + clock-output-names = "mmc0", > + "mmc0_output", > + "mmc0_sample"; > + }; > + > + mmc1_clk: clk@01c2008c { > + #clock-cells = <1>; > + compatible = "allwinner,sun4i-a10-mmc-clk"; > + reg = <0x01c2008c 0x4>; > + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; > + clock-output-names = "mmc1", > + "mmc1_output", > + "mmc1_sample"; > + }; > + > + mmc2_clk: clk@01c20090 { > + #clock-cells = <1>; > + compatible = "allwinner,sun4i-a10-mmc-clk"; > + reg = <0x01c20090 0x4>; > + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; > + clock-output-names = "mmc2", > + "mmc2_output", > + "mmc2_sample"; > + }; > + > + ts_clk: clk@01c20098 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-mod0-clk"; > + reg = <0x01c20098 0x4>; > + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; > + clock-output-names = "ts"; > + }; > + > + ss_clk: clk@01c2009c { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-mod0-clk"; > + reg = <0x01c2009c 0x4>; > + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; > + clock-output-names = "ss"; > + }; > + > + spi0_clk: clk@01c200a0 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-mod0-clk"; > + reg = <0x01c200a0 0x4>; > + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; > + clock-output-names = "spi0"; > + }; > + > + spi1_clk: clk@01c200a4 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-mod0-clk"; > + reg = <0x01c200a4 0x4>; > + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; > + clock-output-names = "spi1"; > + }; > + > + spi2_clk: clk@01c200a8 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-mod0-clk"; > + reg = <0x01c200a8 0x4>; > + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; > + clock-output-names = "spi2"; > + }; > + > + ir0_clk: clk@01c200b0 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-mod0-clk"; > + reg = <0x01c200b0 0x4>; > + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; > + clock-output-names = "ir0"; > + }; > + > + i2s0_clk: clk@01c200b8 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-mod1-clk"; > + reg = <0x01c200b8 0x4>; > + clocks = <&pll2 SUN4I_A10_PLL2_8X>, > + <&pll2 SUN4I_A10_PLL2_4X>, > + <&pll2 SUN4I_A10_PLL2_2X>, > + <&pll2 SUN4I_A10_PLL2_1X>; > + clock-output-names = "i2s0"; > + }; > + > + spdif_clk: clk@01c200c0 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-mod1-clk"; > + reg = <0x01c200c0 0x4>; > + clocks = <&pll2 SUN4I_A10_PLL2_8X>, > + <&pll2 SUN4I_A10_PLL2_4X>, > + <&pll2 SUN4I_A10_PLL2_2X>, > + <&pll2 SUN4I_A10_PLL2_1X>; > + clock-output-names = "spdif"; > + }; > + > + usb_clk: clk@01c200cc { > + #clock-cells = <1>; > + #reset-cells = <1>; > + compatible = "allwinner,sun5i-a13-usb-clk"; > + reg = <0x01c200cc 0x4>; > + clocks = <&pll6 1>; > + clock-output-names = "usb_ohci0", "usb_phy"; > + }; > + > + dram_gates: clk@01c20100 { > + #clock-cells = <1>; > + compatible = "nextthing,gr8-dram-gates-clk", > + "allwinner,sun4i-a10-gates-clk"; > + reg = <0x01c20100 0x4>; > + clocks = <&pll5 0>; > + clock-indices = <0>, > + <1>, > + <25>, > + <26>, > + <29>, > + <31>; > + clock-output-names = "dram_ve", > + "dram_csi", > + "dram_de_fe", > + "dram_de_be", > + "dram_ace", > + "dram_iep"; > + }; > + > + de_be_clk: clk@01c20104 { > + #clock-cells = <0>; > + #reset-cells = <0>; > + compatible = "allwinner,sun4i-a10-display-clk"; > + reg = <0x01c20104 0x4>; > + clocks = <&pll3>, <&pll7>, <&pll5 1>; > + clock-output-names = "de-be"; > + }; > + > + de_fe_clk: clk@01c2010c { > + #clock-cells = <0>; > + #reset-cells = <0>; > + compatible = "allwinner,sun4i-a10-display-clk"; > + reg = <0x01c2010c 0x4>; > + clocks = <&pll3>, <&pll7>, <&pll5 1>; > + clock-output-names = "de-fe"; > + }; > + > + tcon_ch0_clk: clk@01c20118 { > + #clock-cells = <0>; > + #reset-cells = <1>; > + compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; > + reg = <0x01c20118 0x4>; > + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; > + clock-output-names = "tcon-ch0-sclk"; > + }; > + > + tcon_ch1_clk: clk@01c2012c { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; > + reg = <0x01c2012c 0x4>; > + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; > + clock-output-names = "tcon-ch1-sclk"; > + }; > + > + codec_clk: clk@01c20140 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-codec-clk"; > + reg = <0x01c20140 0x4>; > + clocks = <&pll2 SUN4I_A10_PLL2_1X>; > + clock-output-names = "codec"; > + }; > + > + mbus_clk: clk@01c2015c { > + #clock-cells = <0>; > + compatible = "allwinner,sun5i-a13-mbus-clk"; > + reg = <0x01c2015c 0x4>; > + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; > + clock-output-names = "mbus"; > + }; > + }; > + > + display-engine { > + compatible = "allwinner,sun5i-a13-display-engine"; > + allwinner,pipelines = <&fe0>; > + }; > + > + soc@01c00000 { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + sram-controller@01c00000 { > + compatible = "allwinner,sun4i-a10-sram-controller"; > + reg = <0x01c00000 0x30>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + sram_a: sram@00000000 { > + compatible = "mmio-sram"; > + reg = <0x00000000 0xc000>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0x00000000 0xc000>; > + }; > + > + sram_d: sram@00010000 { > + compatible = "mmio-sram"; > + reg = <0x00010000 0x1000>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0x00010000 0x1000>; > + > + otg_sram: sram-section@0000 { > + compatible = "allwinner,sun4i-a10-sram-d"; > + reg = <0x0000 0x1000>; > + status = "disabled"; > + }; > + }; > + }; > + > + dma: dma-controller@01c02000 { > + compatible = "allwinner,sun4i-a10-dma"; > + reg = <0x01c02000 0x1000>; > + interrupts = <27>; > + clocks = <&ahb_gates 6>; > + #dma-cells = <2>; > + }; > + > + nfc: nand@01c03000 { > + compatible = "allwinner,sun4i-a10-nand"; > + reg = <0x01c03000 0x1000>; > + interrupts = <37>; > + clocks = <&ahb_gates 13>, <&nand_clk>; > + clock-names = "ahb", "mod"; > + dmas = <&dma SUN4I_DMA_DEDICATED 3>; > + dma-names = "rxtx"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + spi0: spi@01c05000 { > + compatible = "allwinner,sun4i-a10-spi"; > + reg = <0x01c05000 0x1000>; > + interrupts = <10>; > + clocks = <&ahb_gates 20>, <&spi0_clk>; > + clock-names = "ahb", "mod"; > + dmas = <&dma SUN4I_DMA_DEDICATED 27>, > + <&dma SUN4I_DMA_DEDICATED 26>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + spi1: spi@01c06000 { > + compatible = "allwinner,sun4i-a10-spi"; > + reg = <0x01c06000 0x1000>; > + interrupts = <11>; > + clocks = <&ahb_gates 21>, <&spi1_clk>; > + clock-names = "ahb", "mod"; > + dmas = <&dma SUN4I_DMA_DEDICATED 9>, > + <&dma SUN4I_DMA_DEDICATED 8>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + tve0: tv-encoder@01c0a000 { > + compatible = "allwinner,sun4i-a10-tv-encoder"; > + reg = <0x01c0a000 0x1000>; > + clocks = <&ahb_gates 34>; > + resets = <&tcon_ch0_clk 0>; > + status = "disabled"; > + > + port { > + #address-cells = <1>; > + #size-cells = <0>; > + > + tve0_in_tcon0: endpoint@0 { > + reg = <0>; > + remote-endpoint = <&tcon0_out_tve0>; > + }; > + }; > + }; > + > + tcon0: lcd-controller@01c0c000 { > + compatible = "allwinner,sun5i-a13-tcon"; > + reg = <0x01c0c000 0x1000>; > + interrupts = <44>; > + resets = <&tcon_ch0_clk 1>; > + reset-names = "lcd"; > + clocks = <&ahb_gates 36>, > + <&tcon_ch0_clk>, > + <&tcon_ch1_clk>; > + clock-names = "ahb", > + "tcon-ch0", > + "tcon-ch1"; > + clock-output-names = "tcon-pixel-clock"; > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + tcon0_in: port@0 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0>; > + > + tcon0_in_be0: endpoint@0 { > + reg = <0>; > + remote-endpoint = <&be0_out_tcon0>; > + }; > + }; > + > + tcon0_out: port@1 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <1>; > + > + tcon0_out_tve0: endpoint@1 { > + reg = <1>; > + remote-endpoint = <&tve0_in_tcon0>; > + }; > + }; > + }; > + }; > + > + mmc0: mmc@01c0f000 { > + compatible = "allwinner,sun5i-a13-mmc"; > + reg = <0x01c0f000 0x1000>; > + clocks = <&ahb_gates 8>, > + <&mmc0_clk 0>, > + <&mmc0_clk 1>, > + <&mmc0_clk 2>; > + clock-names = "ahb", > + "mmc", > + "output", > + "sample"; > + interrupts = <32>; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + mmc1: mmc@01c10000 { > + compatible = "allwinner,sun5i-a13-mmc"; > + reg = <0x01c10000 0x1000>; > + clocks = <&ahb_gates 9>, > + <&mmc1_clk 0>, > + <&mmc1_clk 1>, > + <&mmc1_clk 2>; > + clock-names = "ahb", > + "mmc", > + "output", > + "sample"; > + interrupts = <33>; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + mmc2: mmc@01c11000 { > + compatible = "allwinner,sun5i-a13-mmc"; > + reg = <0x01c11000 0x1000>; > + clocks = <&ahb_gates 10>, > + <&mmc2_clk 0>, > + <&mmc2_clk 1>, > + <&mmc2_clk 2>; > + clock-names = "ahb", > + "mmc", > + "output", > + "sample"; > + interrupts = <34>; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + usb_otg: usb@01c13000 { > + compatible = "allwinner,sun4i-a10-musb"; > + reg = <0x01c13000 0x0400>; > + clocks = <&ahb_gates 0>; > + interrupts = <38>; > + interrupt-names = "mc"; > + phys = <&usbphy 0>; > + phy-names = "usb"; > + extcon = <&usbphy 0>; > + allwinner,sram = <&otg_sram 1>; > + status = "disabled"; > + > + dr_mode = "otg"; > + }; > + > + usbphy: phy@01c13400 { > + #phy-cells = <1>; > + compatible = "allwinner,sun5i-a13-usb-phy"; > + reg = <0x01c13400 0x10 0x01c14800 0x4>; > + reg-names = "phy_ctrl", "pmu1"; > + clocks = <&usb_clk 8>; > + clock-names = "usb_phy"; > + resets = <&usb_clk 0>, <&usb_clk 1>; > + reset-names = "usb0_reset", "usb1_reset"; > + status = "disabled"; > + }; > + > + ehci0: usb@01c14000 { > + compatible = "allwinner,sun5i-a13-ehci", "generic-ehci"; > + reg = <0x01c14000 0x100>; > + interrupts = <39>; > + clocks = <&ahb_gates 1>; > + phys = <&usbphy 1>; > + phy-names = "usb"; > + status = "disabled"; > + }; > + > + ohci0: usb@01c14400 { > + compatible = "allwinner,sun5i-a13-ohci", "generic-ohci"; > + reg = <0x01c14400 0x100>; > + interrupts = <40>; > + clocks = <&usb_clk 6>, <&ahb_gates 2>; > + phys = <&usbphy 1>; > + phy-names = "usb"; > + status = "disabled"; > + }; > + > + spi2: spi@01c17000 { > + compatible = "allwinner,sun4i-a10-spi"; > + reg = <0x01c17000 0x1000>; > + interrupts = <12>; > + clocks = <&ahb_gates 22>, <&spi2_clk>; > + clock-names = "ahb", "mod"; > + dmas = <&dma SUN4I_DMA_DEDICATED 29>, > + <&dma SUN4I_DMA_DEDICATED 28>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + intc: interrupt-controller@01c20400 { > + compatible = "allwinner,sun4i-a10-ic"; > + reg = <0x01c20400 0x400>; > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > + > + pio: pinctrl@01c20800 { > + compatible = "nextthing,gr8-pinctrl"; > + reg = <0x01c20800 0x400>; > + interrupts = <28>; > + clocks = <&apb0_gates 5>; > + gpio-controller; > + interrupt-controller; > + #interrupt-cells = <3>; > + #gpio-cells = <3>; > + > + i2c0_pins_a: i2c0@0 { > + allwinner,pins = "PB0", "PB1"; > + allwinner,function = "i2c0"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + > + i2c1_pins_a: i2c1@0 { > + allwinner,pins = "PB15", "PB16"; > + allwinner,function = "i2c1"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + > + i2c2_pins_a: i2c2@0 { > + allwinner,pins = "PB17", "PB18"; > + allwinner,function = "i2c2"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + > + i2s0_pins_a: i2s0@0 { > + allwinner,pins = "PB5", "PB6", "PB7", "PB8", "PB9"; > + allwinner,function = "i2s0"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + > + ir0_rx_pins_a: ir0@0 { > + allwinner,pins = "PB4"; > + allwinner,function = "ir0"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + > + lcd_rgb666_pins: lcd_rgb666@0 { > + allwinner,pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", > + "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", > + "PD18", "PD19", "PD20", "PD21", "PD22", "PD23", > + "PD24", "PD25", "PD26", "PD27"; > + allwinner,function = "lcd0"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + > + mmc0_pins_a: mmc0@0 { > + allwinner,pins = "PF0", "PF1", "PF2", "PF3", > + "PF4", "PF5"; > + allwinner,function = "mmc0"; > + allwinner,drive = <SUN4I_PINCTRL_30_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + > + nand_pins_a: nand_base0@0 { > + allwinner,pins = "PC0", "PC1", "PC2", > + "PC5", "PC8", "PC9", "PC10", > + "PC11", "PC12", "PC13", "PC14", > + "PC15"; > + allwinner,function = "nand0"; > + allwinner,drive = <0>; > + allwinner,pull = <0>; > + }; > + > + nand_cs0_pins_a: nand_cs@0 { > + allwinner,pins = "PC4"; > + allwinner,function = "nand0"; > + allwinner,drive = <0>; > + allwinner,pull = <0>; > + }; > + > + nand_rb0_pins_a: nand_rb@0 { > + allwinner,pins = "PC6"; > + allwinner,function = "nand0"; > + allwinner,drive = <0>; > + allwinner,pull = <0>; > + }; > + > + uart1_pins_a: uart1@1 { > + allwinner,pins = "PG3", "PG4"; > + allwinner,function = "uart1"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + > + uart1_cts_rts_pins_a: uart1-cts-rts@0 { > + allwinner,pins = "PG5", "PG6"; > + allwinner,function = "uart1"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + > + pwm0_pins_a: pwm0@0 { > + allwinner,pins = "PB2"; > + allwinner,function = "pwm0"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + > + spdif_tx_pins_a: spdif@0 { > + allwinner,pins = "PB10"; > + allwinner,function = "spdif"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; > + }; > + }; > + > + pwm: pwm@01c20e00 { > + compatible = "allwinner,sun5i-a10s-pwm"; > + reg = <0x01c20e00 0xc>; > + clocks = <&osc24M>; > + #pwm-cells = <3>; > + status = "disabled"; > + }; > + > + timer@01c20c00 { > + compatible = "allwinner,sun4i-a10-timer"; > + reg = <0x01c20c00 0x90>; > + interrupts = <22>; > + clocks = <&osc24M>; > + }; > + > + wdt: watchdog@01c20c90 { > + compatible = "allwinner,sun4i-a10-wdt"; > + reg = <0x01c20c90 0x10>; > + }; > + > + spdif: spdif@01c21000 { > + #sound-dai-cells = <0>; > + compatible = "allwinner,sun4i-a10-spdif"; > + reg = <0x01c21000 0x400>; > + interrupts = <13>; > + clocks = <&apb0_gates 1>, <&spdif_clk>; > + clock-names = "apb", "spdif"; > + dmas = <&dma SUN4I_DMA_NORMAL 2>, > + <&dma SUN4I_DMA_NORMAL 2>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + }; > + > + ir0: ir@01c21800 { > + compatible = "allwinner,sun4i-a10-ir"; > + clocks = <&apb0_gates 6>, <&ir0_clk>; > + clock-names = "apb", "ir"; > + interrupts = <5>; > + reg = <0x01c21800 0x40>; > + status = "disabled"; > + }; > + > + i2s0: i2s@01c22400 { > + #sound-dai-cells = <0>; > + compatible = "allwinner,sun4i-a10-i2s"; > + reg = <0x01c22400 0x400>; > + interrupts = <16>; > + clocks = <&apb0_gates 3>, <&i2s0_clk>; > + clock-names = "apb", "mod"; > + dmas = <&dma SUN4I_DMA_NORMAL 3>, > + <&dma SUN4I_DMA_NORMAL 3>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + }; > + > + lradc: lradc@01c22800 { > + compatible = "allwinner,sun4i-a10-lradc-keys"; > + reg = <0x01c22800 0x100>; > + interrupts = <31>; > + status = "disabled"; > + }; > + > + codec: codec@01c22c00 { > + #sound-dai-cells = <0>; > + compatible = "allwinner,sun4i-a10-codec"; > + reg = <0x01c22c00 0x40>; > + interrupts = <30>; > + clocks = <&apb0_gates 0>, <&codec_clk>; > + clock-names = "apb", "codec"; > + dmas = <&dma SUN4I_DMA_NORMAL 19>, > + <&dma SUN4I_DMA_NORMAL 19>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + }; > + > + rtp: rtp@01c25000 { > + compatible = "allwinner,sun5i-a13-ts"; > + reg = <0x01c25000 0x100>; > + interrupts = <29>; > + #thermal-sensor-cells = <0>; > + }; > + > + uart1: serial@01c28400 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28400 0x400>; > + interrupts = <2>; > + reg-shift = <2>; > + reg-io-width = <4>; > + clocks = <&apb1_gates 17>; > + status = "disabled"; > + }; > + > + uart2: serial@01c28800 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28800 0x400>; > + interrupts = <3>; > + reg-shift = <2>; > + reg-io-width = <4>; > + clocks = <&apb1_gates 18>; > + status = "disabled"; > + }; > + > + i2c0: i2c@01c2ac00 { > + compatible = "allwinner,sun4i-a10-i2c"; > + reg = <0x01c2ac00 0x400>; > + interrupts = <7>; > + clocks = <&apb1_gates 0>; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + i2c1: i2c@01c2b000 { > + compatible = "allwinner,sun4i-a10-i2c"; > + reg = <0x01c2b000 0x400>; > + interrupts = <8>; > + clocks = <&apb1_gates 1>; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + i2c2: i2c@01c2b400 { > + compatible = "allwinner,sun4i-a10-i2c"; > + reg = <0x01c2b400 0x400>; > + interrupts = <9>; > + clocks = <&apb1_gates 2>; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + timer@01c60000 { > + compatible = "allwinner,sun5i-a13-hstimer"; > + reg = <0x01c60000 0x1000>; > + interrupts = <82>, <83>; > + clocks = <&ahb_gates 28>; > + }; > + > + fe0: display-frontend@01e00000 { > + compatible = "allwinner,sun5i-a13-display-frontend"; > + reg = <0x01e00000 0x20000>; > + interrupts = <47>; > + clocks = <&ahb_gates 46>, <&de_fe_clk>, > + <&dram_gates 25>; > + clock-names = "ahb", "mod", > + "ram"; > + resets = <&de_fe_clk>; > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + fe0_out: port@1 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <1>; > + > + fe0_out_be0: endpoint@0 { > + reg = <0>; > + remote-endpoint = <&be0_in_fe0>; > + }; > + }; > + }; > + }; > + > + be0: display-backend@01e60000 { > + compatible = "allwinner,sun5i-a13-display-backend"; > + reg = <0x01e60000 0x10000>; > + clocks = <&ahb_gates 44>, <&de_be_clk>, > + <&dram_gates 26>; > + clock-names = "ahb", "mod", > + "ram"; > + resets = <&de_be_clk>; > + status = "disabled"; > + > + assigned-clocks = <&de_be_clk>; > + assigned-clock-rates = <300000000>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + be0_in: port@0 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0>; > + > + be0_in_fe0: endpoint@0 { > + reg = <0>; > + remote-endpoint = <&fe0_out_be0>; > + }; > + }; > + > + be0_out: port@1 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <1>; > + > + be0_out_tcon0: endpoint@0 { > + reg = <0>; > + remote-endpoint = <&tcon0_in_be0>; > + }; > + }; > + }; > + }; > + }; > +}; > -- > 2.9.2 >
Hello Maxime, On Wed, Aug 31, 2016 at 10:18 AM, Maxime Ripard <maxime.ripard@free-electrons.com> wrote: [snip] > + > +#include "skeleton.dtsi" > + The skeleton.dtsi has been deprecated and shouldn't be used in new DTS files: http://www.spinics.net/lists/arm-kernel/msg528080.html Best regards, Javier
On Wed, Aug 31, 2016 at 4:18 PM, Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > From: Mylène Josserand <mylene.josserand@free-electrons.com> > > The GR8 is an SoC made by Nextthing loosely based on the sun5i family. > > Since it's not clear yet what we can factor out and merge with the A10s and > A13 support, let's keep it out of the sun5i.dtsi include tree. We will > figure out what can be shared when things settle down. > > Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> > --- > arch/arm/boot/dts/gr8.dtsi | 1080 ++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 1080 insertions(+) > create mode 100644 arch/arm/boot/dts/gr8.dtsi > > diff --git a/arch/arm/boot/dts/gr8.dtsi b/arch/arm/boot/dts/gr8.dtsi > new file mode 100644 > index 000000000000..d21cfa3f3c14 > --- /dev/null > +++ b/arch/arm/boot/dts/gr8.dtsi In the node names, you sometimes use underscores and sometimes use hyphens. Here are the ones I spotted: > + osc3M: osc3M_clk { > + pll3x2: pll3x2_clk { > + pll7x2: pll7x2_clk { > + display-engine { > + sram-controller@01c00000 { > + otg_sram: sram-section@0000 { > + dma: dma-controller@01c02000 { > + tve0: tv-encoder@01c0a000 { > + tcon0: lcd-controller@01c0c000 { > + intc: interrupt-controller@01c20400 { > + lcd_rgb666_pins: lcd_rgb666@0 { > + nand_pins_a: nand_base0@0 { > + nand_cs0_pins_a: nand_cs@0 { > + nand_rb0_pins_a: nand_rb@0 { > + uart1_cts_rts_pins_a: uart1-cts-rts@0 { > + fe0: display-frontend@01e00000 { > + be0: display-backend@01e60000 { Underscores should not be used in node names. [1][2] Since you're adding a new file here, please use hyphens instead. [1] https://www.mail-archive.com/linux-kernel%40vger.kernel.org/msg1122967.html [2] https://www.mail-archive.com/linux-kernel%40vger.kernel.org/msg1145633.html
Hi Javier, On Wed, Sep 07, 2016 at 04:51:55PM +0200, Javier Martinez Canillas wrote: > Hello Maxime, > > On Wed, Aug 31, 2016 at 10:18 AM, Maxime Ripard > <maxime.ripard@free-electrons.com> wrote: > > [snip] > > > + > > +#include "skeleton.dtsi" > > + > > The skeleton.dtsi has been deprecated and shouldn't be used in new DTS files: > > http://www.spinics.net/lists/arm-kernel/msg528080.html Ok, thanks, I'll change it in the v3. Maxime
On Wed, Sep 07, 2016 at 07:51:48PM +0200, Rask Ingemann Lambertsen wrote: > On Wed, Aug 31, 2016 at 4:18 PM, Maxime Ripard > <maxime.ripard@free-electrons.com> wrote: > > From: Mylène Josserand <mylene.josserand@free-electrons.com> > > > > The GR8 is an SoC made by Nextthing loosely based on the sun5i family. > > > > Since it's not clear yet what we can factor out and merge with the A10s and > > A13 support, let's keep it out of the sun5i.dtsi include tree. We will > > figure out what can be shared when things settle down. > > > > Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com> > > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> > > --- > > arch/arm/boot/dts/gr8.dtsi | 1080 ++++++++++++++++++++++++++++++++++++++++++++ > > 1 file changed, 1080 insertions(+) > > create mode 100644 arch/arm/boot/dts/gr8.dtsi > > > > diff --git a/arch/arm/boot/dts/gr8.dtsi b/arch/arm/boot/dts/gr8.dtsi > > new file mode 100644 > > index 000000000000..d21cfa3f3c14 > > --- /dev/null > > +++ b/arch/arm/boot/dts/gr8.dtsi > > In the node names, you sometimes use underscores and sometimes use hyphens. > Here are the ones I spotted: > > > + osc3M: osc3M_clk { > > + pll3x2: pll3x2_clk { > > + pll7x2: pll7x2_clk { > > + display-engine { > > + sram-controller@01c00000 { > > + otg_sram: sram-section@0000 { > > + dma: dma-controller@01c02000 { > > + tve0: tv-encoder@01c0a000 { > > + tcon0: lcd-controller@01c0c000 { > > + intc: interrupt-controller@01c20400 { > > + lcd_rgb666_pins: lcd_rgb666@0 { > > + nand_pins_a: nand_base0@0 { > > + nand_cs0_pins_a: nand_cs@0 { > > + nand_rb0_pins_a: nand_rb@0 { > > + uart1_cts_rts_pins_a: uart1-cts-rts@0 { > > + fe0: display-frontend@01e00000 { > > + be0: display-backend@01e60000 { > > Underscores should not be used in node names. [1][2] Since you're adding a > new file here, please use hyphens instead. I wonder what the rationale behind this is. The ePAPR clearly documents the underscore as being a valid character for the node names. I'll change the few inconsistencies though. Thanks! Maxime
diff --git a/arch/arm/boot/dts/gr8.dtsi b/arch/arm/boot/dts/gr8.dtsi new file mode 100644 index 000000000000..d21cfa3f3c14 --- /dev/null +++ b/arch/arm/boot/dts/gr8.dtsi @@ -0,0 +1,1080 @@ +/* + * Copyright 2016 Mylène Josserand + * + * Mylène Josserand <mylene.josserand@free-electrons.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "skeleton.dtsi" + +#include <dt-bindings/clock/sun4i-a10-pll2.h> +#include <dt-bindings/dma/sun4i-a10.h> +#include <dt-bindings/pinctrl/sun4i-a10.h> + +/ { + interrupt-parent = <&intc>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a8"; + reg = <0x0>; + clocks = <&cpu>; + }; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* + * This is a dummy clock, to be used as placeholder on + * other mux clocks when a specific parent clock is not + * yet implemented. It should be dropped when the driver + * is complete. + */ + dummy: dummy { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + osc24M: clk@01c20050 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-osc-clk"; + reg = <0x01c20050 0x4>; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + + osc3M: osc3M_clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + clocks = <&osc24M>; + clock-output-names = "osc3M"; + }; + + osc32k: clk@0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "osc32k"; + }; + + pll1: clk@01c20000 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-pll1-clk"; + reg = <0x01c20000 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll1"; + }; + + pll2: clk@01c20008 { + #clock-cells = <1>; + compatible = "allwinner,sun5i-a13-pll2-clk"; + reg = <0x01c20008 0x8>; + clocks = <&osc24M>; + clock-output-names = "pll2-1x", "pll2-2x", + "pll2-4x", "pll2-8x"; + }; + + pll3: clk@01c20010 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-pll3-clk"; + reg = <0x01c20010 0x4>; + clocks = <&osc3M>; + clock-output-names = "pll3"; + }; + + pll3x2: pll3x2_clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <2>; + clocks = <&pll3>; + clock-output-names = "pll3-2x"; + }; + + pll4: clk@01c20018 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-pll1-clk"; + reg = <0x01c20018 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll4"; + }; + + pll5: clk@01c20020 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-pll5-clk"; + reg = <0x01c20020 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll5_ddr", "pll5_other"; + }; + + pll6: clk@01c20028 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-pll6-clk"; + reg = <0x01c20028 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll6_sata", "pll6_other", "pll6"; + }; + + pll7: clk@01c20030 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-pll3-clk"; + reg = <0x01c20030 0x4>; + clocks = <&osc3M>; + clock-output-names = "pll7"; + }; + + pll7x2: pll7x2_clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <2>; + clocks = <&pll7>; + clock-output-names = "pll7-2x"; + }; + + /* dummy is 200M */ + cpu: cpu@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-cpu-clk"; + reg = <0x01c20054 0x4>; + clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; + clock-output-names = "cpu"; + }; + + axi: axi@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-axi-clk"; + reg = <0x01c20054 0x4>; + clocks = <&cpu>; + clock-output-names = "axi"; + }; + + ahb: ahb@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun5i-a13-ahb-clk"; + reg = <0x01c20054 0x4>; + clocks = <&axi>, <&cpu>, <&pll6 1>; + clock-output-names = "ahb"; + /* + * Use PLL6 as parent, instead of CPU/AXI + * which has rate changes due to cpufreq + */ + assigned-clocks = <&ahb>; + assigned-clock-parents = <&pll6 1>; + }; + + apb0: apb0@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-apb0-clk"; + reg = <0x01c20054 0x4>; + clocks = <&ahb>; + clock-output-names = "apb0"; + }; + + apb1: clk@01c20058 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-apb1-clk"; + reg = <0x01c20058 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&osc32k>; + clock-output-names = "apb1"; + }; + + axi_gates: clk@01c2005c { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-axi-gates-clk"; + reg = <0x01c2005c 0x4>; + clocks = <&axi>; + clock-indices = <0>; + clock-output-names = "axi_dram"; + }; + + ahb_gates: clk@01c20060 { + #clock-cells = <1>; + compatible = "allwinner,sun5i-a13-ahb-gates-clk"; + reg = <0x01c20060 0x8>; + clocks = <&ahb>; + clock-indices = <0>, <1>, + <2>, <5>, <6>, + <7>, <8>, <9>, + <10>, <13>, + <14>, <20>, + <21>, <22>, + <28>, <32>, <34>, + <36>, <40>, <44>, + <46>, <51>, + <52>; + clock-output-names = "ahb_usbotg", "ahb_ehci", + "ahb_ohci", "ahb_ss", "ahb_dma", + "ahb_bist", "ahb_mmc0", "ahb_mmc1", + "ahb_mmc2", "ahb_nand", + "ahb_sdram", "ahb_spi0", + "ahb_spi1", "ahb_spi2", + "ahb_stimer", "ahb_ve", "ahb_tve", + "ahb_lcd", "ahb_csi", "ahb_de_be", + "ahb_de_fe", "ahb_iep", + "ahb_mali400"; + }; + + apb0_gates: clk@01c20068 { + #clock-cells = <1>; + compatible = "allwinner,sun5i-a13-apb0-gates-clk"; + reg = <0x01c20068 0x4>; + clocks = <&apb0>; + clock-indices = <0>, <3>, + <5>, <6>; + clock-output-names = "apb0_codec", "apb0_i2s0", + "apb0_pio", "apb0_ir"; + }; + + apb1_gates: clk@01c2006c { + #clock-cells = <1>; + compatible = "allwinner,sun5i-a13-apb1-gates-clk"; + reg = <0x01c2006c 0x4>; + clocks = <&apb1>; + clock-indices = <0>, <1>, + <2>, <17>, + <18>; + clock-output-names = "apb1_i2c0", "apb1_i2c1", + "apb1_i2c2", "apb1_uart1", + "apb1_uart2"; + }; + + nand_clk: clk@01c20080 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c20080 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "nand"; + }; + + ms_clk: clk@01c20084 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c20084 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ms"; + }; + + mmc0_clk: clk@01c20088 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-mmc-clk"; + reg = <0x01c20088 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mmc0", + "mmc0_output", + "mmc0_sample"; + }; + + mmc1_clk: clk@01c2008c { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-mmc-clk"; + reg = <0x01c2008c 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mmc1", + "mmc1_output", + "mmc1_sample"; + }; + + mmc2_clk: clk@01c20090 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-mmc-clk"; + reg = <0x01c20090 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mmc2", + "mmc2_output", + "mmc2_sample"; + }; + + ts_clk: clk@01c20098 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c20098 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ts"; + }; + + ss_clk: clk@01c2009c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c2009c 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ss"; + }; + + spi0_clk: clk@01c200a0 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c200a0 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "spi0"; + }; + + spi1_clk: clk@01c200a4 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c200a4 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "spi1"; + }; + + spi2_clk: clk@01c200a8 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c200a8 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "spi2"; + }; + + ir0_clk: clk@01c200b0 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c200b0 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ir0"; + }; + + i2s0_clk: clk@01c200b8 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod1-clk"; + reg = <0x01c200b8 0x4>; + clocks = <&pll2 SUN4I_A10_PLL2_8X>, + <&pll2 SUN4I_A10_PLL2_4X>, + <&pll2 SUN4I_A10_PLL2_2X>, + <&pll2 SUN4I_A10_PLL2_1X>; + clock-output-names = "i2s0"; + }; + + spdif_clk: clk@01c200c0 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod1-clk"; + reg = <0x01c200c0 0x4>; + clocks = <&pll2 SUN4I_A10_PLL2_8X>, + <&pll2 SUN4I_A10_PLL2_4X>, + <&pll2 SUN4I_A10_PLL2_2X>, + <&pll2 SUN4I_A10_PLL2_1X>; + clock-output-names = "spdif"; + }; + + usb_clk: clk@01c200cc { + #clock-cells = <1>; + #reset-cells = <1>; + compatible = "allwinner,sun5i-a13-usb-clk"; + reg = <0x01c200cc 0x4>; + clocks = <&pll6 1>; + clock-output-names = "usb_ohci0", "usb_phy"; + }; + + dram_gates: clk@01c20100 { + #clock-cells = <1>; + compatible = "nextthing,gr8-dram-gates-clk", + "allwinner,sun4i-a10-gates-clk"; + reg = <0x01c20100 0x4>; + clocks = <&pll5 0>; + clock-indices = <0>, + <1>, + <25>, + <26>, + <29>, + <31>; + clock-output-names = "dram_ve", + "dram_csi", + "dram_de_fe", + "dram_de_be", + "dram_ace", + "dram_iep"; + }; + + de_be_clk: clk@01c20104 { + #clock-cells = <0>; + #reset-cells = <0>; + compatible = "allwinner,sun4i-a10-display-clk"; + reg = <0x01c20104 0x4>; + clocks = <&pll3>, <&pll7>, <&pll5 1>; + clock-output-names = "de-be"; + }; + + de_fe_clk: clk@01c2010c { + #clock-cells = <0>; + #reset-cells = <0>; + compatible = "allwinner,sun4i-a10-display-clk"; + reg = <0x01c2010c 0x4>; + clocks = <&pll3>, <&pll7>, <&pll5 1>; + clock-output-names = "de-fe"; + }; + + tcon_ch0_clk: clk@01c20118 { + #clock-cells = <0>; + #reset-cells = <1>; + compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; + reg = <0x01c20118 0x4>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; + clock-output-names = "tcon-ch0-sclk"; + }; + + tcon_ch1_clk: clk@01c2012c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; + reg = <0x01c2012c 0x4>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; + clock-output-names = "tcon-ch1-sclk"; + }; + + codec_clk: clk@01c20140 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-codec-clk"; + reg = <0x01c20140 0x4>; + clocks = <&pll2 SUN4I_A10_PLL2_1X>; + clock-output-names = "codec"; + }; + + mbus_clk: clk@01c2015c { + #clock-cells = <0>; + compatible = "allwinner,sun5i-a13-mbus-clk"; + reg = <0x01c2015c 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mbus"; + }; + }; + + display-engine { + compatible = "allwinner,sun5i-a13-display-engine"; + allwinner,pipelines = <&fe0>; + }; + + soc@01c00000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram-controller@01c00000 { + compatible = "allwinner,sun4i-a10-sram-controller"; + reg = <0x01c00000 0x30>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram_a: sram@00000000 { + compatible = "mmio-sram"; + reg = <0x00000000 0xc000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00000000 0xc000>; + }; + + sram_d: sram@00010000 { + compatible = "mmio-sram"; + reg = <0x00010000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00010000 0x1000>; + + otg_sram: sram-section@0000 { + compatible = "allwinner,sun4i-a10-sram-d"; + reg = <0x0000 0x1000>; + status = "disabled"; + }; + }; + }; + + dma: dma-controller@01c02000 { + compatible = "allwinner,sun4i-a10-dma"; + reg = <0x01c02000 0x1000>; + interrupts = <27>; + clocks = <&ahb_gates 6>; + #dma-cells = <2>; + }; + + nfc: nand@01c03000 { + compatible = "allwinner,sun4i-a10-nand"; + reg = <0x01c03000 0x1000>; + interrupts = <37>; + clocks = <&ahb_gates 13>, <&nand_clk>; + clock-names = "ahb", "mod"; + dmas = <&dma SUN4I_DMA_DEDICATED 3>; + dma-names = "rxtx"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi0: spi@01c05000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c05000 0x1000>; + interrupts = <10>; + clocks = <&ahb_gates 20>, <&spi0_clk>; + clock-names = "ahb", "mod"; + dmas = <&dma SUN4I_DMA_DEDICATED 27>, + <&dma SUN4I_DMA_DEDICATED 26>; + dma-names = "rx", "tx"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@01c06000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c06000 0x1000>; + interrupts = <11>; + clocks = <&ahb_gates 21>, <&spi1_clk>; + clock-names = "ahb", "mod"; + dmas = <&dma SUN4I_DMA_DEDICATED 9>, + <&dma SUN4I_DMA_DEDICATED 8>; + dma-names = "rx", "tx"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + tve0: tv-encoder@01c0a000 { + compatible = "allwinner,sun4i-a10-tv-encoder"; + reg = <0x01c0a000 0x1000>; + clocks = <&ahb_gates 34>; + resets = <&tcon_ch0_clk 0>; + status = "disabled"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + tve0_in_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_out_tve0>; + }; + }; + }; + + tcon0: lcd-controller@01c0c000 { + compatible = "allwinner,sun5i-a13-tcon"; + reg = <0x01c0c000 0x1000>; + interrupts = <44>; + resets = <&tcon_ch0_clk 1>; + reset-names = "lcd"; + clocks = <&ahb_gates 36>, + <&tcon_ch0_clk>, + <&tcon_ch1_clk>; + clock-names = "ahb", + "tcon-ch0", + "tcon-ch1"; + clock-output-names = "tcon-pixel-clock"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon0_in_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_out_tcon0>; + }; + }; + + tcon0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon0_out_tve0: endpoint@1 { + reg = <1>; + remote-endpoint = <&tve0_in_tcon0>; + }; + }; + }; + }; + + mmc0: mmc@01c0f000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ahb_gates 8>, + <&mmc0_clk 0>, + <&mmc0_clk 1>, + <&mmc0_clk 2>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + interrupts = <32>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc1: mmc@01c10000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ahb_gates 9>, + <&mmc1_clk 0>, + <&mmc1_clk 1>, + <&mmc1_clk 2>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + interrupts = <33>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc2: mmc@01c11000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c11000 0x1000>; + clocks = <&ahb_gates 10>, + <&mmc2_clk 0>, + <&mmc2_clk 1>, + <&mmc2_clk 2>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + interrupts = <34>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + usb_otg: usb@01c13000 { + compatible = "allwinner,sun4i-a10-musb"; + reg = <0x01c13000 0x0400>; + clocks = <&ahb_gates 0>; + interrupts = <38>; + interrupt-names = "mc"; + phys = <&usbphy 0>; + phy-names = "usb"; + extcon = <&usbphy 0>; + allwinner,sram = <&otg_sram 1>; + status = "disabled"; + + dr_mode = "otg"; + }; + + usbphy: phy@01c13400 { + #phy-cells = <1>; + compatible = "allwinner,sun5i-a13-usb-phy"; + reg = <0x01c13400 0x10 0x01c14800 0x4>; + reg-names = "phy_ctrl", "pmu1"; + clocks = <&usb_clk 8>; + clock-names = "usb_phy"; + resets = <&usb_clk 0>, <&usb_clk 1>; + reset-names = "usb0_reset", "usb1_reset"; + status = "disabled"; + }; + + ehci0: usb@01c14000 { + compatible = "allwinner,sun5i-a13-ehci", "generic-ehci"; + reg = <0x01c14000 0x100>; + interrupts = <39>; + clocks = <&ahb_gates 1>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci0: usb@01c14400 { + compatible = "allwinner,sun5i-a13-ohci", "generic-ohci"; + reg = <0x01c14400 0x100>; + interrupts = <40>; + clocks = <&usb_clk 6>, <&ahb_gates 2>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + spi2: spi@01c17000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c17000 0x1000>; + interrupts = <12>; + clocks = <&ahb_gates 22>, <&spi2_clk>; + clock-names = "ahb", "mod"; + dmas = <&dma SUN4I_DMA_DEDICATED 29>, + <&dma SUN4I_DMA_DEDICATED 28>; + dma-names = "rx", "tx"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + intc: interrupt-controller@01c20400 { + compatible = "allwinner,sun4i-a10-ic"; + reg = <0x01c20400 0x400>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + pio: pinctrl@01c20800 { + compatible = "nextthing,gr8-pinctrl"; + reg = <0x01c20800 0x400>; + interrupts = <28>; + clocks = <&apb0_gates 5>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <3>; + #gpio-cells = <3>; + + i2c0_pins_a: i2c0@0 { + allwinner,pins = "PB0", "PB1"; + allwinner,function = "i2c0"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + i2c1_pins_a: i2c1@0 { + allwinner,pins = "PB15", "PB16"; + allwinner,function = "i2c1"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + i2c2_pins_a: i2c2@0 { + allwinner,pins = "PB17", "PB18"; + allwinner,function = "i2c2"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + i2s0_pins_a: i2s0@0 { + allwinner,pins = "PB5", "PB6", "PB7", "PB8", "PB9"; + allwinner,function = "i2s0"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + ir0_rx_pins_a: ir0@0 { + allwinner,pins = "PB4"; + allwinner,function = "ir0"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + lcd_rgb666_pins: lcd_rgb666@0 { + allwinner,pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", + "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", + "PD18", "PD19", "PD20", "PD21", "PD22", "PD23", + "PD24", "PD25", "PD26", "PD27"; + allwinner,function = "lcd0"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + mmc0_pins_a: mmc0@0 { + allwinner,pins = "PF0", "PF1", "PF2", "PF3", + "PF4", "PF5"; + allwinner,function = "mmc0"; + allwinner,drive = <SUN4I_PINCTRL_30_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + nand_pins_a: nand_base0@0 { + allwinner,pins = "PC0", "PC1", "PC2", + "PC5", "PC8", "PC9", "PC10", + "PC11", "PC12", "PC13", "PC14", + "PC15"; + allwinner,function = "nand0"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + nand_cs0_pins_a: nand_cs@0 { + allwinner,pins = "PC4"; + allwinner,function = "nand0"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + nand_rb0_pins_a: nand_rb@0 { + allwinner,pins = "PC6"; + allwinner,function = "nand0"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + uart1_pins_a: uart1@1 { + allwinner,pins = "PG3", "PG4"; + allwinner,function = "uart1"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + uart1_cts_rts_pins_a: uart1-cts-rts@0 { + allwinner,pins = "PG5", "PG6"; + allwinner,function = "uart1"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + pwm0_pins_a: pwm0@0 { + allwinner,pins = "PB2"; + allwinner,function = "pwm0"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + spdif_tx_pins_a: spdif@0 { + allwinner,pins = "PB10"; + allwinner,function = "spdif"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; + }; + + pwm: pwm@01c20e00 { + compatible = "allwinner,sun5i-a10s-pwm"; + reg = <0x01c20e00 0xc>; + clocks = <&osc24M>; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@01c20c00 { + compatible = "allwinner,sun4i-a10-timer"; + reg = <0x01c20c00 0x90>; + interrupts = <22>; + clocks = <&osc24M>; + }; + + wdt: watchdog@01c20c90 { + compatible = "allwinner,sun4i-a10-wdt"; + reg = <0x01c20c90 0x10>; + }; + + spdif: spdif@01c21000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun4i-a10-spdif"; + reg = <0x01c21000 0x400>; + interrupts = <13>; + clocks = <&apb0_gates 1>, <&spdif_clk>; + clock-names = "apb", "spdif"; + dmas = <&dma SUN4I_DMA_NORMAL 2>, + <&dma SUN4I_DMA_NORMAL 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + ir0: ir@01c21800 { + compatible = "allwinner,sun4i-a10-ir"; + clocks = <&apb0_gates 6>, <&ir0_clk>; + clock-names = "apb", "ir"; + interrupts = <5>; + reg = <0x01c21800 0x40>; + status = "disabled"; + }; + + i2s0: i2s@01c22400 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun4i-a10-i2s"; + reg = <0x01c22400 0x400>; + interrupts = <16>; + clocks = <&apb0_gates 3>, <&i2s0_clk>; + clock-names = "apb", "mod"; + dmas = <&dma SUN4I_DMA_NORMAL 3>, + <&dma SUN4I_DMA_NORMAL 3>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lradc: lradc@01c22800 { + compatible = "allwinner,sun4i-a10-lradc-keys"; + reg = <0x01c22800 0x100>; + interrupts = <31>; + status = "disabled"; + }; + + codec: codec@01c22c00 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun4i-a10-codec"; + reg = <0x01c22c00 0x40>; + interrupts = <30>; + clocks = <&apb0_gates 0>, <&codec_clk>; + clock-names = "apb", "codec"; + dmas = <&dma SUN4I_DMA_NORMAL 19>, + <&dma SUN4I_DMA_NORMAL 19>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + rtp: rtp@01c25000 { + compatible = "allwinner,sun5i-a13-ts"; + reg = <0x01c25000 0x100>; + interrupts = <29>; + #thermal-sensor-cells = <0>; + }; + + uart1: serial@01c28400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28400 0x400>; + interrupts = <2>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb1_gates 17>; + status = "disabled"; + }; + + uart2: serial@01c28800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28800 0x400>; + interrupts = <3>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb1_gates 18>; + status = "disabled"; + }; + + i2c0: i2c@01c2ac00 { + compatible = "allwinner,sun4i-a10-i2c"; + reg = <0x01c2ac00 0x400>; + interrupts = <7>; + clocks = <&apb1_gates 0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@01c2b000 { + compatible = "allwinner,sun4i-a10-i2c"; + reg = <0x01c2b000 0x400>; + interrupts = <8>; + clocks = <&apb1_gates 1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@01c2b400 { + compatible = "allwinner,sun4i-a10-i2c"; + reg = <0x01c2b400 0x400>; + interrupts = <9>; + clocks = <&apb1_gates 2>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + timer@01c60000 { + compatible = "allwinner,sun5i-a13-hstimer"; + reg = <0x01c60000 0x1000>; + interrupts = <82>, <83>; + clocks = <&ahb_gates 28>; + }; + + fe0: display-frontend@01e00000 { + compatible = "allwinner,sun5i-a13-display-frontend"; + reg = <0x01e00000 0x20000>; + interrupts = <47>; + clocks = <&ahb_gates 46>, <&de_fe_clk>, + <&dram_gates 25>; + clock-names = "ahb", "mod", + "ram"; + resets = <&de_fe_clk>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + fe0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + fe0_out_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_in_fe0>; + }; + }; + }; + }; + + be0: display-backend@01e60000 { + compatible = "allwinner,sun5i-a13-display-backend"; + reg = <0x01e60000 0x10000>; + clocks = <&ahb_gates 44>, <&de_be_clk>, + <&dram_gates 26>; + clock-names = "ahb", "mod", + "ram"; + resets = <&de_be_clk>; + status = "disabled"; + + assigned-clocks = <&de_be_clk>; + assigned-clock-rates = <300000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + be0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + be0_in_fe0: endpoint@0 { + reg = <0>; + remote-endpoint = <&fe0_out_be0>; + }; + }; + + be0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + be0_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_be0>; + }; + }; + }; + }; + }; +};