| Message ID | 20161011184044.28373-1-cov@codeaurora.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 10/11/2016 01:40 PM, Christopher Covington wrote: > Beginning with a simple sanity check of the control register, add > a unit test for the ARM Performance Monitors Unit (PMU). As of > October 2016, whether KVM mode has a PMU at all is a tricky > question of which QEMU / mach-virt version is used. So only enable > the TCG mode tests for now. Given that we have KVM-based vPMU enabled in QEMU, it is very desirable for these unit testing cases to work on KVM. Right now both check_cycles_increase() and check_cpi() fail under KVM. I will help debug it. > > Signed-off-by: Christopher Covington <cov@codeaurora.org> > Reviewed-by: Andrew Jones <drjones@redhat.com> > --- > arm/Makefile.common | 3 +- > arm/pmu.c | 82 +++++++++++++++++++++++++++++++++++++++++++++++++++++ > arm/unittests.cfg | 14 +++++++++ > 3 files changed, 98 insertions(+), 1 deletion(-) > create mode 100644 arm/pmu.c > > diff --git a/arm/Makefile.common b/arm/Makefile.common > index ccb554d..f98f422 100644 > --- a/arm/Makefile.common > +++ b/arm/Makefile.common > @@ -11,7 +11,8 @@ endif > > tests-common = \ > $(TEST_DIR)/selftest.flat \ > - $(TEST_DIR)/spinlock-test.flat > + $(TEST_DIR)/spinlock-test.flat \ > + $(TEST_DIR)/pmu.flat > > all: test_cases > > diff --git a/arm/pmu.c b/arm/pmu.c > new file mode 100644 > index 0000000..42d0ee1 > --- /dev/null > +++ b/arm/pmu.c > @@ -0,0 +1,82 @@ > +/* > + * Test the ARM Performance Monitors Unit (PMU). > + * > + * Copyright 2015 The Linux Foundation. All rights reserved. > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU Lesser General Public License version 2.1 and > + * only version 2.1 as published by the Free Software Foundation. > + * > + * This program is distributed in the hope that it will be useful, but WITHOUT > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License > + * for more details. > + */ > +#include "libcflat.h" > + > +#if defined(__arm__) > +static inline uint32_t get_pmcr(void) > +{ > + uint32_t ret; > + > + asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (ret)); > + return ret; > +} > +#elif defined(__aarch64__) > +static inline uint32_t get_pmcr(void) > +{ > + uint32_t ret; > + > + asm volatile("mrs %0, pmcr_el0" : "=r" (ret)); > + return ret; > +} > +#endif > + > +struct pmu_data { > + union { > + uint32_t pmcr_el0; > + struct { > + uint32_t enable:1; > + uint32_t event_counter_reset:1; > + uint32_t cycle_counter_reset:1; > + uint32_t cycle_counter_clock_divider:1; > + uint32_t event_counter_export:1; > + uint32_t cycle_counter_disable_when_prohibited:1; > + uint32_t cycle_counter_long:1; > + uint32_t reserved:4; > + uint32_t counters:5; > + uint32_t identification_code:8; > + uint32_t implementer:8; > + }; > + }; > +}; > + > +/* > + * As a simple sanity check on the PMCR_EL0, ensure the implementer field isn't > + * null. Also print out a couple other interesting fields for diagnostic > + * purposes. For example, as of fall 2015, QEMU TCG mode doesn't implement > + * event counters and therefore reports zero event counters, but hopefully > + * support for at least the instructions event will be added in the future and > + * the reported number of event counters will become nonzero. > + */ > +static bool check_pmcr(void) > +{ > + struct pmu_data pmu; > + > + pmu.pmcr_el0 = get_pmcr(); > + > + printf("PMU implementer: %c\n", pmu.implementer); > + printf("Identification code: 0x%x\n", pmu.identification_code); > + printf("Event counters: %d\n", pmu.counters); > + > + return pmu.implementer != 0; > +} > + > +int main(void) > +{ > + report_prefix_push("pmu"); > + > + report("Control register", check_pmcr()); > + > + return report_summary(); > +} > diff --git a/arm/unittests.cfg b/arm/unittests.cfg > index ffd12e5..edaed4a 100644 > --- a/arm/unittests.cfg > +++ b/arm/unittests.cfg > @@ -51,3 +51,17 @@ file = selftest.flat > smp = $MAX_SMP > extra_params = -append 'smp' > groups = selftest > + > +# Test PMU support with -icount IPC=1 > +[pmu-icount-1] > +file = pmu.flat > +extra_params = -icount 0 -append '1' > +groups = pmu > +accel = tcg > + > +# Test PMU support with -icount IPC=256 > +[pmu-icount-256] > +file = pmu.flat > +extra_params = -icount 8 -append '256' > +groups = pmu > +accel = tcg >
diff --git a/arm/Makefile.common b/arm/Makefile.common index ccb554d..f98f422 100644 --- a/arm/Makefile.common +++ b/arm/Makefile.common @@ -11,7 +11,8 @@ endif tests-common = \ $(TEST_DIR)/selftest.flat \ - $(TEST_DIR)/spinlock-test.flat + $(TEST_DIR)/spinlock-test.flat \ + $(TEST_DIR)/pmu.flat all: test_cases diff --git a/arm/pmu.c b/arm/pmu.c new file mode 100644 index 0000000..42d0ee1 --- /dev/null +++ b/arm/pmu.c @@ -0,0 +1,82 @@ +/* + * Test the ARM Performance Monitors Unit (PMU). + * + * Copyright 2015 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU Lesser General Public License version 2.1 and + * only version 2.1 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License + * for more details. + */ +#include "libcflat.h" + +#if defined(__arm__) +static inline uint32_t get_pmcr(void) +{ + uint32_t ret; + + asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (ret)); + return ret; +} +#elif defined(__aarch64__) +static inline uint32_t get_pmcr(void) +{ + uint32_t ret; + + asm volatile("mrs %0, pmcr_el0" : "=r" (ret)); + return ret; +} +#endif + +struct pmu_data { + union { + uint32_t pmcr_el0; + struct { + uint32_t enable:1; + uint32_t event_counter_reset:1; + uint32_t cycle_counter_reset:1; + uint32_t cycle_counter_clock_divider:1; + uint32_t event_counter_export:1; + uint32_t cycle_counter_disable_when_prohibited:1; + uint32_t cycle_counter_long:1; + uint32_t reserved:4; + uint32_t counters:5; + uint32_t identification_code:8; + uint32_t implementer:8; + }; + }; +}; + +/* + * As a simple sanity check on the PMCR_EL0, ensure the implementer field isn't + * null. Also print out a couple other interesting fields for diagnostic + * purposes. For example, as of fall 2015, QEMU TCG mode doesn't implement + * event counters and therefore reports zero event counters, but hopefully + * support for at least the instructions event will be added in the future and + * the reported number of event counters will become nonzero. + */ +static bool check_pmcr(void) +{ + struct pmu_data pmu; + + pmu.pmcr_el0 = get_pmcr(); + + printf("PMU implementer: %c\n", pmu.implementer); + printf("Identification code: 0x%x\n", pmu.identification_code); + printf("Event counters: %d\n", pmu.counters); + + return pmu.implementer != 0; +} + +int main(void) +{ + report_prefix_push("pmu"); + + report("Control register", check_pmcr()); + + return report_summary(); +} diff --git a/arm/unittests.cfg b/arm/unittests.cfg index ffd12e5..edaed4a 100644 --- a/arm/unittests.cfg +++ b/arm/unittests.cfg @@ -51,3 +51,17 @@ file = selftest.flat smp = $MAX_SMP extra_params = -append 'smp' groups = selftest + +# Test PMU support with -icount IPC=1 +[pmu-icount-1] +file = pmu.flat +extra_params = -icount 0 -append '1' +groups = pmu +accel = tcg + +# Test PMU support with -icount IPC=256 +[pmu-icount-256] +file = pmu.flat +extra_params = -icount 8 -append '256' +groups = pmu +accel = tcg