| Message ID | 20110609175313.GG24424@n2100.arm.linux.org.uk (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Thu, Jun 09, 2011 at 06:53:13PM +0100, Russell King - ARM Linux wrote: > On Thu, Jun 09, 2011 at 06:12:55PM +0100, Russell King - ARM Linux wrote: > > > 3. Avoid direct write to AUXCTRL in generic suspend code. > > > > This is the only problematical one that I can see. We need to restore > > this on systems running in secure mode. What we could do is rather than > > writing to the register, read it first and compare its value with what > > was saved to see whether we need to write it. > > > > Then, if platforms run in non-secure mode, they are responsible for > > restoring that register back to its pre-suspend value before their > > assembly calls cpu_resume(). > > And here's a patch which does that: Ping. > 8<----------- > From: Russell King <rmk+kernel@arm.linux.org.uk> > ARM: Avoid writing to auxctrl register unless it needs to be updated > > As the auxiliary control register is not writable in non-secure mode > such as on OMAP, we must avoid writing the register when resuming in > non-secure mode. Avoid this by moving the responsibility to the > SoC code in this case to ensure that the auxiliary control register > is restored before cpu_resume() is called. > > Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> > -- > arch/arm/mm/proc-v7.S | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S > index 3c38678..fa1e6d5 100644 > --- a/arch/arm/mm/proc-v7.S > +++ b/arch/arm/mm/proc-v7.S > @@ -237,7 +237,9 @@ ENTRY(cpu_v7_do_resume) > mcr p15, 0, r7, c2, c0, 0 @ TTB 0 > mcr p15, 0, r8, c2, c0, 1 @ TTB 1 > mcr p15, 0, ip, c2, c0, 2 @ TTB control register > - mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register > + mrc p15, 0, r4, c1, c0, 1 @ Read auxiliary control register > + teq r4, r10 > + mcrne p15, 0, r10, c1, c0, 1 @ Auxiliary control register > mcr p15, 0, r11, c1, c0, 2 @ Co-processor access control > ldr r4, =PRRR @ PRRR > ldr r5, =NMRR @ NMRR > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 3c38678..fa1e6d5 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -237,7 +237,9 @@ ENTRY(cpu_v7_do_resume) mcr p15, 0, r7, c2, c0, 0 @ TTB 0 mcr p15, 0, r8, c2, c0, 1 @ TTB 1 mcr p15, 0, ip, c2, c0, 2 @ TTB control register - mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register + mrc p15, 0, r4, c1, c0, 1 @ Read auxiliary control register + teq r4, r10 + mcrne p15, 0, r10, c1, c0, 1 @ Auxiliary control register mcr p15, 0, r11, c1, c0, 2 @ Co-processor access control ldr r4, =PRRR @ PRRR ldr r5, =NMRR @ NMRR