diff mbox

[4/8] drm/i915/huc: Add debugfs for HuC loading status check

Message ID 1475520182-9224-5-git-send-email-anusha.srivatsa@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Srivatsa, Anusha Oct. 3, 2016, 6:42 p.m. UTC 
From: Peter Antoine <peter.antoine@intel.com>

Add debugfs entry for HuC loading status check.

v2: rebase on-top of drm-intel-nightly.
v3: rebased again.
v7: rebased.
v8: rebased.

Tested-by: Xiang Haihao <haihao.xiang@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

Comments

jeff.mcgee@intel.com Oct. 13, 2016, 5:49 p.m. UTC | #1 
Reviewed-by: Jeff McGee <jeff.mcgee@intel.com>

On Mon, Oct 03, 2016 at 11:42:58AM -0700, Anusha Srivatsa wrote:
> From: Peter Antoine <peter.antoine@intel.com>
> 
> Add debugfs entry for HuC loading status check.
> 
> v2: rebase on-top of drm-intel-nightly.
> v3: rebased again.
> v7: rebased.
> v8: rebased.
> 
> Tested-by: Xiang Haihao <haihao.xiang@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 31 +++++++++++++++++++++++++++++++
>  1 file changed, 31 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 44258a8..7bd0e23 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2413,6 +2413,36 @@ static int i915_llc(struct seq_file *m, void *data)
>  	return 0;
>  }
>  
> +static int i915_huc_load_status_info(struct seq_file *m, void *data)
> +{
> +	struct drm_i915_private *dev_priv = node_to_i915(m->private);
> +	struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
> +
> +	if (!HAS_HUC_UCODE(dev_priv))
> +		return 0;
> +
> +	seq_puts(m, "HuC firmware status:\n");
> +	seq_printf(m, "\tpath: %s\n", huc_fw->uc_fw_path);
> +	seq_printf(m, "\tfetch: %s\n",
> +		intel_uc_fw_status_repr(huc_fw->fetch_status));
> +	seq_printf(m, "\tload: %s\n",
> +		intel_uc_fw_status_repr(huc_fw->load_status));
> +	seq_printf(m, "\tversion wanted: %d.%d\n",
> +		huc_fw->major_ver_wanted, huc_fw->minor_ver_wanted);
> +	seq_printf(m, "\tversion found: %d.%d\n",
> +		huc_fw->major_ver_found, huc_fw->minor_ver_found);
> +	seq_printf(m, "\theader: offset is %d; size = %d\n",
> +		huc_fw->header_offset, huc_fw->header_size);
> +	seq_printf(m, "\tuCode: offset is %d; size = %d\n",
> +		huc_fw->ucode_offset, huc_fw->ucode_size);
> +	seq_printf(m, "\tRSA: offset is %d; size = %d\n",
> +		huc_fw->rsa_offset, huc_fw->rsa_size);
> +
> +	seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2));
> +
> +	return 0;
> +}
> +
>  static int i915_guc_load_status_info(struct seq_file *m, void *data)
>  {
>  	struct drm_i915_private *dev_priv = node_to_i915(m->private);
> @@ -4427,6 +4457,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
>  	{"i915_guc_info", i915_guc_info, 0},
>  	{"i915_guc_load_status", i915_guc_load_status_info, 0},
>  	{"i915_guc_log_dump", i915_guc_log_dump, 0},
> +	{"i915_huc_load_status", i915_huc_load_status_info, 0},
>  	{"i915_frequency_info", i915_frequency_info, 0},
>  	{"i915_hangcheck_info", i915_hangcheck_info, 0},
>  	{"i915_drpc_info", i915_drpc_info, 0},
> -- 
> 2.7.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Santa, Carlos Oct. 24, 2016, 11:48 p.m. UTC | #2 
Tested with HuC version 1.07.1398 on SKL.
Reviewed-by: Carlos Santa <carlos.santa@intel.com>
Tested-by: Carlos Santa <carlos.santa@intel.com>


On Mon, 2016-10-03 at 11:42 -0700, Anusha Srivatsa wrote:
> From: Peter Antoine <peter.antoine@intel.com>
> 
> Add debugfs entry for HuC loading status check.
> 
> v2: rebase on-top of drm-intel-nightly.
> v3: rebased again.
> v7: rebased.
> v8: rebased.
> 
> Tested-by: Xiang Haihao <haihao.xiang@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 31
> +++++++++++++++++++++++++++++++
>  1 file changed, 31 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 44258a8..7bd0e23 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2413,6 +2413,36 @@ static int i915_llc(struct seq_file *m, void
> *data)
>  	return 0;
>  }
>  
> +static int i915_huc_load_status_info(struct seq_file *m, void *data)
> +{
> +	struct drm_i915_private *dev_priv = node_to_i915(m-
> >private);
> +	struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
> +
> +	if (!HAS_HUC_UCODE(dev_priv))
> +		return 0;
> +
> +	seq_puts(m, "HuC firmware status:\n");
> +	seq_printf(m, "\tpath: %s\n", huc_fw->uc_fw_path);
> +	seq_printf(m, "\tfetch: %s\n",
> +		intel_uc_fw_status_repr(huc_fw->fetch_status));
> +	seq_printf(m, "\tload: %s\n",
> +		intel_uc_fw_status_repr(huc_fw->load_status));
> +	seq_printf(m, "\tversion wanted: %d.%d\n",
> +		huc_fw->major_ver_wanted, huc_fw->minor_ver_wanted);
> +	seq_printf(m, "\tversion found: %d.%d\n",
> +		huc_fw->major_ver_found, huc_fw->minor_ver_found);
> +	seq_printf(m, "\theader: offset is %d; size = %d\n",
> +		huc_fw->header_offset, huc_fw->header_size);
> +	seq_printf(m, "\tuCode: offset is %d; size = %d\n",
> +		huc_fw->ucode_offset, huc_fw->ucode_size);
> +	seq_printf(m, "\tRSA: offset is %d; size = %d\n",
> +		huc_fw->rsa_offset, huc_fw->rsa_size);
> +
> +	seq_printf(m, "\nHuC status 0x%08x:\n",
> I915_READ(HUC_STATUS2));
> +
> +	return 0;
> +}
> +
>  static int i915_guc_load_status_info(struct seq_file *m, void *data)
>  {
>  	struct drm_i915_private *dev_priv = node_to_i915(m-
> >private);
> @@ -4427,6 +4457,7 @@ static const struct drm_info_list
> i915_debugfs_list[] = {
>  	{"i915_guc_info", i915_guc_info, 0},
>  	{"i915_guc_load_status", i915_guc_load_status_info, 0},
>  	{"i915_guc_log_dump", i915_guc_log_dump, 0},
> +	{"i915_huc_load_status", i915_huc_load_status_info, 0},
>  	{"i915_frequency_info", i915_frequency_info, 0},
>  	{"i915_hangcheck_info", i915_hangcheck_info, 0},
>  	{"i915_drpc_info", i915_drpc_info, 0},
Santa, Carlos Oct. 25, 2016, 10:14 p.m. UTC | #3 
Tested with HuC version 1.07.1398 on SKL.

Reviewed-by: Carlos Santa <carlos.santa@intel.com>
Tested-by: Carlos Santa <carlos.santa@intel.com>

On Mon, 2016-10-03 at 11:42 -0700, Anusha Srivatsa wrote:
> From: Peter Antoine <peter.antoine@intel.com>
> 
> Add debugfs entry for HuC loading status check.
> 
> v2: rebase on-top of drm-intel-nightly.
> v3: rebased again.
> v7: rebased.
> v8: rebased.
> 
> Tested-by: Xiang Haihao <haihao.xiang@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 31
> +++++++++++++++++++++++++++++++
>  1 file changed, 31 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 44258a8..7bd0e23 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2413,6 +2413,36 @@ static int i915_llc(struct seq_file *m, void
> *data)
>  	return 0;
>  }
>  
> +static int i915_huc_load_status_info(struct seq_file *m, void *data)
> +{
> +	struct drm_i915_private *dev_priv = node_to_i915(m-
> >private);
> +	struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
> +
> +	if (!HAS_HUC_UCODE(dev_priv))
> +		return 0;
> +
> +	seq_puts(m, "HuC firmware status:\n");
> +	seq_printf(m, "\tpath: %s\n", huc_fw->uc_fw_path);
> +	seq_printf(m, "\tfetch: %s\n",
> +		intel_uc_fw_status_repr(huc_fw->fetch_status));
> +	seq_printf(m, "\tload: %s\n",
> +		intel_uc_fw_status_repr(huc_fw->load_status));
> +	seq_printf(m, "\tversion wanted: %d.%d\n",
> +		huc_fw->major_ver_wanted, huc_fw->minor_ver_wanted);
> +	seq_printf(m, "\tversion found: %d.%d\n",
> +		huc_fw->major_ver_found, huc_fw->minor_ver_found);
> +	seq_printf(m, "\theader: offset is %d; size = %d\n",
> +		huc_fw->header_offset, huc_fw->header_size);
> +	seq_printf(m, "\tuCode: offset is %d; size = %d\n",
> +		huc_fw->ucode_offset, huc_fw->ucode_size);
> +	seq_printf(m, "\tRSA: offset is %d; size = %d\n",
> +		huc_fw->rsa_offset, huc_fw->rsa_size);
> +
> +	seq_printf(m, "\nHuC status 0x%08x:\n",
> I915_READ(HUC_STATUS2));
> +
> +	return 0;
> +}
> +
>  static int i915_guc_load_status_info(struct seq_file *m, void *data)
>  {
>  	struct drm_i915_private *dev_priv = node_to_i915(m-
> >private);
> @@ -4427,6 +4457,7 @@ static const struct drm_info_list
> i915_debugfs_list[] = {
>  	{"i915_guc_info", i915_guc_info, 0},
>  	{"i915_guc_load_status", i915_guc_load_status_info, 0},
>  	{"i915_guc_log_dump", i915_guc_log_dump, 0},
> +	{"i915_huc_load_status", i915_huc_load_status_info, 0},
>  	{"i915_frequency_info", i915_frequency_info, 0},
>  	{"i915_hangcheck_info", i915_hangcheck_info, 0},
>  	{"i915_drpc_info", i915_drpc_info, 0},
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 44258a8..7bd0e23 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2413,6 +2413,36 @@  static int i915_llc(struct seq_file *m, void *data)
 	return 0;
 }
 
+static int i915_huc_load_status_info(struct seq_file *m, void *data)
+{
+	struct drm_i915_private *dev_priv = node_to_i915(m->private);
+	struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
+
+	if (!HAS_HUC_UCODE(dev_priv))
+		return 0;
+
+	seq_puts(m, "HuC firmware status:\n");
+	seq_printf(m, "\tpath: %s\n", huc_fw->uc_fw_path);
+	seq_printf(m, "\tfetch: %s\n",
+		intel_uc_fw_status_repr(huc_fw->fetch_status));
+	seq_printf(m, "\tload: %s\n",
+		intel_uc_fw_status_repr(huc_fw->load_status));
+	seq_printf(m, "\tversion wanted: %d.%d\n",
+		huc_fw->major_ver_wanted, huc_fw->minor_ver_wanted);
+	seq_printf(m, "\tversion found: %d.%d\n",
+		huc_fw->major_ver_found, huc_fw->minor_ver_found);
+	seq_printf(m, "\theader: offset is %d; size = %d\n",
+		huc_fw->header_offset, huc_fw->header_size);
+	seq_printf(m, "\tuCode: offset is %d; size = %d\n",
+		huc_fw->ucode_offset, huc_fw->ucode_size);
+	seq_printf(m, "\tRSA: offset is %d; size = %d\n",
+		huc_fw->rsa_offset, huc_fw->rsa_size);
+
+	seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2));
+
+	return 0;
+}
+
 static int i915_guc_load_status_info(struct seq_file *m, void *data)
 {
 	struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -4427,6 +4457,7 @@  static const struct drm_info_list i915_debugfs_list[] = {
 	{"i915_guc_info", i915_guc_info, 0},
 	{"i915_guc_load_status", i915_guc_load_status_info, 0},
 	{"i915_guc_log_dump", i915_guc_log_dump, 0},
+	{"i915_huc_load_status", i915_huc_load_status_info, 0},
 	{"i915_frequency_info", i915_frequency_info, 0},
 	{"i915_hangcheck_info", i915_hangcheck_info, 0},
 	{"i915_drpc_info", i915_drpc_info, 0},