| Message ID | 1477998697-22284-1-git-send-email-ander.conselvan.de.oliveira@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On ti, 2016-11-01 at 13:11 +0200, Ander Conselvan de Oliveira wrote: > Hardware engineers confirmed that writing to it has no effect, as implied by > the FIXME comment. > > Cc: Imre Deak <imre.deak@intel.com> > Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> You could also remove the corresponding comment from bxt_ddi_phy_verify_state(), either way: Reviewed-by: Imre Deak <imre.deak@intel.com> > --- > drivers/gpu/drm/i915/intel_dpio_phy.c | 16 ---------------- > 1 file changed, 16 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c > index 4a6164a..e95b291 100644 > --- a/drivers/gpu/drm/i915/intel_dpio_phy.c > +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c > @@ -365,22 +365,6 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv, > I915_WRITE(BXT_PORT_CL2CM_DW6(phy), val); > } > > - val = I915_READ(BXT_PORT_CL1CM_DW30(phy)); > - val &= ~OCL2_LDOFUSE_PWR_DIS; > - /* > - * On PHY1 disable power on the second channel, since no port is > - * connected there. On PHY0 both channels have a port, so leave it > - * enabled. > - * TODO: port C is only connected on BXT-P, so on BXT0/1 we should > - * power down the second channel on PHY0 as well. > - * > - * FIXME: Clarify programming of the following, the register is > - * read-only with bit 6 fixed at 0 at least in stepping A. > - */ > - if (!phy_info->dual_channel) > - val |= OCL2_LDOFUSE_PWR_DIS; > - I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val); > - > if (phy_info->rcomp_phy != -1) { > uint32_t grc_code; > /*
> == Series Details == > > Series: drm/i915/bxt: Don't set OCL2_LDOFUSE_PWR_DIS bit in phy init > sequence (rev2) > URL : https://patchwork.freedesktop.org/series/14669/ > State : warning > > == Summary == > > Series 14669v2 drm/i915/bxt: Don't set OCL2_LDOFUSE_PWR_DIS bit in phy > init sequence > https://patchwork.freedesktop.org/api/1.0/series/14669/revisions/2/mbox/ > > Test drv_module_reload_basic: > pass -> DMESG-WARN (fi-skl-6770hq) Still using IGT 1.16-g5bfbbea that has no Jani's patches. But CI builds done today should have that fix. > Test kms_cursor_legacy: > Subgroup basic-busy-flip-before-cursor-varying-size: > pass -> DMESG-WARN (fi-ilk-650) > Test kms_pipe_crc_basic: > Subgroup bad-nb-words-3: > dmesg-warn -> PASS (fi-ilk-650) > Subgroup bad-source: > dmesg-warn -> PASS (fi-ilk-650) > Subgroup nonblocking-crc-pipe-a-frame-sequence: > dmesg-warn -> PASS (fi-ilk-650) > Subgroup nonblocking-crc-pipe-b-frame-sequence: > pass -> DMESG-WARN (fi-ilk-650) > Subgroup read-crc-pipe-b: > pass -> DMESG-WARN (fi-ilk-650) > Subgroup suspend-read-crc-pipe-a: > dmesg-warn -> PASS (fi-ilk-650) For ILK-650 Dwarns: https://bugs.freedesktop.org/show_bug.cgi?id=98531 > fi-ilk-650 total:241 pass:183 dwarn:4 dfail:0 fail:0 skip:54 > > c5ad9c11e819eebcad5b9be5aa5e991e89b26965 drm-intel-nightly: 2016y- > 11m-01d-16h-36m-25s UTC integration manifest > 4a635f6 drm/i915/bxt: Don't set OCL2_LDOFUSE_PWR_DIS bit in phy init > sequence > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_2884/ Jani Saarinen Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
On Wed, 2016-11-02 at 07:24 +0000, Saarinen, Jani wrote: > > > > == Series Details == > > > > Series: drm/i915/bxt: Don't set OCL2_LDOFUSE_PWR_DIS bit in phy init > > sequence (rev2) > > URL : https://patchwork.freedesktop.org/series/14669/ > > State : warning > > > > == Summary == > > > > Series 14669v2 drm/i915/bxt: Don't set OCL2_LDOFUSE_PWR_DIS bit in phy > > init sequence > > https://patchwork.freedesktop.org/api/1.0/series/14669/revisions/2/mbox/ > > > > Test drv_module_reload_basic: > > pass -> DMESG-WARN (fi-skl-6770hq) > Still using IGT 1.16-g5bfbbea that has no Jani's patches. But CI builds done > today should have that fix. > > > > > Test kms_cursor_legacy: > > Subgroup basic-busy-flip-before-cursor-varying-size: > > pass -> DMESG-WARN (fi-ilk-650) > > Test kms_pipe_crc_basic: > > Subgroup bad-nb-words-3: > > dmesg-warn -> PASS (fi-ilk-650) > > Subgroup bad-source: > > dmesg-warn -> PASS (fi-ilk-650) > > Subgroup nonblocking-crc-pipe-a-frame-sequence: > > dmesg-warn -> PASS (fi-ilk-650) > > Subgroup nonblocking-crc-pipe-b-frame-sequence: > > pass -> DMESG-WARN (fi-ilk-650) > > Subgroup read-crc-pipe-b: > > pass -> DMESG-WARN (fi-ilk-650) > > Subgroup suspend-read-crc-pipe-a: > > dmesg-warn -> PASS (fi-ilk-650) > For ILK-650 Dwarns: https://bugs.freedesktop.org/show_bug.cgi?id=98531 Thanks. Patch pushed. Ander > > > > > fi-ilk-650 total:241 pass:183 dwarn:4 dfail:0 fail:0 skip:54 > > > > c5ad9c11e819eebcad5b9be5aa5e991e89b26965 drm-intel-nightly: 2016y- > > 11m-01d-16h-36m-25s UTC integration manifest > > 4a635f6 drm/i915/bxt: Don't set OCL2_LDOFUSE_PWR_DIS bit in phy init > > sequence > > > > == Logs == > > > > For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_2884/ > > Jani Saarinen > Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo > > > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c index 4a6164a..e95b291 100644 --- a/drivers/gpu/drm/i915/intel_dpio_phy.c +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c @@ -365,22 +365,6 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv, I915_WRITE(BXT_PORT_CL2CM_DW6(phy), val); } - val = I915_READ(BXT_PORT_CL1CM_DW30(phy)); - val &= ~OCL2_LDOFUSE_PWR_DIS; - /* - * On PHY1 disable power on the second channel, since no port is - * connected there. On PHY0 both channels have a port, so leave it - * enabled. - * TODO: port C is only connected on BXT-P, so on BXT0/1 we should - * power down the second channel on PHY0 as well. - * - * FIXME: Clarify programming of the following, the register is - * read-only with bit 6 fixed at 0 at least in stepping A. - */ - if (!phy_info->dual_channel) - val |= OCL2_LDOFUSE_PWR_DIS; - I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val); - if (phy_info->rcomp_phy != -1) { uint32_t grc_code; /*
Hardware engineers confirmed that writing to it has no effect, as implied by the FIXME comment. Cc: Imre Deak <imre.deak@intel.com> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> --- drivers/gpu/drm/i915/intel_dpio_phy.c | 16 ---------------- 1 file changed, 16 deletions(-)