| Message ID | 20161107144445.14069-4-kbastian@mail.uni-paderborn.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 11/07/2016 03:44 PM, Bastian Koppelmann wrote: > From: Peer Adelt <peer.adelt@c-lab.de> > > Puts the content of data register D[a] into E[c][63:32] and the > content of data register D[b] into E[c][31:0]. > > [BK: fix style error] > Signed-off-by: Peer Adelt <peer.adelt@c-lab.de> > Message-Id: <1465314555-11501-4-git-send-email-peer.adelt@c-lab.de> > --- > target-tricore/translate.c | 15 +++++++++++++++ > target-tricore/tricore-opcodes.h | 1 + > 2 files changed, 16 insertions(+) > > diff --git a/target-tricore/translate.c b/target-tricore/translate.c > index 3fec353..4fe8a5f 100644 > --- a/target-tricore/translate.c > +++ b/target-tricore/translate.c > @@ -6034,11 +6034,15 @@ static void decode_rr_accumulator(CPUTriCoreState *env, DisasContext *ctx) > uint32_t op2; > int r3, r2, r1; > > + TCGv temp; > + > r3 = MASK_OP_RR_D(ctx->opcode); > r2 = MASK_OP_RR_S2(ctx->opcode); > r1 = MASK_OP_RR_S1(ctx->opcode); > op2 = MASK_OP_RR_OP2(ctx->opcode); > > + temp = tcg_temp_new(); There's no reason to allocate temp here, for all of the insns that don't require it, as opposed to ... > + > switch (op2) { > case OPC2_32_RR_ABS: > gen_abs(cpu_gpr_d[r3], cpu_gpr_d[r2]); > @@ -6224,6 +6228,16 @@ static void decode_rr_accumulator(CPUTriCoreState *env, DisasContext *ctx) > case OPC2_32_RR_MOV: > tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); > break; > + case OPC2_32_RR_MOV_64: > + if (tricore_feature(env, TRICORE_FEATURE_16)) { > + CHECK_REG_PAIR(r3); ... here within the IF, right before it's used. > + tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); > + tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); > + tcg_gen_mov_tl(cpu_gpr_d[r3 + 1], temp); And freed here... > + } else { > + generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); > + } > + break; > case OPC2_32_RR_NE: > tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], > cpu_gpr_d[r2]); > @@ -6344,6 +6358,7 @@ static void decode_rr_accumulator(CPUTriCoreState *env, DisasContext *ctx) > default: > generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); > } > + tcg_temp_free(temp); ... not here. r~
diff --git a/target-tricore/translate.c b/target-tricore/translate.c index 3fec353..4fe8a5f 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -6034,11 +6034,15 @@ static void decode_rr_accumulator(CPUTriCoreState *env, DisasContext *ctx) uint32_t op2; int r3, r2, r1; + TCGv temp; + r3 = MASK_OP_RR_D(ctx->opcode); r2 = MASK_OP_RR_S2(ctx->opcode); r1 = MASK_OP_RR_S1(ctx->opcode); op2 = MASK_OP_RR_OP2(ctx->opcode); + temp = tcg_temp_new(); + switch (op2) { case OPC2_32_RR_ABS: gen_abs(cpu_gpr_d[r3], cpu_gpr_d[r2]); @@ -6224,6 +6228,16 @@ static void decode_rr_accumulator(CPUTriCoreState *env, DisasContext *ctx) case OPC2_32_RR_MOV: tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); break; + case OPC2_32_RR_MOV_64: + if (tricore_feature(env, TRICORE_FEATURE_16)) { + CHECK_REG_PAIR(r3); + tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); + tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); + tcg_gen_mov_tl(cpu_gpr_d[r3 + 1], temp); + } else { + generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); + } + break; case OPC2_32_RR_NE: tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); @@ -6344,6 +6358,7 @@ static void decode_rr_accumulator(CPUTriCoreState *env, DisasContext *ctx) default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } + tcg_temp_free(temp); } static void decode_rr_logical_shift(CPUTriCoreState *env, DisasContext *ctx) diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h index df666b0..78ba338 100644 --- a/target-tricore/tricore-opcodes.h +++ b/target-tricore/tricore-opcodes.h @@ -1062,6 +1062,7 @@ enum { OPC2_32_RR_MIN_H = 0x78, OPC2_32_RR_MIN_HU = 0x79, OPC2_32_RR_MOV = 0x1f, + OPC2_32_RR_MOV_64 = 0x81, OPC2_32_RR_NE = 0x11, OPC2_32_RR_OR_EQ = 0x27, OPC2_32_RR_OR_GE = 0x2b,