diff mbox

[v2] drm/i915/glk: Reuse broxton code for geminilake

Message ID 1478871063-7238-1-git-send-email-ander.conselvan.de.oliveira@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Ander Conselvan de Oliveira Nov. 11, 2016, 1:31 p.m. UTC 
Geminilake is mostly backwards compatible with broxton, so change most
of the IS_BROXTON() checks to IS_GEN9_LP(). Differences between the
platforms will be implemented in follow-up patches.

v2: Don't reuse broxton's path in intel_update_max_cdclk().
    Don't set plane count as in broxton.

v3: Rebase

v4: Include the check intel_bios_is_port_hpd_inverted().
    Commit message.

v5: Leave i915_dmc_info() out; glk's csr version != bxt's. (Rodrigo)

Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c     | 10 +++++-----
 drivers/gpu/drm/i915/i915_gem_gtt.c     |  8 ++++----
 drivers/gpu/drm/i915/i915_irq.c         | 10 +++++-----
 drivers/gpu/drm/i915/i915_reg.h         |  4 ++--
 drivers/gpu/drm/i915/intel_bios.c       |  2 +-
 drivers/gpu/drm/i915/intel_ddi.c        | 10 +++++-----
 drivers/gpu/drm/i915/intel_display.c    |  8 ++++----
 drivers/gpu/drm/i915/intel_dp.c         | 20 ++++++++++----------
 drivers/gpu/drm/i915/intel_dpll_mgr.c   |  2 +-
 drivers/gpu/drm/i915/intel_dsi.c        | 28 ++++++++++++++--------------
 drivers/gpu/drm/i915/intel_dsi_pll.c    | 12 ++++++------
 drivers/gpu/drm/i915/intel_hdmi.c       |  6 +++---
 drivers/gpu/drm/i915/intel_i2c.c        |  4 ++--
 drivers/gpu/drm/i915/intel_mocs.c       |  2 +-
 drivers/gpu/drm/i915/intel_panel.c      |  2 +-
 drivers/gpu/drm/i915/intel_pm.c         |  6 +++---
 drivers/gpu/drm/i915/intel_runtime_pm.c |  6 +++---
 17 files changed, 70 insertions(+), 70 deletions(-)

Comments

Ander Conselvan de Oliveira Nov. 11, 2016, 1:53 p.m. UTC | #1 
Resent with proper --in-reply-to . Please ignore.

On Fri, 2016-11-11 at 15:31 +0200, Ander Conselvan de Oliveira wrote:
> Geminilake is mostly backwards compatible with broxton, so change most
> of the IS_BROXTON() checks to IS_GEN9_LP(). Differences between the
> platforms will be implemented in follow-up patches.
> 
> v2: Don't reuse broxton's path in intel_update_max_cdclk().
>     Don't set plane count as in broxton.
> 
> v3: Rebase
> 
> v4: Include the check intel_bios_is_port_hpd_inverted().
>     Commit message.
> 
> v5: Leave i915_dmc_info() out; glk's csr version != bxt's. (Rodrigo)
> 
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.
> com>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c     | 10 +++++-----
>  drivers/gpu/drm/i915/i915_gem_gtt.c     |  8 ++++----
>  drivers/gpu/drm/i915/i915_irq.c         | 10 +++++-----
>  drivers/gpu/drm/i915/i915_reg.h         |  4 ++--
>  drivers/gpu/drm/i915/intel_bios.c       |  2 +-
>  drivers/gpu/drm/i915/intel_ddi.c        | 10 +++++-----
>  drivers/gpu/drm/i915/intel_display.c    |  8 ++++----
>  drivers/gpu/drm/i915/intel_dp.c         | 20 ++++++++++----------
>  drivers/gpu/drm/i915/intel_dpll_mgr.c   |  2 +-
>  drivers/gpu/drm/i915/intel_dsi.c        | 28 ++++++++++++++--------------
>  drivers/gpu/drm/i915/intel_dsi_pll.c    | 12 ++++++------
>  drivers/gpu/drm/i915/intel_hdmi.c       |  6 +++---
>  drivers/gpu/drm/i915/intel_i2c.c        |  4 ++--
>  drivers/gpu/drm/i915/intel_mocs.c       |  2 +-
>  drivers/gpu/drm/i915/intel_panel.c      |  2 +-
>  drivers/gpu/drm/i915/intel_pm.c         |  6 +++---
>  drivers/gpu/drm/i915/intel_runtime_pm.c |  6 +++---
>  17 files changed, 70 insertions(+), 70 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index b681d42..5d349d6 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1128,7 +1128,7 @@ static int i915_frequency_info(struct seq_file *m, void
> *unused)
>  		int max_freq;
>  
>  		rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
> -		if (IS_BROXTON(dev_priv)) {
> +		if (IS_GEN9_LP(dev_priv)) {
>  			rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
>  			gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
>  		} else {
> @@ -1224,7 +1224,7 @@ static int i915_frequency_info(struct seq_file *m, void
> *unused)
>  		seq_printf(m, "Down threshold: %d%%\n",
>  			   dev_priv->rps.down_threshold);
>  
> -		max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 0 :
> +		max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
>  			    rp_state_cap >> 16) & 0xff;
>  		max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
>  			     GEN9_FREQ_SCALER : 1);
> @@ -1237,7 +1237,7 @@ static int i915_frequency_info(struct seq_file *m, void
> *unused)
>  		seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
>  			   intel_gpu_freq(dev_priv, max_freq));
>  
> -		max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 16 :
> +		max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
>  			    rp_state_cap >> 0) & 0xff;
>  		max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
>  			     GEN9_FREQ_SCALER : 1);
> @@ -5185,7 +5185,7 @@ static void gen9_sseu_device_status(struct
> drm_i915_private *dev_priv,
>  	u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
>  
>  	/* BXT has a single slice and at most 3 subslices. */
> -	if (IS_BROXTON(dev_priv)) {
> +	if (IS_GEN9_LP(dev_priv)) {
>  		s_max = 1;
>  		ss_max = 3;
>  	}
> @@ -5219,7 +5219,7 @@ static void gen9_sseu_device_status(struct
> drm_i915_private *dev_priv,
>  		for (ss = 0; ss < ss_max; ss++) {
>  			unsigned int eu_cnt;
>  
> -			if (IS_BROXTON(dev_priv)) {
> +			if (IS_GEN9_LP(dev_priv)) {
>  				if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
>  					/* skip disabled subslice */
>  					continue;
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index a5fafa3..36483a2 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -377,7 +377,7 @@ static void kunmap_page_dma(struct drm_i915_private
> *dev_priv, void *vaddr)
>  	/* There are only few exceptions for gen >=6. chv and bxt.
>  	 * And we are not sure about the latter so play safe for now.
>  	 */
> -	if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
> +	if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
>  		drm_clflush_virt_range(vaddr, PAGE_SIZE);
>  
>  	kunmap_atomic(vaddr);
> @@ -2946,7 +2946,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64
> size)
>  	 * resort to an uncached mapping. The WC issue is easily caught by
> the
>  	 * readback check when writing GTT PTE entries.
>  	 */
> -	if (IS_BROXTON(to_i915(ggtt->base.dev)))
> +	if (IS_GEN9_LP(to_i915(ggtt->base.dev)))
>  		ggtt->gsm = ioremap_nocache(phys_addr, size);
>  	else
>  		ggtt->gsm = ioremap_wc(phys_addr, size);
> @@ -3078,7 +3078,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
>  
>  	ggtt->base.total = (size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
>  
> -	if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
> +	if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
>  		chv_setup_private_ppat(dev_priv);
>  	else
>  		bdw_setup_private_ppat(dev_priv);
> @@ -3319,7 +3319,7 @@ void i915_gem_restore_gtt_mappings(struct drm_device
> *dev)
>  	ggtt->base.closed = false;
>  
>  	if (INTEL_INFO(dev)->gen >= 8) {
> -		if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
> +		if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
>  			chv_setup_private_ppat(dev_priv);
>  		else
>  			bdw_setup_private_ppat(dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 6d7505b..081b3b7 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2435,7 +2435,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv,
> u32 master_ctl)
>  				found = true;
>  			}
>  
> -			if (IS_BROXTON(dev_priv)) {
> +			if (IS_GEN9_LP(dev_priv)) {
>  				tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
>  				if (tmp_mask) {
>  					bxt_hpd_irq_handler(dev_priv,
> tmp_mask,
> @@ -2451,7 +2451,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv,
> u32 master_ctl)
>  				}
>  			}
>  
> -			if (IS_BROXTON(dev_priv) && (iir &
> BXT_DE_PORT_GMBUS)) {
> +			if (IS_GEN9_LP(dev_priv) && (iir &
> BXT_DE_PORT_GMBUS)) {
>  				gmbus_irq_handler(dev_priv);
>  				found = true;
>  			}
> @@ -3379,7 +3379,7 @@ static void gen8_de_irq_postinstall(struct
> drm_i915_private *dev_priv)
>  				  GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
>  		de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
>  				  GEN9_AUX_CHANNEL_D;
> -		if (IS_BROXTON(dev_priv))
> +		if (IS_GEN9_LP(dev_priv))
>  			de_port_masked |= BXT_DE_PORT_GMBUS;
>  	} else {
>  		de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
> @@ -3390,7 +3390,7 @@ static void gen8_de_irq_postinstall(struct
> drm_i915_private *dev_priv)
>  					   GEN8_PIPE_FIFO_UNDERRUN;
>  
>  	de_port_enables = de_port_masked;
> -	if (IS_BROXTON(dev_priv))
> +	if (IS_GEN9_LP(dev_priv))
>  		de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
>  	else if (IS_BROADWELL(dev_priv))
>  		de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
> @@ -4215,7 +4215,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
>  		dev->driver->irq_uninstall = gen8_irq_uninstall;
>  		dev->driver->enable_vblank = gen8_enable_vblank;
>  		dev->driver->disable_vblank = gen8_disable_vblank;
> -		if (IS_BROXTON(dev_priv))
> +		if (IS_GEN9_LP(dev_priv))
>  			dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
>  		else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
>  			dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3361d7f..1be2a7d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2920,7 +2920,7 @@ enum skl_disp_power_wells {
>  #define INTERVAL_1_33_US(us)	(((us) * 3)   >> 2)
>  #define INTERVAL_0_833_US(us)	(((us) * 6) / 5)
>  #define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN9(dev_priv) ? \
> -				(IS_BROXTON(dev_priv) ? \
> +				(IS_GEN9_LP(dev_priv) ? \
>  				INTERVAL_0_833_US(us) : \
>  				INTERVAL_1_33_US(us)) : \
>  				INTERVAL_1_28_US(us))
> @@ -2929,7 +2929,7 @@ enum skl_disp_power_wells {
>  #define INTERVAL_1_33_TO_US(interval)  (((interval) << 2) / 3)
>  #define INTERVAL_0_833_TO_US(interval) (((interval) * 5)  / 6)
>  #define GT_PM_INTERVAL_TO_US(dev_priv, interval) (IS_GEN9(dev_priv) ? \
> -                           (IS_BROXTON(dev_priv) ? \
> +                           (IS_GEN9_LP(dev_priv) ? \
>                             INTERVAL_0_833_TO_US(interval) : \
>                             INTERVAL_1_33_TO_US(interval)) : \
>                             INTERVAL_1_28_TO_US(interval))
> diff --git a/drivers/gpu/drm/i915/intel_bios.c
> b/drivers/gpu/drm/i915/intel_bios.c
> index 5ab646e..bd705f9 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -1765,7 +1765,7 @@ intel_bios_is_port_hpd_inverted(struct drm_i915_private
> *dev_priv,
>  {
>  	int i;
>  
> -	if (WARN_ON_ONCE(!IS_BROXTON(dev_priv)))
> +	if (WARN_ON_ONCE(!IS_GEN9_LP(dev_priv)))
>  		return false;
>  
>  	for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 0ad4e16..a129ffa 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -442,7 +442,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private
> *dev_priv, enum port por
>  
>  	hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
>  
> -	if (IS_BROXTON(dev_priv))
> +	if (IS_GEN9_LP(dev_priv))
>  		return hdmi_level;
>  
>  	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> @@ -1091,7 +1091,7 @@ void intel_ddi_clock_get(struct intel_encoder *encoder,
>  		hsw_ddi_clock_get(encoder, pipe_config);
>  	else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
>  		skl_ddi_clock_get(encoder, pipe_config);
> -	else if (IS_BROXTON(dev_priv))
> +	else if (IS_GEN9_LP(dev_priv))
>  		bxt_ddi_clock_get(encoder, pipe_config);
>  }
>  
> @@ -1153,7 +1153,7 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
>  	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
>  		return skl_ddi_pll_select(intel_crtc, crtc_state,
>  					  intel_encoder);
> -	else if (IS_BROXTON(dev_priv))
> +	else if (IS_GEN9_LP(dev_priv))
>  		return bxt_ddi_pll_select(intel_crtc, crtc_state,
>  					  intel_encoder);
>  	else
> @@ -1643,7 +1643,7 @@ uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
>  
>  	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
>  		skl_ddi_set_iboost(encoder, level);
> -	else if (IS_BROXTON(dev_priv))
> +	else if (IS_GEN9_LP(dev_priv))
>  		bxt_ddi_vswing_sequence(dev_priv, level, port, encoder-
> >type);
>  
>  	return DDI_BUF_TRANS_SELECT(level);
> @@ -2246,7 +2246,7 @@ void intel_ddi_init(struct drm_device *dev, enum port
> port)
>  	 * configuration so that we use the proper lane count for our
>  	 * calculations.
>  	 */
> -	if (IS_BROXTON(dev_priv) && port == PORT_A) {
> +	if (IS_GEN9_LP(dev_priv) && port == PORT_A) {
>  		if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
>  			DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES
> for port A; fixing\n");
>  			intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 01dbf1b..723ff9d 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -614,12 +614,12 @@ static bool intel_PLL_is_valid(struct drm_i915_private
> *dev_priv,
>  		INTELPllInvalid("m1 out of range\n");
>  
>  	if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
> -	    !IS_CHERRYVIEW(dev_priv) && !IS_BROXTON(dev_priv))
> +	    !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
>  		if (clock->m1 <= clock->m2)
>  			INTELPllInvalid("m1 <= m2\n");
>  
>  	if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
> -	    !IS_BROXTON(dev_priv)) {
> +	    !IS_GEN9_LP(dev_priv)) {
>  		if (clock->p < limit->p.min || limit->p.max < clock->p)
>  			INTELPllInvalid("p out of range\n");
>  		if (clock->m < limit->m.min || limit->m.max < clock->m)
> @@ -10675,7 +10675,7 @@ static void haswell_get_ddi_port_state(struct
> intel_crtc *crtc,
>  
>  	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
>  		skylake_get_ddi_pll(dev_priv, port, pipe_config);
> -	else if (IS_BROXTON(dev_priv))
> +	else if (IS_GEN9_LP(dev_priv))
>  		bxt_get_ddi_pll(dev_priv, port, pipe_config);
>  	else
>  		haswell_get_ddi_pll(dev_priv, port, pipe_config);
> @@ -10721,7 +10721,7 @@ static bool haswell_get_pipe_config(struct intel_crtc
> *crtc,
>  
>  	active = hsw_get_transcoder_state(crtc, pipe_config,
> &power_domain_mask);
>  
> -	if (IS_BROXTON(dev_priv) &&
> +	if (IS_GEN9_LP(dev_priv) &&
>  	    bxt_get_dsi_transcoder_state(crtc, pipe_config,
> &power_domain_mask)) {
>  		WARN_ON(active);
>  		active = true;
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 117a714..675e103 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -233,7 +233,7 @@ intel_dp_source_rates(struct intel_dp *intel_dp, const int
> **source_rates)
>  	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
>  	int size;
>  
> -	if (IS_BROXTON(dev_priv)) {
> +	if (IS_GEN9_LP(dev_priv)) {
>  		*source_rates = bxt_rates;
>  		size = ARRAY_SIZE(bxt_rates);
>  	} else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> @@ -688,7 +688,7 @@ static void intel_pps_get_registers(struct
> drm_i915_private *dev_priv,
>  
>  	memset(regs, 0, sizeof(*regs));
>  
> -	if (IS_BROXTON(dev_priv))
> +	if (IS_GEN9_LP(dev_priv))
>  		pps_idx = bxt_power_sequencer_idx(intel_dp);
>  	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  		pps_idx = vlv_power_sequencer_pipe(intel_dp);
> @@ -697,7 +697,7 @@ static void intel_pps_get_registers(struct
> drm_i915_private *dev_priv,
>  	regs->pp_stat = PP_STATUS(pps_idx);
>  	regs->pp_on = PP_ON_DELAYS(pps_idx);
>  	regs->pp_off = PP_OFF_DELAYS(pps_idx);
> -	if (!IS_BROXTON(dev_priv))
> +	if (!IS_GEN9_LP(dev_priv))
>  		regs->pp_div = PP_DIVISOR(pps_idx);
>  }
>  
> @@ -2984,7 +2984,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	enum port port = dp_to_dig_port(intel_dp)->port;
>  
> -	if (IS_BROXTON(dev_priv))
> +	if (IS_GEN9_LP(dev_priv))
>  		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
>  	else if (INTEL_INFO(dev)->gen >= 9) {
>  		if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
> @@ -4300,7 +4300,7 @@ static bool intel_digital_port_connected(struct
> drm_i915_private *dev_priv,
>  		return ibx_digital_port_connected(dev_priv, port);
>  	else if (HAS_PCH_SPLIT(dev_priv))
>  		return cpt_digital_port_connected(dev_priv, port);
> -	else if (IS_BROXTON(dev_priv))
> +	else if (IS_GEN9_LP(dev_priv))
>  		return bxt_digital_port_connected(dev_priv, port);
>  	else if (IS_GM45(dev_priv))
>  		return gm45_digital_port_connected(dev_priv, port);
> @@ -4932,7 +4932,7 @@ intel_pps_readout_hw_state(struct drm_i915_private
> *dev_priv,
>  
>  	pp_on = I915_READ(regs.pp_on);
>  	pp_off = I915_READ(regs.pp_off);
> -	if (!IS_BROXTON(dev_priv)) {
> +	if (!IS_GEN9_LP(dev_priv)) {
>  		I915_WRITE(regs.pp_ctrl, pp_ctl);
>  		pp_div = I915_READ(regs.pp_div);
>  	}
> @@ -4950,7 +4950,7 @@ intel_pps_readout_hw_state(struct drm_i915_private
> *dev_priv,
>  	seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
>  		   PANEL_POWER_DOWN_DELAY_SHIFT;
>  
> -	if (IS_BROXTON(dev_priv)) {
> +	if (IS_GEN9_LP(dev_priv)) {
>  		u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
>  			BXT_POWER_CYCLE_DELAY_SHIFT;
>  		if (tmp > 0)
> @@ -5081,7 +5081,7 @@ intel_dp_init_panel_power_sequencer_registers(struct
> drm_device *dev,
>  		 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
>  	/* Compute the divisor for the pp clock, simply match the Bspec
>  	 * formula. */
> -	if (IS_BROXTON(dev_priv)) {
> +	if (IS_GEN9_LP(dev_priv)) {
>  		pp_div = I915_READ(regs.pp_ctrl);
>  		pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
>  		pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
> @@ -5107,7 +5107,7 @@ intel_dp_init_panel_power_sequencer_registers(struct
> drm_device *dev,
>  
>  	I915_WRITE(regs.pp_on, pp_on);
>  	I915_WRITE(regs.pp_off, pp_off);
> -	if (IS_BROXTON(dev_priv))
> +	if (IS_GEN9_LP(dev_priv))
>  		I915_WRITE(regs.pp_ctrl, pp_div);
>  	else
>  		I915_WRITE(regs.pp_div, pp_div);
> @@ -5115,7 +5115,7 @@ intel_dp_init_panel_power_sequencer_registers(struct
> drm_device *dev,
>  	DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x,
> PP_OFF %#x, PP_DIV %#x\n",
>  		      I915_READ(regs.pp_on),
>  		      I915_READ(regs.pp_off),
> -		      IS_BROXTON(dev_priv) ?
> +		      IS_GEN9_LP(dev_priv) ?
>  		      (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK)
> :
>  		      I915_READ(regs.pp_div));
>  }
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 21853a1..8205c1c 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -1861,7 +1861,7 @@ void intel_shared_dpll_init(struct drm_device *dev)
>  
>  	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
>  		dpll_mgr = &skl_pll_mgr;
> -	else if (IS_BROXTON(dev_priv))
> +	else if (IS_GEN9_LP(dev_priv))
>  		dpll_mgr = &bxt_pll_mgr;
>  	else if (HAS_DDI(dev_priv))
>  		dpll_mgr = &hsw_pll_mgr;
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c
> b/drivers/gpu/drm/i915/intel_dsi.c
> index 4e0d025..4e19fbc 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -340,7 +340,7 @@ static bool intel_dsi_compute_config(struct intel_encoder
> *encoder,
>  	/* DSI uses short packets for sync events, so clear mode flags for
> DSI */
>  	adjusted_mode->flags = 0;
>  
> -	if (IS_BROXTON(dev_priv)) {
> +	if (IS_GEN9_LP(dev_priv)) {
>  		/* Dual link goes to DSI transcoder A. */
>  		if (intel_dsi->ports == BIT(PORT_C))
>  			pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
> @@ -441,7 +441,7 @@ static void intel_dsi_device_ready(struct intel_encoder
> *encoder)
>  
>  	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  		vlv_dsi_device_ready(encoder);
> -	else if (IS_BROXTON(dev_priv))
> +	else if (IS_GEN9_LP(dev_priv))
>  		bxt_dsi_device_ready(encoder);
>  }
>  
> @@ -464,7 +464,7 @@ static void intel_dsi_port_enable(struct intel_encoder
> *encoder)
>  	}
>  
>  	for_each_dsi_port(port, intel_dsi->ports) {
> -		i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
> +		i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
>  			BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
>  		u32 temp;
>  
> @@ -494,7 +494,7 @@ static void intel_dsi_port_disable(struct intel_encoder
> *encoder)
>  	enum port port;
>  
>  	for_each_dsi_port(port, intel_dsi->ports) {
> -		i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
> +		i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
>  			BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
>  		u32 temp;
>  
> @@ -663,7 +663,7 @@ static void intel_dsi_clear_device_ready(struct
> intel_encoder *encoder)
>  	DRM_DEBUG_KMS("\n");
>  	for_each_dsi_port(port, intel_dsi->ports) {
>  		/* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV
> */
> -		i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
> +		i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
>  			BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
>  		u32 val;
>  
> @@ -755,12 +755,12 @@ static bool intel_dsi_get_hw_state(struct intel_encoder
> *encoder,
>  	 * configuration, otherwise accessing DSI registers will hang the
>  	 * machine. See BSpec North Display Engine registers/MIPI[BXT].
>  	 */
> -	if (IS_BROXTON(dev_priv) && !intel_dsi_pll_is_enabled(dev_priv))
> +	if (IS_GEN9_LP(dev_priv) && !intel_dsi_pll_is_enabled(dev_priv))
>  		goto out_put_power;
>  
>  	/* XXX: this only works for one DSI output */
>  	for_each_dsi_port(port, intel_dsi->ports) {
> -		i915_reg_t ctrl_reg = IS_BROXTON(dev_priv) ?
> +		i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ?
>  			BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
>  		bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE;
>  
> @@ -785,7 +785,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder
> *encoder,
>  		if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))
>  			continue;
>  
> -		if (IS_BROXTON(dev_priv)) {
> +		if (IS_GEN9_LP(dev_priv)) {
>  			u32 tmp = I915_READ(MIPI_CTRL(port));
>  			tmp &= BXT_PIPE_SELECT_MASK;
>  			tmp >>= BXT_PIPE_SELECT_SHIFT;
> @@ -973,7 +973,7 @@ static void intel_dsi_get_config(struct intel_encoder
> *encoder,
>  	u32 pclk;
>  	DRM_DEBUG_KMS("\n");
>  
> -	if (IS_BROXTON(dev_priv))
> +	if (IS_GEN9_LP(dev_priv))
>  		bxt_dsi_get_pipe_config(encoder, pipe_config);
>  
>  	pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp,
> @@ -1065,7 +1065,7 @@ static void set_dsi_timings(struct drm_encoder *encoder,
>  	hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
>  
>  	for_each_dsi_port(port, intel_dsi->ports) {
> -		if (IS_BROXTON(dev_priv)) {
> +		if (IS_GEN9_LP(dev_priv)) {
>  			/*
>  			 * Program hdisplay and vdisplay on MIPI transcoder.
>  			 * This is different from calculated hactive and
> @@ -1152,7 +1152,7 @@ static void intel_dsi_prepare(struct intel_encoder
> *intel_encoder,
>  			tmp &= ~READ_REQUEST_PRIORITY_MASK;
>  			I915_WRITE(MIPI_CTRL(port), tmp |
>  					READ_REQUEST_PRIORITY_HIGH);
> -		} else if (IS_BROXTON(dev_priv)) {
> +		} else if (IS_GEN9_LP(dev_priv)) {
>  			enum pipe pipe = intel_crtc->pipe;
>  
>  			tmp = I915_READ(MIPI_CTRL(port));
> @@ -1241,7 +1241,7 @@ static void intel_dsi_prepare(struct intel_encoder
> *intel_encoder,
>  		I915_WRITE(MIPI_INIT_COUNT(port),
>  				txclkesc(intel_dsi->escape_clk_div, 100));
>  
> -		if (IS_BROXTON(dev_priv) && (!intel_dsi->dual_link)) {
> +		if (IS_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) {
>  			/*
>  			 * BXT spec says write MIPI_INIT_COUNT for
>  			 * both the ports, even if only one is
> @@ -1451,7 +1451,7 @@ void intel_dsi_init(struct drm_device *dev)
>  
>  	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
>  		dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
> -	} else if (IS_BROXTON(dev_priv)) {
> +	} else if (IS_GEN9_LP(dev_priv)) {
>  		dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
>  	} else {
>  		DRM_ERROR("Unsupported Mipi device to reg base");
> @@ -1492,7 +1492,7 @@ void intel_dsi_init(struct drm_device *dev)
>  	 * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI
> DSI
>  	 * port C. BXT isn't limited like this.
>  	 */
> -	if (IS_BROXTON(dev_priv))
> +	if (IS_GEN9_LP(dev_priv))
>  		intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) |
> BIT(PIPE_C);
>  	else if (port == PORT_A)
>  		intel_encoder->crtc_mask = BIT(PIPE_A);
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c
> b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index 56eff60..cf8c1b0 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -351,7 +351,7 @@ static u32 bxt_dsi_get_pclk(struct intel_encoder *encoder,
> int pipe_bpp,
>  u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
>  		       struct intel_crtc_state *config)
>  {
> -	if (IS_BROXTON(to_i915(encoder->base.dev)))
> +	if (IS_GEN9_LP(to_i915(encoder->base.dev)))
>  		return bxt_dsi_get_pclk(encoder, pipe_bpp, config);
>  	else
>  		return vlv_dsi_get_pclk(encoder, pipe_bpp, config);
> @@ -504,7 +504,7 @@ static void bxt_enable_dsi_pll(struct intel_encoder
> *encoder,
>  
>  bool intel_dsi_pll_is_enabled(struct drm_i915_private *dev_priv)
>  {
> -	if (IS_BROXTON(dev_priv))
> +	if (IS_GEN9_LP(dev_priv))
>  		return bxt_dsi_pll_is_enabled(dev_priv);
>  
>  	MISSING_CASE(INTEL_DEVID(dev_priv));
> @@ -519,7 +519,7 @@ int intel_compute_dsi_pll(struct intel_encoder *encoder,
>  
>  	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  		return vlv_compute_dsi_pll(encoder, config);
> -	else if (IS_BROXTON(dev_priv))
> +	else if (IS_GEN9_LP(dev_priv))
>  		return bxt_compute_dsi_pll(encoder, config);
>  
>  	return -ENODEV;
> @@ -532,7 +532,7 @@ void intel_enable_dsi_pll(struct intel_encoder *encoder,
>  
>  	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  		vlv_enable_dsi_pll(encoder, config);
> -	else if (IS_BROXTON(dev_priv))
> +	else if (IS_GEN9_LP(dev_priv))
>  		bxt_enable_dsi_pll(encoder, config);
>  }
>  
> @@ -542,7 +542,7 @@ void intel_disable_dsi_pll(struct intel_encoder *encoder)
>  
>  	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  		vlv_disable_dsi_pll(encoder);
> -	else if (IS_BROXTON(dev_priv))
> +	else if (IS_GEN9_LP(dev_priv))
>  		bxt_disable_dsi_pll(encoder);
>  }
>  
> @@ -566,7 +566,7 @@ void intel_dsi_reset_clocks(struct intel_encoder *encoder,
> enum port port)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  
> -	if (IS_BROXTON(dev_priv))
> +	if (IS_GEN9_LP(dev_priv))
>  		bxt_dsi_reset_clocks(encoder, port);
>  	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  		vlv_dsi_reset_clocks(encoder, port);
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
> b/drivers/gpu/drm/i915/intel_hdmi.c
> index fb88e32..034ec1a2 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1246,7 +1246,7 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi,
>  		return MODE_CLOCK_HIGH;
>  
>  	/* BXT DPLL can't generate 223-240 MHz */
> -	if (IS_BROXTON(dev_priv) && clock > 223333 && clock < 240000)
> +	if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
>  		return MODE_CLOCK_RANGE;
>  
>  	/* CHV DPLL can't generate 216-240 MHz */
> @@ -1809,13 +1809,13 @@ static u8 intel_hdmi_ddc_pin(struct drm_i915_private
> *dev_priv,
>  
>  	switch (port) {
>  	case PORT_B:
> -		if (IS_BROXTON(dev_priv))
> +		if (IS_GEN9_LP(dev_priv))
>  			ddc_pin = GMBUS_PIN_1_BXT;
>  		else
>  			ddc_pin = GMBUS_PIN_DPB;
>  		break;
>  	case PORT_C:
> -		if (IS_BROXTON(dev_priv))
> +		if (IS_GEN9_LP(dev_priv))
>  			ddc_pin = GMBUS_PIN_2_BXT;
>  		else
>  			ddc_pin = GMBUS_PIN_DPC;
> diff --git a/drivers/gpu/drm/i915/intel_i2c.c
> b/drivers/gpu/drm/i915/intel_i2c.c
> index 83f260b..1606e31 100644
> --- a/drivers/gpu/drm/i915/intel_i2c.c
> +++ b/drivers/gpu/drm/i915/intel_i2c.c
> @@ -72,7 +72,7 @@ static const struct gmbus_pin gmbus_pins_bxt[] = {
>  static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private
> *dev_priv,
>  					     unsigned int pin)
>  {
> -	if (IS_BROXTON(dev_priv))
> +	if (IS_GEN9_LP(dev_priv))
>  		return &gmbus_pins_bxt[pin];
>  	else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
>  		return &gmbus_pins_skl[pin];
> @@ -87,7 +87,7 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private
> *dev_priv,
>  {
>  	unsigned int size;
>  
> -	if (IS_BROXTON(dev_priv))
> +	if (IS_GEN9_LP(dev_priv))
>  		size = ARRAY_SIZE(gmbus_pins_bxt);
>  	else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
>  		size = ARRAY_SIZE(gmbus_pins_skl);
> diff --git a/drivers/gpu/drm/i915/intel_mocs.c
> b/drivers/gpu/drm/i915/intel_mocs.c
> index 80bb924..eed0707 100644
> --- a/drivers/gpu/drm/i915/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/intel_mocs.c
> @@ -182,7 +182,7 @@ static bool get_mocs_settings(struct drm_i915_private
> *dev_priv,
>  		table->size  = ARRAY_SIZE(skylake_mocs_table);
>  		table->table = skylake_mocs_table;
>  		result = true;
> -	} else if (IS_BROXTON(dev_priv)) {
> +	} else if (IS_GEN9_LP(dev_priv)) {
>  		table->size  = ARRAY_SIZE(broxton_mocs_table);
>  		table->table = broxton_mocs_table;
>  		result = true;
> diff --git a/drivers/gpu/drm/i915/intel_panel.c
> b/drivers/gpu/drm/i915/intel_panel.c
> index be4b4d5..bf2899d 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -1756,7 +1756,7 @@ intel_panel_init_backlight_funcs(struct intel_panel
> *panel)
>  	    intel_dsi_dcs_init_backlight_funcs(connector) == 0)
>  		return;
>  
> -	if (IS_BROXTON(dev_priv)) {
> +	if (IS_GEN9_LP(dev_priv)) {
>  		panel->backlight.setup = bxt_setup_backlight;
>  		panel->backlight.enable = bxt_enable_backlight;
>  		panel->backlight.disable = bxt_disable_backlight;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index cc9e0c0..dcf5cd4 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5228,7 +5228,7 @@ int sanitize_rc6_option(struct drm_i915_private
> *dev_priv, int enable_rc6)
>  	if (!enable_rc6)
>  		return 0;
>  
> -	if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
> +	if (IS_GEN9_LP(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
>  		DRM_INFO("RC6 disabled by BIOS\n");
>  		return 0;
>  	}
> @@ -5262,7 +5262,7 @@ static void gen6_init_rps_frequencies(struct
> drm_i915_private *dev_priv)
>  	/* All of these values are in units of 50MHz */
>  
>  	/* static values from HW: RP0 > RP1 > RPn (min_freq) */
> -	if (IS_BROXTON(dev_priv)) {
> +	if (IS_GEN9_LP(dev_priv)) {
>  		u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
>  		dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
>  		dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
> @@ -7642,7 +7642,7 @@ void intel_init_clock_gating_hooks(struct
> drm_i915_private *dev_priv)
>  		dev_priv->display.init_clock_gating =
> skylake_init_clock_gating;
>  	else if (IS_KABYLAKE(dev_priv))
>  		dev_priv->display.init_clock_gating =
> kabylake_init_clock_gating;
> -	else if (IS_BROXTON(dev_priv))
> +	else if (IS_GEN9_LP(dev_priv))
>  		dev_priv->display.init_clock_gating = bxt_init_clock_gating;
>  	else if (IS_BROADWELL(dev_priv))
>  		dev_priv->display.init_clock_gating =
> broadwell_init_clock_gating;
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 0599408..697574f 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -530,7 +530,7 @@ static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
>  	u32 mask;
>  
>  	mask = DC_STATE_EN_UPTO_DC5;
> -	if (IS_BROXTON(dev_priv))
> +	if (IS_GEN9_LP(dev_priv))
>  		mask |= DC_STATE_EN_DC9;
>  	else
>  		mask |= DC_STATE_EN_UPTO_DC6;
> @@ -911,7 +911,7 @@ static void gen9_dc_off_power_well_enable(struct
> drm_i915_private *dev_priv,
>  
>  	gen9_assert_dbuf_enabled(dev_priv);
>  
> -	if (IS_BROXTON(dev_priv))
> +	if (IS_GEN9_LP(dev_priv))
>  		bxt_verify_ddi_phy_power_wells(dev_priv);
>  }
>  
> @@ -2170,7 +2170,7 @@ static uint32_t get_allowed_dc_mask(const struct
> drm_i915_private *dev_priv,
>  	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
>  		max_dc = 2;
>  		mask = 0;
> -	} else if (IS_BROXTON(dev_priv)) {
> +	} else if (IS_GEN9_LP(dev_priv)) {
>  		max_dc = 1;
>  		/*
>  		 * DC9 has a separate HW flow from the rest of the DC states,
kernel test robot Nov. 11, 2016, 3:43 p.m. UTC | #2 
Hi Ander,

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on next-20161111]
[cannot apply to v4.9-rc4]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Ander-Conselvan-de-Oliveira/drm-i915-glk-Reuse-broxton-code-for-geminilake/20161111-215001
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-x006-201645 (attached as .config)
compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
reproduce:
        # save the attached .config to linux build tree
        make ARCH=i386 

All error/warnings (new ones prefixed by >>):

   In file included from include/uapi/linux/stddef.h:1:0,
                    from include/linux/stddef.h:4,
                    from include/uapi/linux/posix_types.h:4,
                    from include/uapi/linux/types.h:13,
                    from include/linux/types.h:5,
                    from include/linux/list.h:4,
                    from include/linux/agp_backend.h:33,
                    from include/drm/drmP.h:35,
                    from drivers/gpu/drm/i915/intel_mocs.h:52,
                    from drivers/gpu/drm/i915/intel_mocs.c:23:
   drivers/gpu/drm/i915/intel_mocs.c: In function 'get_mocs_settings':
>> drivers/gpu/drm/i915/intel_mocs.c:185:13: error: implicit declaration of function 'IS_GEN9_LP' [-Werror=implicit-function-declaration]
     } else if (IS_GEN9_LP(dev_priv)) {
                ^
   include/linux/compiler.h:149:30: note: in definition of macro '__trace_if'
     if (__builtin_constant_p(!!(cond)) ? !!(cond) :   \
                                 ^~~~
>> drivers/gpu/drm/i915/intel_mocs.c:185:9: note: in expansion of macro 'if'
     } else if (IS_GEN9_LP(dev_priv)) {
            ^~
   Cyclomatic Complexity 1 drivers/gpu/drm/i915/i915_reg.h:i915_mmio_reg_offset
   Cyclomatic Complexity 1 drivers/gpu/drm/i915/intel_ringbuffer.h:intel_ring_emit
   Cyclomatic Complexity 1 drivers/gpu/drm/i915/intel_ringbuffer.h:intel_ring_emit_reg
   Cyclomatic Complexity 1 drivers/gpu/drm/i915/intel_ringbuffer.h:intel_ring_advance
   Cyclomatic Complexity 1 drivers/gpu/drm/i915/i915_drv.h:to_i915
   Cyclomatic Complexity 1 drivers/gpu/drm/i915/intel_mocs.c:l3cc_combine
   Cyclomatic Complexity 9 drivers/gpu/drm/i915/intel_mocs.c:mocs_register
   Cyclomatic Complexity 23 drivers/gpu/drm/i915/intel_mocs.c:get_mocs_settings
   Cyclomatic Complexity 9 drivers/gpu/drm/i915/intel_mocs.c:emit_mocs_control_table
   Cyclomatic Complexity 11 drivers/gpu/drm/i915/intel_mocs.c:emit_mocs_l3cc_table
   Cyclomatic Complexity 8 drivers/gpu/drm/i915/intel_mocs.c:intel_mocs_init_engine
   Cyclomatic Complexity 6 drivers/gpu/drm/i915/intel_mocs.c:intel_mocs_init_l3cc_table
   Cyclomatic Complexity 6 drivers/gpu/drm/i915/intel_mocs.c:intel_rcs_context_init_mocs
   cc1: all warnings being treated as errors
--
   In file included from include/uapi/linux/stddef.h:1:0,
                    from include/linux/stddef.h:4,
                    from include/uapi/linux/posix_types.h:4,
                    from include/uapi/linux/types.h:13,
                    from include/linux/types.h:5,
                    from include/drm/drm_dp_helper.h:26,
                    from drivers/gpu/drm/i915/intel_bios.c:28:
   drivers/gpu/drm/i915/intel_bios.c: In function 'intel_bios_is_port_hpd_inverted':
>> drivers/gpu/drm/i915/intel_bios.c:1768:20: error: implicit declaration of function 'IS_GEN9_LP' [-Werror=implicit-function-declaration]
     if (WARN_ON_ONCE(!IS_GEN9_LP(dev_priv)))
                       ^
   include/linux/compiler.h:149:30: note: in definition of macro '__trace_if'
     if (__builtin_constant_p(!!(cond)) ? !!(cond) :   \
                                 ^~~~
>> drivers/gpu/drm/i915/intel_bios.c:1768:2: note: in expansion of macro 'if'
     if (WARN_ON_ONCE(!IS_GEN9_LP(dev_priv)))
     ^~
>> drivers/gpu/drm/i915/i915_drv.h:95:25: note: in expansion of macro 'WARN_ONCE'
    #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
                            ^~~~~~~~~
>> drivers/gpu/drm/i915/intel_bios.c:1768:6: note: in expansion of macro 'WARN_ON_ONCE'
     if (WARN_ON_ONCE(!IS_GEN9_LP(dev_priv)))
         ^~~~~~~~~~~~
   Cyclomatic Complexity 1 arch/x86/include/asm/bitops.h:fls
   Cyclomatic Complexity 1 include/linux/log2.h:__ilog2_u32
   Cyclomatic Complexity 1 include/asm-generic/getorder.h:__get_order
   Cyclomatic Complexity 56 include/linux/slab.h:kmalloc_index
   Cyclomatic Complexity 67 include/linux/slab.h:kmalloc_large
   Cyclomatic Complexity 9 include/linux/slab.h:kmalloc
   Cyclomatic Complexity 17 include/linux/slab.h:kmalloc_array
   Cyclomatic Complexity 1 include/linux/slab.h:kcalloc
   Cyclomatic Complexity 1 include/linux/slab.h:kzalloc
   Cyclomatic Complexity 1 drivers/gpu/drm/i915/intel_bios.c:get_lvds_dvo_timing
   Cyclomatic Complexity 6 drivers/gpu/drm/i915/intel_bios.c:intel_bios_ssc_frequency
   Cyclomatic Complexity 1 drivers/gpu/drm/i915/intel_bios.c:child_device_ptr
   Cyclomatic Complexity 1 drivers/gpu/drm/i915/intel_bios.c:get_bdb_header
   Cyclomatic Complexity 9 drivers/gpu/drm/i915/intel_bios.c:_get_blocksize
   Cyclomatic Complexity 6 drivers/gpu/drm/i915/intel_bios.c:find_section
   Cyclomatic Complexity 1 drivers/gpu/drm/i915/intel_bios.c:get_blocksize
   Cyclomatic Complexity 11 drivers/gpu/drm/i915/intel_bios.c:get_lvds_fp_timing
   Cyclomatic Complexity 4 drivers/gpu/drm/i915/intel_bios.c:init_vbt_defaults
   Cyclomatic Complexity 11 drivers/gpu/drm/i915/intel_bios.c:parse_general_features
   Cyclomatic Complexity 11 drivers/gpu/drm/i915/intel_bios.c:parse_lfp_backlight
   Cyclomatic Complexity 25 drivers/gpu/drm/i915/intel_bios.c:parse_sdvo_device_mapping
   Cyclomatic Complexity 7 drivers/gpu/drm/i915/intel_bios.c:parse_driver_features
   Cyclomatic Complexity 25 drivers/gpu/drm/i915/intel_bios.c:parse_edp
   Cyclomatic Complexity 7 drivers/gpu/drm/i915/intel_bios.c:parse_psr
   Cyclomatic Complexity 14 drivers/gpu/drm/i915/intel_bios.c:find_panel_sequence_block
   Cyclomatic Complexity 11 drivers/gpu/drm/i915/intel_bios.c:goto_next_sequence_v3
   Cyclomatic Complexity 11 drivers/gpu/drm/i915/intel_bios.c:goto_next_sequence
   Cyclomatic Complexity 8 drivers/gpu/drm/i915/intel_bios.c:sanitize_ddc_pin
   Cyclomatic Complexity 8 drivers/gpu/drm/i915/intel_bios.c:sanitize_aux_ch
   Cyclomatic Complexity 3 drivers/gpu/drm/i915/intel_bios.c:translate_iboost
   Cyclomatic Complexity 89 drivers/gpu/drm/i915/intel_bios.c:parse_ddi_port
   Cyclomatic Complexity 8 drivers/gpu/drm/i915/intel_bios.c:parse_ddi_ports
   Cyclomatic Complexity 6 drivers/gpu/drm/i915/intel_bios.c:parse_general_definitions
   Cyclomatic Complexity 9 drivers/gpu/drm/i915/intel_bios.c:fill_detail_timing_data
   Cyclomatic Complexity 28 drivers/gpu/drm/i915/intel_bios.c:parse_lfp_panel_data
   Cyclomatic Complexity 11 drivers/gpu/drm/i915/intel_bios.c:parse_sdvo_panel_data
   Cyclomatic Complexity 35 drivers/gpu/drm/i915/intel_bios.c:parse_device_mapping
   Cyclomatic Complexity 21 drivers/gpu/drm/i915/intel_bios.c:parse_mipi_sequence
   Cyclomatic Complexity 11 drivers/gpu/drm/i915/intel_bios.c:intel_bios_is_valid_vbt
   Cyclomatic Complexity 4 drivers/gpu/drm/i915/intel_bios.c:find_vbt
   Cyclomatic Complexity 9 drivers/gpu/drm/i915/intel_bios.c:intel_bios_is_tv_present
   Cyclomatic Complexity 17 drivers/gpu/drm/i915/intel_bios.c:intel_bios_is_lvds_present
   Cyclomatic Complexity 21 drivers/gpu/drm/i915/intel_bios.c:intel_bios_is_port_present
   Cyclomatic Complexity 12 drivers/gpu/drm/i915/intel_bios.c:intel_bios_is_port_edp
   Cyclomatic Complexity 17 drivers/gpu/drm/i915/intel_bios.c:intel_bios_is_port_dp_dual_mode
   Cyclomatic Complexity 8 drivers/gpu/drm/i915/intel_bios.c:intel_bios_is_dsi_present
   Cyclomatic Complexity 16 drivers/gpu/drm/i915/intel_bios.c:parse_mipi_config
   Cyclomatic Complexity 11 drivers/gpu/drm/i915/intel_bios.c:intel_bios_init
   Cyclomatic Complexity 26 drivers/gpu/drm/i915/intel_bios.c:intel_bios_is_port_hpd_inverted
   Cyclomatic Complexity 18 drivers/gpu/drm/i915/intel_bios.c:intel_bios_is_lspcon_present
   cc1: all warnings being treated as errors
--
   In file included from include/uapi/linux/stddef.h:1:0,
                    from include/linux/stddef.h:4,
                    from include/uapi/linux/posix_types.h:4,
                    from include/uapi/linux/types.h:13,
                    from include/linux/types.h:5,
                    from include/linux/list.h:4,
                    from include/linux/dmi.h:4,
                    from drivers/gpu/drm/i915/intel_display.c:27:
   drivers/gpu/drm/i915/intel_display.c: In function 'intel_PLL_is_valid':
>> drivers/gpu/drm/i915/intel_display.c:617:35: error: implicit declaration of function 'IS_GEN9_LP' [-Werror=implicit-function-declaration]
         !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
                                      ^
   include/linux/compiler.h:149:30: note: in definition of macro '__trace_if'
     if (__builtin_constant_p(!!(cond)) ? !!(cond) :   \
                                 ^~~~
   drivers/gpu/drm/i915/intel_display.c:616:2: note: in expansion of macro 'if'
     if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
     ^~
   Cyclomatic Complexity 5 include/linux/compiler.h:__read_once_size
   Cyclomatic Complexity 5 include/linux/compiler.h:__write_once_size
   Cyclomatic Complexity 1 arch/x86/include/asm/bitops.h:constant_test_bit
   Cyclomatic Complexity 1 arch/x86/include/asm/bitops.h:ffs
   Cyclomatic Complexity 1 arch/x86/include/asm/bitops.h:fls
   Cyclomatic Complexity 1 include/linux/bitops.h:fls_long
   Cyclomatic Complexity 1 include/linux/log2.h:__ilog2_u32
   Cyclomatic Complexity 3 include/linux/log2.h:is_power_of_2
   Cyclomatic Complexity 1 include/linux/log2.h:__roundup_pow_of_two
   Cyclomatic Complexity 1 include/linux/list.h:INIT_LIST_HEAD
   Cyclomatic Complexity 1 include/linux/list.h:list_empty
   Cyclomatic Complexity 1 include/linux/err.h:ERR_PTR
   Cyclomatic Complexity 1 include/linux/err.h:PTR_ERR
   Cyclomatic Complexity 2 include/linux/err.h:IS_ERR
   Cyclomatic Complexity 1 include/linux/err.h:ERR_CAST
   Cyclomatic Complexity 2 include/linux/err.h:PTR_ERR_OR_ZERO
   Cyclomatic Complexity 1 arch/x86/include/asm/atomic.h:atomic_read
   Cyclomatic Complexity 1 arch/x86/include/asm/atomic.h:atomic_set
   Cyclomatic Complexity 1 arch/x86/include/asm/atomic.h:atomic_sub_and_test
   Cyclomatic Complexity 1 arch/x86/include/asm/atomic.h:atomic_inc
   Cyclomatic Complexity 1 arch/x86/include/asm/atomic.h:atomic_dec
   Cyclomatic Complexity 1 arch/x86/include/asm/atomic.h:atomic_add_return
   Cyclomatic Complexity 1 arch/x86/include/asm/atomic.h:atomic_cmpxchg
   Cyclomatic Complexity 1 arch/x86/include/asm/atomic.h:atomic_or
   Cyclomatic Complexity 5 arch/x86/include/asm/atomic.h:__atomic_add_unless
   Cyclomatic Complexity 1 include/linux/atomic.h:atomic_add_unless
   Cyclomatic Complexity 1 include/asm-generic/getorder.h:__get_order
   Cyclomatic Complexity 1 include/linux/jump_label.h:static_key_count
   Cyclomatic Complexity 2 include/linux/jump_label.h:static_key_false
   Cyclomatic Complexity 1 arch/x86/include/asm/paravirt.h:arch_local_save_flags
   Cyclomatic Complexity 1 arch/x86/include/asm/paravirt.h:arch_local_irq_restore
   Cyclomatic Complexity 1 arch/x86/include/asm/paravirt.h:arch_local_irq_disable
   Cyclomatic Complexity 1 arch/x86/include/asm/paravirt.h:arch_local_irq_enable
   Cyclomatic Complexity 1 arch/x86/include/asm/paravirt.h:arch_local_irq_save
   Cyclomatic Complexity 3 arch/x86/include/asm/div64.h:div_u64_rem
   Cyclomatic Complexity 1 include/linux/math64.h:div_u64
   Cyclomatic Complexity 1 arch/x86/include/asm/irqflags.h:arch_irqs_disabled_flags
   Cyclomatic Complexity 1 arch/x86/include/asm/processor.h:rep_nop
   Cyclomatic Complexity 1 arch/x86/include/asm/processor.h:cpu_relax
   Cyclomatic Complexity 1 include/linux/mutex.h:mutex_is_locked
   Cyclomatic Complexity 1 arch/x86/include/asm/preempt.h:preempt_count
   Cyclomatic Complexity 8 arch/x86/include/asm/preempt.h:__preempt_count_add
   Cyclomatic Complexity 1 arch/x86/include/asm/preempt.h:__preempt_count_dec_and_test
   Cyclomatic Complexity 1 arch/x86/include/asm/preempt.h:should_resched
   Cyclomatic Complexity 1 include/linux/spinlock.h:spinlock_check
   Cyclomatic Complexity 1 include/linux/spinlock.h:spin_lock
   Cyclomatic Complexity 1 include/linux/spinlock.h:spin_lock_irq
   Cyclomatic Complexity 2 include/linux/spinlock.h:spin_unlock
   Cyclomatic Complexity 2 include/linux/spinlock.h:spin_unlock_irq
   Cyclomatic Complexity 3 include/linux/spinlock.h:spin_unlock_irqrestore
   Cyclomatic Complexity 3 include/linux/seqlock.h:__read_seqcount_begin
   Cyclomatic Complexity 1 include/linux/seqlock.h:raw_read_seqcount_begin
   Cyclomatic Complexity 1 include/linux/seqlock.h:read_seqcount_begin
   Cyclomatic Complexity 2 include/linux/seqlock.h:__read_seqcount_retry
   Cyclomatic Complexity 1 include/linux/seqlock.h:read_seqcount_retry
   Cyclomatic Complexity 1 include/linux/wait.h:waitqueue_active
   Cyclomatic Complexity 1 include/linux/jiffies.h:_msecs_to_jiffies
   Cyclomatic Complexity 5 include/linux/jiffies.h:msecs_to_jiffies
   Cyclomatic Complexity 1 include/linux/jiffies.h:_usecs_to_jiffies
   Cyclomatic Complexity 4 include/linux/jiffies.h:usecs_to_jiffies
   Cyclomatic Complexity 1 include/linux/rcupdate.h:rcu_read_lock
   Cyclomatic Complexity 1 include/linux/rcupdate.h:rcu_read_unlock
   Cyclomatic Complexity 1 include/linux/rcupdate.h:rcu_read_lock_sched_notrace
   Cyclomatic Complexity 2 include/linux/rcupdate.h:rcu_read_unlock_sched_notrace
   Cyclomatic Complexity 9 include/linux/idr.h:idr_find
   Cyclomatic Complexity 13 include/linux/kref.h:kref_get
   Cyclomatic Complexity 5 include/linux/kref.h:kref_sub
   Cyclomatic Complexity 1 include/linux/kref.h:kref_put
   Cyclomatic Complexity 1 include/linux/kref.h:kref_get_unless_zero
   Cyclomatic Complexity 1 include/linux/workqueue.h:queue_work
   Cyclomatic Complexity 1 include/linux/workqueue.h:flush_scheduled_work
   Cyclomatic Complexity 1 include/linux/sched.h:local_clock
   Cyclomatic Complexity 56 include/linux/slab.h:kmalloc_index
   Cyclomatic Complexity 67 include/linux/slab.h:kmalloc_large
   Cyclomatic Complexity 9 include/linux/slab.h:kmalloc
   Cyclomatic Complexity 1 include/linux/slab.h:kzalloc
   Cyclomatic Complexity 1 arch/x86/include/asm/io.h:outb
   Cyclomatic Complexity 1 arch/x86/include/asm/io.h:inb
   Cyclomatic Complexity 1 include/linux/vgaarb.h:vga_get_uninterruptible
   Cyclomatic Complexity 1 include/linux/pci.h:pci_read_config_word
   Cyclomatic Complexity 1 include/linux/pci.h:pci_write_config_word
   Cyclomatic Complexity 3 include/linux/dma-fence.h:dma_fence_put
   Cyclomatic Complexity 3 include/linux/dma-fence.h:dma_fence_get
   Cyclomatic Complexity 5 include/linux/dma-fence.h:dma_fence_is_signaled
   Cyclomatic Complexity 1 include/linux/ww_mutex.h:ww_mutex_is_locked
   Cyclomatic Complexity 1 include/drm/drm_modeset_lock.h:drm_modeset_is_locked
   Cyclomatic Complexity 1 include/drm/drm_rect.h:drm_rect_width
   Cyclomatic Complexity 1 include/drm/drm_rect.h:drm_rect_height
   Cyclomatic Complexity 1 include/drm/drm_framebuffer.h:drm_framebuffer_reference
   Cyclomatic Complexity 1 include/drm/drm_framebuffer.h:drm_framebuffer_unreference
   Cyclomatic Complexity 1 include/drm/drm_connector.h:drm_connector_index
   Cyclomatic Complexity 1 include/drm/drm_connector.h:drm_connector_reference
--
   In file included from include/uapi/linux/stddef.h:1:0,
                    from include/linux/stddef.h:4,
                    from include/uapi/linux/posix_types.h:4,
                    from include/uapi/linux/types.h:13,
                    from include/linux/types.h:5,
                    from include/linux/async.h:15,
                    from drivers/gpu/drm/i915/intel_drv.h:28,
                    from drivers/gpu/drm/i915/intel_dpll_mgr.c:24:
   drivers/gpu/drm/i915/intel_dpll_mgr.c: In function 'intel_shared_dpll_init':
>> drivers/gpu/drm/i915/intel_dpll_mgr.c:1864:11: error: implicit declaration of function 'IS_GEN9_LP' [-Werror=implicit-function-declaration]
     else if (IS_GEN9_LP(dev_priv))
              ^
   include/linux/compiler.h:149:30: note: in definition of macro '__trace_if'
     if (__builtin_constant_p(!!(cond)) ? !!(cond) :   \
                                 ^~~~
>> drivers/gpu/drm/i915/intel_dpll_mgr.c:1864:7: note: in expansion of macro 'if'
     else if (IS_GEN9_LP(dev_priv))
          ^~
   Cyclomatic Complexity 1 arch/x86/include/asm/paravirt.h:arch_local_save_flags
   Cyclomatic Complexity 3 arch/x86/include/asm/div64.h:div_u64_rem
   Cyclomatic Complexity 1 include/linux/math64.h:div_u64
   Cyclomatic Complexity 1 arch/x86/include/asm/irqflags.h:arch_irqs_disabled_flags
   Cyclomatic Complexity 1 arch/x86/include/asm/processor.h:rep_nop
   Cyclomatic Complexity 1 arch/x86/include/asm/processor.h:cpu_relax
   Cyclomatic Complexity 1 arch/x86/include/asm/preempt.h:preempt_count
   Cyclomatic Complexity 1 include/linux/jiffies.h:_usecs_to_jiffies
   Cyclomatic Complexity 4 include/linux/jiffies.h:usecs_to_jiffies
   Cyclomatic Complexity 1 include/drm/drm_crtc.h:drm_crtc_index
   Cyclomatic Complexity 4 include/drm/drmP.h:drm_can_sleep
   Cyclomatic Complexity 2 drivers/gpu/drm/i915/i915_drv.h:onoff
   Cyclomatic Complexity 1 drivers/gpu/drm/i915/i915_drv.h:to_i915
   Cyclomatic Complexity 1 drivers/gpu/drm/i915/intel_drv.h:enc_to_dig_port
   Cyclomatic Complexity 1 drivers/gpu/drm/i915/intel_drv.h:enc_to_mst
   Cyclomatic Complexity 3 drivers/gpu/drm/i915/intel_dpll_mgr.c:ibx_pch_dpll_mode_set
   Cyclomatic Complexity 1 drivers/gpu/drm/i915/intel_dpll_mgr.c:hsw_ddi_wrpll_disable
   Cyclomatic Complexity 1 drivers/gpu/drm/i915/intel_dpll_mgr.c:hsw_ddi_spll_disable
   Cyclomatic Complexity 6 drivers/gpu/drm/i915/intel_dpll_mgr.c:hsw_wrpll_get_budget_for_freq
   Cyclomatic Complexity 1 drivers/gpu/drm/i915/intel_dpll_mgr.c:hsw_ddi_lcpll_enable
   Cyclomatic Complexity 1 drivers/gpu/drm/i915/intel_dpll_mgr.c:hsw_ddi_lcpll_disable
   Cyclomatic Complexity 1 drivers/gpu/drm/i915/intel_dpll_mgr.c:hsw_ddi_lcpll_get_hw_state
   Cyclomatic Complexity 1 drivers/gpu/drm/i915/intel_dpll_mgr.c:skl_ddi_pll_write_ctrl1
   Cyclomatic Complexity 1 drivers/gpu/drm/i915/intel_dpll_mgr.c:skl_ddi_dpll0_enable
   Cyclomatic Complexity 1 drivers/gpu/drm/i915/intel_dpll_mgr.c:skl_ddi_pll_disable
   Cyclomatic Complexity 1 drivers/gpu/drm/i915/intel_dpll_mgr.c:skl_ddi_dpll0_disable
   Cyclomatic Complexity 1 drivers/gpu/drm/i915/intel_dpll_mgr.c:bxt_ddi_pll_disable
   Cyclomatic Complexity 4 drivers/gpu/drm/i915/intel_dpll_mgr.c:bxt_ddi_dp_pll_dividers
   Cyclomatic Complexity 33 drivers/gpu/drm/i915/intel_dpll_mgr.c:hsw_wrpll_update_rnp
   Cyclomatic Complexity 6 drivers/gpu/drm/i915/intel_dpll_mgr.c:hsw_ddi_calculate_wrpll
   Cyclomatic Complexity 39 drivers/gpu/drm/i915/intel_dpll_mgr.c:skl_wrpll_get_multipliers
   Cyclomatic Complexity 18 drivers/gpu/drm/i915/intel_dpll_mgr.c:skl_wrpll_params_populate
   Cyclomatic Complexity 23 drivers/gpu/drm/i915/intel_dpll_mgr.c:bxt_ddi_set_dpll_hw_state
   Cyclomatic Complexity 15 drivers/gpu/drm/i915/intel_dpll_mgr.c:ibx_assert_pch_refclk_enabled
   Cyclomatic Complexity 7 drivers/gpu/drm/i915/intel_dpll_mgr.c:intel_ddi_pll_init
   Cyclomatic Complexity 9 drivers/gpu/drm/i915/intel_dpll_mgr.c:intel_find_shared_dpll
   Cyclomatic Complexity 3 drivers/gpu/drm/i915/intel_dpll_mgr.c:hsw_ddi_hdmi_get_dpll
   Cyclomatic Complexity 5 drivers/gpu/drm/i915/intel_dpll_mgr.c:ibx_pch_dpll_get_hw_state
   Cyclomatic Complexity 2 drivers/gpu/drm/i915/intel_dpll_mgr.c:hsw_ddi_spll_get_hw_state
   Cyclomatic Complexity 2 drivers/gpu/drm/i915/intel_dpll_mgr.c:hsw_ddi_wrpll_get_hw_state
   Cyclomatic Complexity 6 drivers/gpu/drm/i915/intel_dpll_mgr.c:skl_ddi_pll_get_hw_state
   Cyclomatic Complexity 6 drivers/gpu/drm/i915/intel_dpll_mgr.c:skl_ddi_dpll0_get_hw_state
   Cyclomatic Complexity 6 drivers/gpu/drm/i915/intel_dpll_mgr.c:ibx_pch_dpll_disable
   Cyclomatic Complexity 5 drivers/gpu/drm/i915/intel_dpll_mgr.c:ibx_pch_dpll_enable
   Cyclomatic Complexity 1 drivers/gpu/drm/i915/intel_dpll_mgr.c:hsw_ddi_spll_enable
   Cyclomatic Complexity 1 drivers/gpu/drm/i915/intel_dpll_mgr.c:hsw_ddi_wrpll_enable
   Cyclomatic Complexity 1 drivers/gpu/drm/i915/intel_dpll_mgr.c:skl_wrpll_context_init
   Cyclomatic Complexity 5 drivers/gpu/drm/i915/intel_dpll_mgr.c:bxt_ddi_hdmi_pll_dividers
   Cyclomatic Complexity 1 drivers/gpu/drm/i915/intel_dpll_mgr.c:bxt_ddi_hdmi_set_dpll_hw_state
   Cyclomatic Complexity 5 drivers/gpu/drm/i915/intel_dpll_mgr.c:bxt_ddi_pll_get_hw_state
   Cyclomatic Complexity 11 drivers/gpu/drm/i915/intel_dpll_mgr.c:bxt_ddi_pll_enable
   Cyclomatic Complexity 20 drivers/gpu/drm/i915/intel_dpll_mgr.c:skl_wrpll_try_divider
   Cyclomatic Complexity 16 drivers/gpu/drm/i915/intel_dpll_mgr.c:skl_ddi_calculate_wrpll
   Cyclomatic Complexity 2 drivers/gpu/drm/i915/intel_dpll_mgr.c:skl_ddi_hdmi_pll_dividers
   Cyclomatic Complexity 2 drivers/gpu/drm/i915/intel_dpll_mgr.c:skl_ddi_pll_enable
   Cyclomatic Complexity 1 drivers/gpu/drm/i915/intel_dpll_mgr.c:intel_get_shared_dpll_by_id
   Cyclomatic Complexity 7 drivers/gpu/drm/i915/intel_dpll_mgr.c:intel_get_shared_dpll_id
   Cyclomatic Complexity 1 drivers/gpu/drm/i915/intel_dpll_mgr.c:intel_shared_dpll_config_get
   Cyclomatic Complexity 3 drivers/gpu/drm/i915/intel_dpll_mgr.c:intel_reference_shared_dpll
   Cyclomatic Complexity 5 drivers/gpu/drm/i915/intel_dpll_mgr.c:ibx_get_dpll
   Cyclomatic Complexity 1 drivers/gpu/drm/i915/intel_dpll_mgr.c:intel_shared_dpll_config_put
   Cyclomatic Complexity 12 drivers/gpu/drm/i915/intel_dpll_mgr.c:assert_shared_dpll
   Cyclomatic Complexity 13 drivers/gpu/drm/i915/intel_dpll_mgr.c:intel_prepare_shared_dpll
   Cyclomatic Complexity 22 drivers/gpu/drm/i915/intel_dpll_mgr.c:intel_enable_shared_dpll
   Cyclomatic Complexity 13 drivers/gpu/drm/i915/intel_dpll_mgr.c:intel_disable_shared_dpll
   Cyclomatic Complexity 3 drivers/gpu/drm/i915/intel_dpll_mgr.c:intel_shared_dpll_commit
   Cyclomatic Complexity 6 drivers/gpu/drm/i915/intel_dpll_mgr.c:hsw_ddi_dp_get_dpll
   Cyclomatic Complexity 22 drivers/gpu/drm/i915/intel_dpll_mgr.c:hsw_get_dpll
   Cyclomatic Complexity 7 drivers/gpu/drm/i915/intel_dpll_mgr.c:skl_ddi_dp_set_dpll_hw_state
   Cyclomatic Complexity 11 drivers/gpu/drm/i915/intel_dpll_mgr.c:skl_find_link_pll
   Cyclomatic Complexity 22 drivers/gpu/drm/i915/intel_dpll_mgr.c:skl_get_dpll
   Cyclomatic Complexity 1 drivers/gpu/drm/i915/intel_dpll_mgr.c:bxt_ddi_dp_set_dpll_hw_state
   Cyclomatic Complexity 9 drivers/gpu/drm/i915/intel_dpll_mgr.c:bxt_get_dpll
   Cyclomatic Complexity 17 drivers/gpu/drm/i915/intel_dpll_mgr.c:intel_shared_dpll_init
   Cyclomatic Complexity 5 drivers/gpu/drm/i915/intel_dpll_mgr.c:intel_get_shared_dpll
   cc1: all warnings being treated as errors
..

vim +/IS_GEN9_LP +185 drivers/gpu/drm/i915/intel_mocs.c

    17	 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
    18	 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
    19	 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
    20	 * SOFTWARE.
    21	 */
    22	
  > 23	#include "intel_mocs.h"
    24	#include "intel_lrc.h"
    25	#include "intel_ringbuffer.h"
    26	
    27	/* structures required */
    28	struct drm_i915_mocs_entry {
    29		u32 control_value;
    30		u16 l3cc_value;
    31	};
    32	
    33	struct drm_i915_mocs_table {
    34		u32 size;
    35		const struct drm_i915_mocs_entry *table;
    36	};
    37	
    38	/* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */
    39	#define LE_CACHEABILITY(value)	((value) << 0)
    40	#define LE_TGT_CACHE(value)	((value) << 2)
    41	#define LE_LRUM(value)		((value) << 4)
    42	#define LE_AOM(value)		((value) << 6)
    43	#define LE_RSC(value)		((value) << 7)
    44	#define LE_SCC(value)		((value) << 8)
    45	#define LE_PFM(value)		((value) << 11)
    46	#define LE_SCF(value)		((value) << 14)
    47	
    48	/* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */
    49	#define L3_ESC(value)		((value) << 0)
    50	#define L3_SCC(value)		((value) << 1)
    51	#define L3_CACHEABILITY(value)	((value) << 4)
    52	
    53	/* Helper defines */
    54	#define GEN9_NUM_MOCS_ENTRIES	62  /* 62 out of 64 - 63 & 64 are reserved. */
    55	
    56	/* (e)LLC caching options */
    57	#define LE_PAGETABLE		0
    58	#define LE_UC			1
    59	#define LE_WT			2
    60	#define LE_WB			3
    61	
    62	/* L3 caching options */
    63	#define L3_DIRECT		0
    64	#define L3_UC			1
    65	#define L3_RESERVED		2
    66	#define L3_WB			3
    67	
    68	/* Target cache */
    69	#define LE_TC_PAGETABLE		0
    70	#define LE_TC_LLC		1
    71	#define LE_TC_LLC_ELLC		2
    72	#define LE_TC_LLC_ELLC_ALT	3
    73	
    74	/*
    75	 * MOCS tables
    76	 *
    77	 * These are the MOCS tables that are programmed across all the rings.
    78	 * The control value is programmed to all the rings that support the
    79	 * MOCS registers. While the l3cc_values are only programmed to the
    80	 * LNCFCMOCS0 - LNCFCMOCS32 registers.
    81	 *
    82	 * These tables are intended to be kept reasonably consistent across
    83	 * platforms. However some of the fields are not applicable to all of
    84	 * them.
    85	 *
    86	 * Entries not part of the following tables are undefined as far as
    87	 * userspace is concerned and shouldn't be relied upon.  For the time
    88	 * being they will be implicitly initialized to the strictest caching
    89	 * configuration (uncached) to guarantee forwards compatibility with
    90	 * userspace programs written against more recent kernels providing
    91	 * additional MOCS entries.
    92	 *
    93	 * NOTE: These tables MUST start with being uncached and the length
    94	 *       MUST be less than 63 as the last two registers are reserved
    95	 *       by the hardware.  These tables are part of the kernel ABI and
    96	 *       may only be updated incrementally by adding entries at the
    97	 *       end.
    98	 */
    99	static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
   100		[I915_MOCS_UNCACHED] = {
   101		  /* 0x00000009 */
   102		  .control_value = LE_CACHEABILITY(LE_UC) |
   103				   LE_TGT_CACHE(LE_TC_LLC_ELLC) |
   104				   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
   105				   LE_PFM(0) | LE_SCF(0),
   106	
   107		  /* 0x0010 */
   108		  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
   109		},
   110		[I915_MOCS_PTE] = {
   111		  /* 0x00000038 */
   112		  .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
   113				   LE_TGT_CACHE(LE_TC_LLC_ELLC) |
   114				   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
   115				   LE_PFM(0) | LE_SCF(0),
   116		  /* 0x0030 */
   117		  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
   118		},
   119		[I915_MOCS_CACHED] = {
   120		  /* 0x0000003b */
   121		  .control_value = LE_CACHEABILITY(LE_WB) |
   122				   LE_TGT_CACHE(LE_TC_LLC_ELLC) |
   123				   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
   124				   LE_PFM(0) | LE_SCF(0),
   125		  /* 0x0030 */
   126		  .l3cc_value =   L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
   127		},
   128	};
   129	
   130	/* NOTE: the LE_TGT_CACHE is not used on Broxton */
   131	static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
   132		[I915_MOCS_UNCACHED] = {
   133		  /* 0x00000009 */
   134		  .control_value = LE_CACHEABILITY(LE_UC) |
   135				   LE_TGT_CACHE(LE_TC_LLC_ELLC) |
   136				   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
   137				   LE_PFM(0) | LE_SCF(0),
   138	
   139		  /* 0x0010 */
   140		  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
   141		},
   142		[I915_MOCS_PTE] = {
   143		  /* 0x00000038 */
   144		  .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
   145				   LE_TGT_CACHE(LE_TC_LLC_ELLC) |
   146				   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
   147				   LE_PFM(0) | LE_SCF(0),
   148	
   149		  /* 0x0030 */
   150		  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
   151		},
   152		[I915_MOCS_CACHED] = {
   153		  /* 0x00000039 */
   154		  .control_value = LE_CACHEABILITY(LE_UC) |
   155				   LE_TGT_CACHE(LE_TC_LLC_ELLC) |
   156				   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
   157				   LE_PFM(0) | LE_SCF(0),
   158	
   159		  /* 0x0030 */
   160		  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
   161		},
   162	};
   163	
   164	/**
   165	 * get_mocs_settings()
   166	 * @dev_priv:	i915 device.
   167	 * @table:      Output table that will be made to point at appropriate
   168	 *	      MOCS values for the device.
   169	 *
   170	 * This function will return the values of the MOCS table that needs to
   171	 * be programmed for the platform. It will return the values that need
   172	 * to be programmed and if they need to be programmed.
   173	 *
   174	 * Return: true if there are applicable MOCS settings for the device.
   175	 */
   176	static bool get_mocs_settings(struct drm_i915_private *dev_priv,
   177				      struct drm_i915_mocs_table *table)
   178	{
   179		bool result = false;
   180	
   181		if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
   182			table->size  = ARRAY_SIZE(skylake_mocs_table);
   183			table->table = skylake_mocs_table;
   184			result = true;
 > 185		} else if (IS_GEN9_LP(dev_priv)) {
   186			table->size  = ARRAY_SIZE(broxton_mocs_table);
   187			table->table = broxton_mocs_table;
   188			result = true;

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index b681d42..5d349d6 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1128,7 +1128,7 @@  static int i915_frequency_info(struct seq_file *m, void *unused)
 		int max_freq;
 
 		rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
-		if (IS_BROXTON(dev_priv)) {
+		if (IS_GEN9_LP(dev_priv)) {
 			rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
 			gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
 		} else {
@@ -1224,7 +1224,7 @@  static int i915_frequency_info(struct seq_file *m, void *unused)
 		seq_printf(m, "Down threshold: %d%%\n",
 			   dev_priv->rps.down_threshold);
 
-		max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 0 :
+		max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
 			    rp_state_cap >> 16) & 0xff;
 		max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
 			     GEN9_FREQ_SCALER : 1);
@@ -1237,7 +1237,7 @@  static int i915_frequency_info(struct seq_file *m, void *unused)
 		seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
 			   intel_gpu_freq(dev_priv, max_freq));
 
-		max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 16 :
+		max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
 			    rp_state_cap >> 0) & 0xff;
 		max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
 			     GEN9_FREQ_SCALER : 1);
@@ -5185,7 +5185,7 @@  static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
 	u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
 
 	/* BXT has a single slice and at most 3 subslices. */
-	if (IS_BROXTON(dev_priv)) {
+	if (IS_GEN9_LP(dev_priv)) {
 		s_max = 1;
 		ss_max = 3;
 	}
@@ -5219,7 +5219,7 @@  static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
 		for (ss = 0; ss < ss_max; ss++) {
 			unsigned int eu_cnt;
 
-			if (IS_BROXTON(dev_priv)) {
+			if (IS_GEN9_LP(dev_priv)) {
 				if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
 					/* skip disabled subslice */
 					continue;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index a5fafa3..36483a2 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -377,7 +377,7 @@  static void kunmap_page_dma(struct drm_i915_private *dev_priv, void *vaddr)
 	/* There are only few exceptions for gen >=6. chv and bxt.
 	 * And we are not sure about the latter so play safe for now.
 	 */
-	if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
+	if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
 		drm_clflush_virt_range(vaddr, PAGE_SIZE);
 
 	kunmap_atomic(vaddr);
@@ -2946,7 +2946,7 @@  static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
 	 * resort to an uncached mapping. The WC issue is easily caught by the
 	 * readback check when writing GTT PTE entries.
 	 */
-	if (IS_BROXTON(to_i915(ggtt->base.dev)))
+	if (IS_GEN9_LP(to_i915(ggtt->base.dev)))
 		ggtt->gsm = ioremap_nocache(phys_addr, size);
 	else
 		ggtt->gsm = ioremap_wc(phys_addr, size);
@@ -3078,7 +3078,7 @@  static int gen8_gmch_probe(struct i915_ggtt *ggtt)
 
 	ggtt->base.total = (size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
 
-	if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
+	if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
 		chv_setup_private_ppat(dev_priv);
 	else
 		bdw_setup_private_ppat(dev_priv);
@@ -3319,7 +3319,7 @@  void i915_gem_restore_gtt_mappings(struct drm_device *dev)
 	ggtt->base.closed = false;
 
 	if (INTEL_INFO(dev)->gen >= 8) {
-		if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
+		if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
 			chv_setup_private_ppat(dev_priv);
 		else
 			bdw_setup_private_ppat(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 6d7505b..081b3b7 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2435,7 +2435,7 @@  gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 				found = true;
 			}
 
-			if (IS_BROXTON(dev_priv)) {
+			if (IS_GEN9_LP(dev_priv)) {
 				tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
 				if (tmp_mask) {
 					bxt_hpd_irq_handler(dev_priv, tmp_mask,
@@ -2451,7 +2451,7 @@  gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 				}
 			}
 
-			if (IS_BROXTON(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
+			if (IS_GEN9_LP(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
 				gmbus_irq_handler(dev_priv);
 				found = true;
 			}
@@ -3379,7 +3379,7 @@  static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
 				  GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
 		de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
 				  GEN9_AUX_CHANNEL_D;
-		if (IS_BROXTON(dev_priv))
+		if (IS_GEN9_LP(dev_priv))
 			de_port_masked |= BXT_DE_PORT_GMBUS;
 	} else {
 		de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
@@ -3390,7 +3390,7 @@  static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
 					   GEN8_PIPE_FIFO_UNDERRUN;
 
 	de_port_enables = de_port_masked;
-	if (IS_BROXTON(dev_priv))
+	if (IS_GEN9_LP(dev_priv))
 		de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
 	else if (IS_BROADWELL(dev_priv))
 		de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
@@ -4215,7 +4215,7 @@  void intel_irq_init(struct drm_i915_private *dev_priv)
 		dev->driver->irq_uninstall = gen8_irq_uninstall;
 		dev->driver->enable_vblank = gen8_enable_vblank;
 		dev->driver->disable_vblank = gen8_disable_vblank;
-		if (IS_BROXTON(dev_priv))
+		if (IS_GEN9_LP(dev_priv))
 			dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
 		else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
 			dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3361d7f..1be2a7d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2920,7 +2920,7 @@  enum skl_disp_power_wells {
 #define INTERVAL_1_33_US(us)	(((us) * 3)   >> 2)
 #define INTERVAL_0_833_US(us)	(((us) * 6) / 5)
 #define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN9(dev_priv) ? \
-				(IS_BROXTON(dev_priv) ? \
+				(IS_GEN9_LP(dev_priv) ? \
 				INTERVAL_0_833_US(us) : \
 				INTERVAL_1_33_US(us)) : \
 				INTERVAL_1_28_US(us))
@@ -2929,7 +2929,7 @@  enum skl_disp_power_wells {
 #define INTERVAL_1_33_TO_US(interval)  (((interval) << 2) / 3)
 #define INTERVAL_0_833_TO_US(interval) (((interval) * 5)  / 6)
 #define GT_PM_INTERVAL_TO_US(dev_priv, interval) (IS_GEN9(dev_priv) ? \
-                           (IS_BROXTON(dev_priv) ? \
+                           (IS_GEN9_LP(dev_priv) ? \
                            INTERVAL_0_833_TO_US(interval) : \
                            INTERVAL_1_33_TO_US(interval)) : \
                            INTERVAL_1_28_TO_US(interval))
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 5ab646e..bd705f9 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -1765,7 +1765,7 @@  intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
 {
 	int i;
 
-	if (WARN_ON_ONCE(!IS_BROXTON(dev_priv)))
+	if (WARN_ON_ONCE(!IS_GEN9_LP(dev_priv)))
 		return false;
 
 	for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 0ad4e16..a129ffa 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -442,7 +442,7 @@  static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
 
 	hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 
-	if (IS_BROXTON(dev_priv))
+	if (IS_GEN9_LP(dev_priv))
 		return hdmi_level;
 
 	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
@@ -1091,7 +1091,7 @@  void intel_ddi_clock_get(struct intel_encoder *encoder,
 		hsw_ddi_clock_get(encoder, pipe_config);
 	else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
 		skl_ddi_clock_get(encoder, pipe_config);
-	else if (IS_BROXTON(dev_priv))
+	else if (IS_GEN9_LP(dev_priv))
 		bxt_ddi_clock_get(encoder, pipe_config);
 }
 
@@ -1153,7 +1153,7 @@  bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
 	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
 		return skl_ddi_pll_select(intel_crtc, crtc_state,
 					  intel_encoder);
-	else if (IS_BROXTON(dev_priv))
+	else if (IS_GEN9_LP(dev_priv))
 		return bxt_ddi_pll_select(intel_crtc, crtc_state,
 					  intel_encoder);
 	else
@@ -1643,7 +1643,7 @@  uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
 
 	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
 		skl_ddi_set_iboost(encoder, level);
-	else if (IS_BROXTON(dev_priv))
+	else if (IS_GEN9_LP(dev_priv))
 		bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
 
 	return DDI_BUF_TRANS_SELECT(level);
@@ -2246,7 +2246,7 @@  void intel_ddi_init(struct drm_device *dev, enum port port)
 	 * configuration so that we use the proper lane count for our
 	 * calculations.
 	 */
-	if (IS_BROXTON(dev_priv) && port == PORT_A) {
+	if (IS_GEN9_LP(dev_priv) && port == PORT_A) {
 		if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
 			DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
 			intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 01dbf1b..723ff9d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -614,12 +614,12 @@  static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
 		INTELPllInvalid("m1 out of range\n");
 
 	if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
-	    !IS_CHERRYVIEW(dev_priv) && !IS_BROXTON(dev_priv))
+	    !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
 		if (clock->m1 <= clock->m2)
 			INTELPllInvalid("m1 <= m2\n");
 
 	if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
-	    !IS_BROXTON(dev_priv)) {
+	    !IS_GEN9_LP(dev_priv)) {
 		if (clock->p < limit->p.min || limit->p.max < clock->p)
 			INTELPllInvalid("p out of range\n");
 		if (clock->m < limit->m.min || limit->m.max < clock->m)
@@ -10675,7 +10675,7 @@  static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
 
 	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
 		skylake_get_ddi_pll(dev_priv, port, pipe_config);
-	else if (IS_BROXTON(dev_priv))
+	else if (IS_GEN9_LP(dev_priv))
 		bxt_get_ddi_pll(dev_priv, port, pipe_config);
 	else
 		haswell_get_ddi_pll(dev_priv, port, pipe_config);
@@ -10721,7 +10721,7 @@  static bool haswell_get_pipe_config(struct intel_crtc *crtc,
 
 	active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
 
-	if (IS_BROXTON(dev_priv) &&
+	if (IS_GEN9_LP(dev_priv) &&
 	    bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
 		WARN_ON(active);
 		active = true;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 117a714..675e103 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -233,7 +233,7 @@  intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 	int size;
 
-	if (IS_BROXTON(dev_priv)) {
+	if (IS_GEN9_LP(dev_priv)) {
 		*source_rates = bxt_rates;
 		size = ARRAY_SIZE(bxt_rates);
 	} else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
@@ -688,7 +688,7 @@  static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
 
 	memset(regs, 0, sizeof(*regs));
 
-	if (IS_BROXTON(dev_priv))
+	if (IS_GEN9_LP(dev_priv))
 		pps_idx = bxt_power_sequencer_idx(intel_dp);
 	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		pps_idx = vlv_power_sequencer_pipe(intel_dp);
@@ -697,7 +697,7 @@  static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
 	regs->pp_stat = PP_STATUS(pps_idx);
 	regs->pp_on = PP_ON_DELAYS(pps_idx);
 	regs->pp_off = PP_OFF_DELAYS(pps_idx);
-	if (!IS_BROXTON(dev_priv))
+	if (!IS_GEN9_LP(dev_priv))
 		regs->pp_div = PP_DIVISOR(pps_idx);
 }
 
@@ -2984,7 +2984,7 @@  intel_dp_voltage_max(struct intel_dp *intel_dp)
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	enum port port = dp_to_dig_port(intel_dp)->port;
 
-	if (IS_BROXTON(dev_priv))
+	if (IS_GEN9_LP(dev_priv))
 		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
 	else if (INTEL_INFO(dev)->gen >= 9) {
 		if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
@@ -4300,7 +4300,7 @@  static bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
 		return ibx_digital_port_connected(dev_priv, port);
 	else if (HAS_PCH_SPLIT(dev_priv))
 		return cpt_digital_port_connected(dev_priv, port);
-	else if (IS_BROXTON(dev_priv))
+	else if (IS_GEN9_LP(dev_priv))
 		return bxt_digital_port_connected(dev_priv, port);
 	else if (IS_GM45(dev_priv))
 		return gm45_digital_port_connected(dev_priv, port);
@@ -4932,7 +4932,7 @@  intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
 
 	pp_on = I915_READ(regs.pp_on);
 	pp_off = I915_READ(regs.pp_off);
-	if (!IS_BROXTON(dev_priv)) {
+	if (!IS_GEN9_LP(dev_priv)) {
 		I915_WRITE(regs.pp_ctrl, pp_ctl);
 		pp_div = I915_READ(regs.pp_div);
 	}
@@ -4950,7 +4950,7 @@  intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
 	seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
 		   PANEL_POWER_DOWN_DELAY_SHIFT;
 
-	if (IS_BROXTON(dev_priv)) {
+	if (IS_GEN9_LP(dev_priv)) {
 		u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
 			BXT_POWER_CYCLE_DELAY_SHIFT;
 		if (tmp > 0)
@@ -5081,7 +5081,7 @@  intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 		 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
 	/* Compute the divisor for the pp clock, simply match the Bspec
 	 * formula. */
-	if (IS_BROXTON(dev_priv)) {
+	if (IS_GEN9_LP(dev_priv)) {
 		pp_div = I915_READ(regs.pp_ctrl);
 		pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
 		pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
@@ -5107,7 +5107,7 @@  intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 
 	I915_WRITE(regs.pp_on, pp_on);
 	I915_WRITE(regs.pp_off, pp_off);
-	if (IS_BROXTON(dev_priv))
+	if (IS_GEN9_LP(dev_priv))
 		I915_WRITE(regs.pp_ctrl, pp_div);
 	else
 		I915_WRITE(regs.pp_div, pp_div);
@@ -5115,7 +5115,7 @@  intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 	DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
 		      I915_READ(regs.pp_on),
 		      I915_READ(regs.pp_off),
-		      IS_BROXTON(dev_priv) ?
+		      IS_GEN9_LP(dev_priv) ?
 		      (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
 		      I915_READ(regs.pp_div));
 }
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 21853a1..8205c1c 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -1861,7 +1861,7 @@  void intel_shared_dpll_init(struct drm_device *dev)
 
 	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
 		dpll_mgr = &skl_pll_mgr;
-	else if (IS_BROXTON(dev_priv))
+	else if (IS_GEN9_LP(dev_priv))
 		dpll_mgr = &bxt_pll_mgr;
 	else if (HAS_DDI(dev_priv))
 		dpll_mgr = &hsw_pll_mgr;
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 4e0d025..4e19fbc 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -340,7 +340,7 @@  static bool intel_dsi_compute_config(struct intel_encoder *encoder,
 	/* DSI uses short packets for sync events, so clear mode flags for DSI */
 	adjusted_mode->flags = 0;
 
-	if (IS_BROXTON(dev_priv)) {
+	if (IS_GEN9_LP(dev_priv)) {
 		/* Dual link goes to DSI transcoder A. */
 		if (intel_dsi->ports == BIT(PORT_C))
 			pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
@@ -441,7 +441,7 @@  static void intel_dsi_device_ready(struct intel_encoder *encoder)
 
 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		vlv_dsi_device_ready(encoder);
-	else if (IS_BROXTON(dev_priv))
+	else if (IS_GEN9_LP(dev_priv))
 		bxt_dsi_device_ready(encoder);
 }
 
@@ -464,7 +464,7 @@  static void intel_dsi_port_enable(struct intel_encoder *encoder)
 	}
 
 	for_each_dsi_port(port, intel_dsi->ports) {
-		i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
+		i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
 			BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
 		u32 temp;
 
@@ -494,7 +494,7 @@  static void intel_dsi_port_disable(struct intel_encoder *encoder)
 	enum port port;
 
 	for_each_dsi_port(port, intel_dsi->ports) {
-		i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
+		i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
 			BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
 		u32 temp;
 
@@ -663,7 +663,7 @@  static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
 	DRM_DEBUG_KMS("\n");
 	for_each_dsi_port(port, intel_dsi->ports) {
 		/* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
-		i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
+		i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
 			BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
 		u32 val;
 
@@ -755,12 +755,12 @@  static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
 	 * configuration, otherwise accessing DSI registers will hang the
 	 * machine. See BSpec North Display Engine registers/MIPI[BXT].
 	 */
-	if (IS_BROXTON(dev_priv) && !intel_dsi_pll_is_enabled(dev_priv))
+	if (IS_GEN9_LP(dev_priv) && !intel_dsi_pll_is_enabled(dev_priv))
 		goto out_put_power;
 
 	/* XXX: this only works for one DSI output */
 	for_each_dsi_port(port, intel_dsi->ports) {
-		i915_reg_t ctrl_reg = IS_BROXTON(dev_priv) ?
+		i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ?
 			BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
 		bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE;
 
@@ -785,7 +785,7 @@  static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
 		if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))
 			continue;
 
-		if (IS_BROXTON(dev_priv)) {
+		if (IS_GEN9_LP(dev_priv)) {
 			u32 tmp = I915_READ(MIPI_CTRL(port));
 			tmp &= BXT_PIPE_SELECT_MASK;
 			tmp >>= BXT_PIPE_SELECT_SHIFT;
@@ -973,7 +973,7 @@  static void intel_dsi_get_config(struct intel_encoder *encoder,
 	u32 pclk;
 	DRM_DEBUG_KMS("\n");
 
-	if (IS_BROXTON(dev_priv))
+	if (IS_GEN9_LP(dev_priv))
 		bxt_dsi_get_pipe_config(encoder, pipe_config);
 
 	pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp,
@@ -1065,7 +1065,7 @@  static void set_dsi_timings(struct drm_encoder *encoder,
 	hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
 
 	for_each_dsi_port(port, intel_dsi->ports) {
-		if (IS_BROXTON(dev_priv)) {
+		if (IS_GEN9_LP(dev_priv)) {
 			/*
 			 * Program hdisplay and vdisplay on MIPI transcoder.
 			 * This is different from calculated hactive and
@@ -1152,7 +1152,7 @@  static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
 			tmp &= ~READ_REQUEST_PRIORITY_MASK;
 			I915_WRITE(MIPI_CTRL(port), tmp |
 					READ_REQUEST_PRIORITY_HIGH);
-		} else if (IS_BROXTON(dev_priv)) {
+		} else if (IS_GEN9_LP(dev_priv)) {
 			enum pipe pipe = intel_crtc->pipe;
 
 			tmp = I915_READ(MIPI_CTRL(port));
@@ -1241,7 +1241,7 @@  static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
 		I915_WRITE(MIPI_INIT_COUNT(port),
 				txclkesc(intel_dsi->escape_clk_div, 100));
 
-		if (IS_BROXTON(dev_priv) && (!intel_dsi->dual_link)) {
+		if (IS_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) {
 			/*
 			 * BXT spec says write MIPI_INIT_COUNT for
 			 * both the ports, even if only one is
@@ -1451,7 +1451,7 @@  void intel_dsi_init(struct drm_device *dev)
 
 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 		dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
-	} else if (IS_BROXTON(dev_priv)) {
+	} else if (IS_GEN9_LP(dev_priv)) {
 		dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
 	} else {
 		DRM_ERROR("Unsupported Mipi device to reg base");
@@ -1492,7 +1492,7 @@  void intel_dsi_init(struct drm_device *dev)
 	 * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI
 	 * port C. BXT isn't limited like this.
 	 */
-	if (IS_BROXTON(dev_priv))
+	if (IS_GEN9_LP(dev_priv))
 		intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
 	else if (port == PORT_A)
 		intel_encoder->crtc_mask = BIT(PIPE_A);
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 56eff60..cf8c1b0 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -351,7 +351,7 @@  static u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
 u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
 		       struct intel_crtc_state *config)
 {
-	if (IS_BROXTON(to_i915(encoder->base.dev)))
+	if (IS_GEN9_LP(to_i915(encoder->base.dev)))
 		return bxt_dsi_get_pclk(encoder, pipe_bpp, config);
 	else
 		return vlv_dsi_get_pclk(encoder, pipe_bpp, config);
@@ -504,7 +504,7 @@  static void bxt_enable_dsi_pll(struct intel_encoder *encoder,
 
 bool intel_dsi_pll_is_enabled(struct drm_i915_private *dev_priv)
 {
-	if (IS_BROXTON(dev_priv))
+	if (IS_GEN9_LP(dev_priv))
 		return bxt_dsi_pll_is_enabled(dev_priv);
 
 	MISSING_CASE(INTEL_DEVID(dev_priv));
@@ -519,7 +519,7 @@  int intel_compute_dsi_pll(struct intel_encoder *encoder,
 
 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		return vlv_compute_dsi_pll(encoder, config);
-	else if (IS_BROXTON(dev_priv))
+	else if (IS_GEN9_LP(dev_priv))
 		return bxt_compute_dsi_pll(encoder, config);
 
 	return -ENODEV;
@@ -532,7 +532,7 @@  void intel_enable_dsi_pll(struct intel_encoder *encoder,
 
 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		vlv_enable_dsi_pll(encoder, config);
-	else if (IS_BROXTON(dev_priv))
+	else if (IS_GEN9_LP(dev_priv))
 		bxt_enable_dsi_pll(encoder, config);
 }
 
@@ -542,7 +542,7 @@  void intel_disable_dsi_pll(struct intel_encoder *encoder)
 
 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		vlv_disable_dsi_pll(encoder);
-	else if (IS_BROXTON(dev_priv))
+	else if (IS_GEN9_LP(dev_priv))
 		bxt_disable_dsi_pll(encoder);
 }
 
@@ -566,7 +566,7 @@  void intel_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
-	if (IS_BROXTON(dev_priv))
+	if (IS_GEN9_LP(dev_priv))
 		bxt_dsi_reset_clocks(encoder, port);
 	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		vlv_dsi_reset_clocks(encoder, port);
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index fb88e32..034ec1a2 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1246,7 +1246,7 @@  hdmi_port_clock_valid(struct intel_hdmi *hdmi,
 		return MODE_CLOCK_HIGH;
 
 	/* BXT DPLL can't generate 223-240 MHz */
-	if (IS_BROXTON(dev_priv) && clock > 223333 && clock < 240000)
+	if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
 		return MODE_CLOCK_RANGE;
 
 	/* CHV DPLL can't generate 216-240 MHz */
@@ -1809,13 +1809,13 @@  static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
 
 	switch (port) {
 	case PORT_B:
-		if (IS_BROXTON(dev_priv))
+		if (IS_GEN9_LP(dev_priv))
 			ddc_pin = GMBUS_PIN_1_BXT;
 		else
 			ddc_pin = GMBUS_PIN_DPB;
 		break;
 	case PORT_C:
-		if (IS_BROXTON(dev_priv))
+		if (IS_GEN9_LP(dev_priv))
 			ddc_pin = GMBUS_PIN_2_BXT;
 		else
 			ddc_pin = GMBUS_PIN_DPC;
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 83f260b..1606e31 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -72,7 +72,7 @@  static const struct gmbus_pin gmbus_pins_bxt[] = {
 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
 					     unsigned int pin)
 {
-	if (IS_BROXTON(dev_priv))
+	if (IS_GEN9_LP(dev_priv))
 		return &gmbus_pins_bxt[pin];
 	else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
 		return &gmbus_pins_skl[pin];
@@ -87,7 +87,7 @@  bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
 {
 	unsigned int size;
 
-	if (IS_BROXTON(dev_priv))
+	if (IS_GEN9_LP(dev_priv))
 		size = ARRAY_SIZE(gmbus_pins_bxt);
 	else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
 		size = ARRAY_SIZE(gmbus_pins_skl);
diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
index 80bb924..eed0707 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -182,7 +182,7 @@  static bool get_mocs_settings(struct drm_i915_private *dev_priv,
 		table->size  = ARRAY_SIZE(skylake_mocs_table);
 		table->table = skylake_mocs_table;
 		result = true;
-	} else if (IS_BROXTON(dev_priv)) {
+	} else if (IS_GEN9_LP(dev_priv)) {
 		table->size  = ARRAY_SIZE(broxton_mocs_table);
 		table->table = broxton_mocs_table;
 		result = true;
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index be4b4d5..bf2899d 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -1756,7 +1756,7 @@  intel_panel_init_backlight_funcs(struct intel_panel *panel)
 	    intel_dsi_dcs_init_backlight_funcs(connector) == 0)
 		return;
 
-	if (IS_BROXTON(dev_priv)) {
+	if (IS_GEN9_LP(dev_priv)) {
 		panel->backlight.setup = bxt_setup_backlight;
 		panel->backlight.enable = bxt_enable_backlight;
 		panel->backlight.disable = bxt_disable_backlight;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index cc9e0c0..dcf5cd4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5228,7 +5228,7 @@  int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
 	if (!enable_rc6)
 		return 0;
 
-	if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
+	if (IS_GEN9_LP(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
 		DRM_INFO("RC6 disabled by BIOS\n");
 		return 0;
 	}
@@ -5262,7 +5262,7 @@  static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
 	/* All of these values are in units of 50MHz */
 
 	/* static values from HW: RP0 > RP1 > RPn (min_freq) */
-	if (IS_BROXTON(dev_priv)) {
+	if (IS_GEN9_LP(dev_priv)) {
 		u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
 		dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
 		dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
@@ -7642,7 +7642,7 @@  void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
 		dev_priv->display.init_clock_gating = skylake_init_clock_gating;
 	else if (IS_KABYLAKE(dev_priv))
 		dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
-	else if (IS_BROXTON(dev_priv))
+	else if (IS_GEN9_LP(dev_priv))
 		dev_priv->display.init_clock_gating = bxt_init_clock_gating;
 	else if (IS_BROADWELL(dev_priv))
 		dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 0599408..697574f 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -530,7 +530,7 @@  static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
 	u32 mask;
 
 	mask = DC_STATE_EN_UPTO_DC5;
-	if (IS_BROXTON(dev_priv))
+	if (IS_GEN9_LP(dev_priv))
 		mask |= DC_STATE_EN_DC9;
 	else
 		mask |= DC_STATE_EN_UPTO_DC6;
@@ -911,7 +911,7 @@  static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
 
 	gen9_assert_dbuf_enabled(dev_priv);
 
-	if (IS_BROXTON(dev_priv))
+	if (IS_GEN9_LP(dev_priv))
 		bxt_verify_ddi_phy_power_wells(dev_priv);
 }
 
@@ -2170,7 +2170,7 @@  static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
 	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
 		max_dc = 2;
 		mask = 0;
-	} else if (IS_BROXTON(dev_priv)) {
+	} else if (IS_GEN9_LP(dev_priv)) {
 		max_dc = 1;
 		/*
 		 * DC9 has a separate HW flow from the rest of the DC states,