| Message ID | 1480452310-29286-1-git-send-email-jeremy.linton@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, Nov 29, 2016 at 02:45:10PM -0600, Jeremy Linton wrote: > The PCIe root complex on Juno translates the MMIO mapped > at 0x5f800000 to the PIO address range starting at 0 > (which is common because PIO addresses are generally < 64k). > Correct the DT to reflect this. > > Signed-off-by: Jeremy Linton <jeremy.linton@arm.com> With the U-Boot patch that I have sent to the ML: Tested-by: Liviu Dudau <Liviu.Dudau@arm.com> also Acked-by: Liviu Dudau <Liviu.Dudau@arm.com> Best regards, Liviu > --- > arch/arm64/boot/dts/arm/juno-base.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi > index 334271a..7d3a2ac 100644 > --- a/arch/arm64/boot/dts/arm/juno-base.dtsi > +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi > @@ -393,7 +393,7 @@ > #address-cells = <3>; > #size-cells = <2>; > dma-coherent; > - ranges = <0x01000000 0x00 0x5f800000 0x00 0x5f800000 0x0 0x00800000>, > + ranges = <0x01000000 0x00 0x00000000 0x00 0x5f800000 0x0 0x00800000>, > <0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>, > <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>; > #interrupt-cells = <1>; > -- > 2.5.5 >
On Tue, Nov 29, 2016 at 02:45:10PM -0600, Jeremy Linton wrote: > The PCIe root complex on Juno translates the MMIO mapped > at 0x5f800000 to the PIO address range starting at 0 > (which is common because PIO addresses are generally < 64k). > Correct the DT to reflect this. > > Signed-off-by: Jeremy Linton <jeremy.linton@arm.com> > --- > arch/arm64/boot/dts/arm/juno-base.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> > diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi > index 334271a..7d3a2ac 100644 > --- a/arch/arm64/boot/dts/arm/juno-base.dtsi > +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi > @@ -393,7 +393,7 @@ > #address-cells = <3>; > #size-cells = <2>; > dma-coherent; > - ranges = <0x01000000 0x00 0x5f800000 0x00 0x5f800000 0x0 0x00800000>, > + ranges = <0x01000000 0x00 0x00000000 0x00 0x5f800000 0x0 0x00800000>, > <0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>, > <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>; > #interrupt-cells = <1>; > -- > 2.5.5 >
Hi Jeremy, On 29/11/16 20:45, Jeremy Linton wrote: > The PCIe root complex on Juno translates the MMIO mapped > at 0x5f800000 to the PIO address range starting at 0 > (which is common because PIO addresses are generally < 64k). > Correct the DT to reflect this. > I have another DT fix that I have asked ARM-SoC guys to pick up directly from the list. If that doesn't happen, I will send PR including both. If that happens then we need to send this to them to be picked directly. At this point I want to wait for couple of days to avoid confusion.
On Wednesday, November 30, 2016 4:29:35 PM CET Sudeep Holla wrote: > Hi Jeremy, > > On 29/11/16 20:45, Jeremy Linton wrote: > > The PCIe root complex on Juno translates the MMIO mapped > > at 0x5f800000 to the PIO address range starting at 0 > > (which is common because PIO addresses are generally < 64k). > > Correct the DT to reflect this. > > > > I have another DT fix that I have asked ARM-SoC guys to pick up directly > from the list. If that doesn't happen, I will send PR including both. > > If that happens then we need to send this to them to be picked directly. > At this point I want to wait for couple of days to avoid confusion. I ended up taking the other one for v4.10, but this one seems more important so I applied it for v4.9. Let me know if you disagree with the priorities, as I plan to send out the last 4.9 fixes pull request to Linus tomorrow. Arnd
On 30/11/16 22:51, Arnd Bergmann wrote: > On Wednesday, November 30, 2016 4:29:35 PM CET Sudeep Holla wrote: >> Hi Jeremy, >> >> On 29/11/16 20:45, Jeremy Linton wrote: >>> The PCIe root complex on Juno translates the MMIO mapped >>> at 0x5f800000 to the PIO address range starting at 0 >>> (which is common because PIO addresses are generally < 64k). >>> Correct the DT to reflect this. >>> >> >> I have another DT fix that I have asked ARM-SoC guys to pick up directly >> from the list. If that doesn't happen, I will send PR including both. >> >> If that happens then we need to send this to them to be picked directly. >> At this point I want to wait for couple of days to avoid confusion. > > I ended up taking the other one for v4.10, but this one seems more > important so I applied it for v4.9. > > Let me know if you disagree with the priorities, as I plan to send out > the last 4.9 fixes pull request to Linus tomorrow. > No that's fine.
diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi index 334271a..7d3a2ac 100644 --- a/arch/arm64/boot/dts/arm/juno-base.dtsi +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi @@ -393,7 +393,7 @@ #address-cells = <3>; #size-cells = <2>; dma-coherent; - ranges = <0x01000000 0x00 0x5f800000 0x00 0x5f800000 0x0 0x00800000>, + ranges = <0x01000000 0x00 0x00000000 0x00 0x5f800000 0x0 0x00800000>, <0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>, <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>; #interrupt-cells = <1>;
The PCIe root complex on Juno translates the MMIO mapped at 0x5f800000 to the PIO address range starting at 0 (which is common because PIO addresses are generally < 64k). Correct the DT to reflect this. Signed-off-by: Jeremy Linton <jeremy.linton@arm.com> --- arch/arm64/boot/dts/arm/juno-base.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)