| Message ID | 1480937130-24561-7-git-send-email-nikunj@linux.vnet.ibm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 12/05/2016 03:25 AM, Nikunj A Dadhania wrote: > + getVSR(xt_num, &xt, env); > + if (msr_le) { > + for (i = 0; i < end; i++) { > + cpu_stb_data_ra(env, addr, xt.u8[i], GETPC()); > + addr = addr_add(env, addr, 1); > + } > + } else { > + for (i = 15; i > 15 - end; i--) { > + cpu_stb_data_ra(env, addr, xt.u8[i], GETPC()); > + addr = addr_add(env, addr, 1); > + } > + } Have you accidentally swapped the implementations of stxvl and stxvll? r~
Richard Henderson <rth@twiddle.net> writes: > On 12/05/2016 03:25 AM, Nikunj A Dadhania wrote: >> + getVSR(xt_num, &xt, env); >> + if (msr_le) { >> + for (i = 0; i < end; i++) { >> + cpu_stb_data_ra(env, addr, xt.u8[i], GETPC()); >> + addr = addr_add(env, addr, 1); >> + } >> + } else { >> + for (i = 15; i > 15 - end; i--) { >> + cpu_stb_data_ra(env, addr, xt.u8[i], GETPC()); >> + addr = addr_add(env, addr, 1); >> + } >> + } > > Have you accidentally swapped the implementations of stxvl and stxvll? Now I am in doubt :-) Let me put my understanding here. In case of stxvl if we have following vector: +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+ BE |“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|00|00| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+ +--+--+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ LE |00|00|“T”|“S”|“E”|“T”|“ ”|“a”|“ ”|“s”|“i”|“ ”|“s”|“i”|"h"|"T"| +--+--+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ So for LE/BE: u[0] = "T", u[1] = "h", u[2] = "i", u[3] = "s", .... Storage should be of following order: +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+ |“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|FF|FF| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+ While in case of stxvll +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+ BE/LE |“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|00|00| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+ For LE: u[0] = 0, u[1] = 0, u[2] = "T", u[3] = "S", .... For BE: u[0] = "T", u[1] = "h", u[2]="i", u[3]="s", .... Storage should be of following order: +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+ |“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|FF|FF| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+ Please let me know your thoughts. While discussing here with Bharata, I think I will need to handle host endian here? Regards, Nikunj
diff --git a/target-ppc/helper.h b/target-ppc/helper.h index 5ddc96d..91bdfc3 100644 --- a/target-ppc/helper.h +++ b/target-ppc/helper.h @@ -320,6 +320,7 @@ DEF_HELPER_3(stvewx, void, env, avr, tl) DEF_HELPER_4(lxvl, void, env, tl, tl, tl) DEF_HELPER_4(lxvll, void, env, tl, tl, tl) DEF_HELPER_4(stxvl, void, env, tl, tl, tl) +DEF_HELPER_4(stxvll, void, env, tl, tl, tl) DEF_HELPER_4(vsumsws, void, env, avr, avr, avr) DEF_HELPER_4(vsum2sws, void, env, avr, avr, avr) DEF_HELPER_4(vsum4sbs, void, env, avr, avr, avr) diff --git a/target-ppc/mem_helper.c b/target-ppc/mem_helper.c index 6227c4d..b9885a8 100644 --- a/target-ppc/mem_helper.c +++ b/target-ppc/mem_helper.c @@ -351,6 +351,31 @@ void helper_stxvl(CPUPPCState *env, target_ulong addr, } } +void helper_stxvll(CPUPPCState *env, target_ulong addr, + target_ulong xt_num, target_ulong rb) +{ + int i; + ppc_vsr_t xt; + target_ulong end = rb & 0xFF; + + if (!end) { + return; + } + + getVSR(xt_num, &xt, env); + if (msr_le) { + for (i = 0; i < end; i++) { + cpu_stb_data_ra(env, addr, xt.u8[i], GETPC()); + addr = addr_add(env, addr, 1); + } + } else { + for (i = 15; i > 15 - end; i--) { + cpu_stb_data_ra(env, addr, xt.u8[i], GETPC()); + addr = addr_add(env, addr, 1); + } + } +} + #undef HI_IDX #undef LO_IDX diff --git a/target-ppc/translate/vsx-impl.inc.c b/target-ppc/translate/vsx-impl.inc.c index d8e2ab4..d2d931c 100644 --- a/target-ppc/translate/vsx-impl.inc.c +++ b/target-ppc/translate/vsx-impl.inc.c @@ -268,6 +268,7 @@ static void gen_##name(DisasContext *ctx) \ VSX_VECTOR_LOAD_STORE_LENGTH(lxvl) VSX_VECTOR_LOAD_STORE_LENGTH(lxvll) VSX_VECTOR_LOAD_STORE_LENGTH(stxvl) +VSX_VECTOR_LOAD_STORE_LENGTH(stxvll) #define VSX_LOAD_SCALAR_DS(name, operation) \ static void gen_##name(DisasContext *ctx) \ diff --git a/target-ppc/translate/vsx-ops.inc.c b/target-ppc/translate/vsx-ops.inc.c index 1a980d6..f315580 100644 --- a/target-ppc/translate/vsx-ops.inc.c +++ b/target-ppc/translate/vsx-ops.inc.c @@ -24,6 +24,7 @@ GEN_HANDLER_E(stxvh8x, 0x1F, 0x0C, 0x1D, 0, PPC_NONE, PPC2_ISA300), GEN_HANDLER_E(stxvb16x, 0x1F, 0x0C, 0x1F, 0, PPC_NONE, PPC2_ISA300), GEN_HANDLER_E(stxvx, 0x1F, 0x0C, 0x0C, 0, PPC_NONE, PPC2_ISA300), GEN_HANDLER_E(stxvl, 0x1F, 0x0D, 0x0C, 0, PPC_NONE, PPC2_ISA300), +GEN_HANDLER_E(stxvll, 0x1F, 0x0D, 0x0D, 0, PPC_NONE, PPC2_ISA300), GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207), GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
stxvll: Store VSX Vector Left-justified with Length Vector (8-bit elements) in LE/BE: +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+ |“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|00|00| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+ Storing 14 bytes would result in following Little/Big-endian Storage: +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+ |“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|FF|FF| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+ Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> --- target-ppc/helper.h | 1 + target-ppc/mem_helper.c | 25 +++++++++++++++++++++++++ target-ppc/translate/vsx-impl.inc.c | 1 + target-ppc/translate/vsx-ops.inc.c | 1 + 4 files changed, 28 insertions(+)